NCV7343D20R2G

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The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. The NCV7343 is an addition to the CAN high−speed transceiver family complementing NCV734x CAN stand−alone transceivers and previous generations such as AMIS42665, AMIS3066x, etc. The NCV7343 guarantees additional timing parameters to ensure robust communication at data rates beyond 1 Mbit/s to cope with CAN flexible data rate requirements (CAN FD). These features make the NCV7343 an excellent choice for all types of HS−CAN networks, in nodes that require a low−power mode with wake−up capability via the CAN bus. 14 1 1 SOIC−14 D2 SUFFIX CASE 751A−03 MARKING DIAGRAMS NCV7343D20 14 Features • • • • • • • • • • • • • • • • • • Compliant with International Standard ISO11898−2:2016 CAN FD Timing Specified up to 5 Mbit/s Extended Bus Load Range Standby and Sleep Mode with very Low Current Consumption CAN Wake−up with Wake−up Pattern (WUP), Short CAN Activity Filter Time, Long Wake−up Timeout and Normal Bus Biasing. Local Wake−up VIO Pin Allowing Direct Interfacing with 3 V to 5 V MCUs Low Electromagnetic Emission (EME) and High Electromagnetic Susceptibility (EMS) High Impedance Bus Lines in Unpowered State Transmit Data (TxD) Dominant Timeout Function (Long) Bus Error Detection Under all Supply Conditions the Chip behaves Predictably ESD Robustness of Bus Pins > 8 kV Thermal Protection Bus Pins Short Circuit Proof to Supply Voltage and Ground Bus Pins Protected against Transients in an Automotive Environment AEC−Q100 Grade 0 Qualified and PPAP Capable These are Pb−Free Devices DFNW14 4.5x3, 0.65P MW SUFFIX CASE 507AC NCV7343MW0 8 1 NCV7343 AWLYWWG 7 1 7 NCV7343D21 14 1 NCV7343−1 AWLYWWG 7 7 SOIC−14 A (W)L YW(W) G or G NCV 7343 ALYW G 8 NCV7343MW1 8 1 14 14 NCV7 343−1 ALYW G 8 DFNW14 = Assembly Site = Wafer Lot = Date Code = Pb−Free Identification ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 21 of this data sheet. Quality • Wettable Flank Package for Enhanced Optical Inspection Typical Applications • Automotive • Industrial Networks © Semiconductor Components Industries, LLC, 2020 July, 2021 − Rev. 1 1 Publication Order Number: NCV7343/D NCV7343 TYPICAL APPLICATION VBAT IN VIO 3V3 / 5V VCC 5V OUT INH OUT VCC VIO Host Interface INH CVCC CVIO VDD RPP IN INH STBN EN ERRN MCU CVB RWAKE1 ECU VB WAKE WAKE RWAKE2 NCV7343 CANH CMC CANL CAN Controller TxD RxD CAN 2x RT GND VSS GND CST Figure 1. Typical Application Diagram RECOMMENDED EXTERNAL COMPONENTS FOR THE APPLICATIONS DIAGRAM Symbol Parameter Value Unit 100 nF Note CVB Decoupling Capacitor on VB Supply Pin, Ceramic CVCC Decoupling Capacitor on VCC Supply Pin, Ceramic 1 mF CVIO Decoupling Capacitor on VIO Supply Pin, Ceramic 100 nF RWAKE1 WAKE Pin Pull−up Resistor 33 kW RWAKE2 WAKE Pin Serial Protection Resistor 3.3 kW CMC Common Mode Choke 100 mH (Note 1) RLT Terminating Resistors 60 W < 1%, ≥ 0.25 W CST Common−mode Stabilization Capacitor, Ceramic 4.7 nF < 20%, 50 V 1. Murata DLW32SH101XF2, Murata DLW32SH101XK2, TDK ACT45B−101−2P, TDK ACT1210R−101−2P www.onsemi.com 2 NCV7343 BLOCK DIAGRAM VIO VCC 5 INH 3 VB 7 10 VIO ERRN STBN EN Local Wakeup Control 8 9 WAKE 13 CANH 12 CANL 14 Thermal Shutdown 6 VCC NCV7343 Mode control + Wake control + Error detection VIO TxD 1 Driver control Tx Timeout VIO RxD Wake−up Filter COMP Rx Timeout COMP 4 VCC/2 OSC UV 11 2 GND NC Figure 2. NCV7343 Block Diagram www.onsemi.com 3 NCV7343 PIN CONNECTIONS 1 14 GND 2 13 VCC 3 RxD 4 EN INH 5 6 TxD 1 14 STBN CANH GND 2 13 CANH 12 CANL VCC 3 12 CANL 11 NC RxD 4 11 NC 10 VB VIO 5 10 VB WAKE EN 6 9 WAKE 8 ERRN 9 8 7 STBN INH ERRN NCV7343MW VIO NCV7343D2 TxD EP 7 (Top View) (Top View) Figure 4. Pin Connections − DFNW14 Figure 3. Pin Connections − SOIC−14 PIN FUNCTION DESCRIPTION Pin Name Description 1 TxD Transmit data input; low input " dominant driver; internal pull−up current 2 GND Ground 3 VCC Supply voltage 4 RxD Receive data output; dominant transmitter " low output 5 VIO Input / Output pins supply voltage 6 EN Enable mode control input; internal pull−down current 7 INH High voltage output for controlling external voltage regulators 8 ERRN Digital output indicating errors and power−up; active low 9 WAKE Local wake−up input 10 VB Battery supply connection 11 NC Not connected 12 CANL Low−level CAN bus line (low in dominant mode) 13 CANH High−level CAN bus line (high in dominant mode) 14 STBN Standby mode control input; internal pull−down current 15 EP Exposed Pad. Recommended to connect to GND or left floating in application (DFNW14 package only) MAXIMUM RATINGS Symbol Parameter Conditions Min Max Unit VB Supply Voltage, Pin VB (Note 2) −0.3 +40 V VSUP Supply Voltage, Pin VCC, VIO (Note 2) −0.3 +6.0 V VCAN DC Voltage at Pins CANH and CANL 0 < VCC < 5.5 V −42 +42 V VDIFF DC Voltage between Any Two Pins (Including CANH and CANL) −42 +42 V VDIG_IN DC Voltage at Pin TxD, STBN, EN −0.3 +40 V VDIG_OUT DC Voltage at Pin RxD, ERRN −0.3 VIO + 0.3 V VINH DC Voltage at Pin INH −0.3 VB + 0.3 V IINH DC Current on INH Pin −5 0 mA VWAKE DC Voltage at Pin WAKE −42 +42 V VESD_IEC Electrostatic Discharge Voltage at Pins CANH, CANL, VB and WAKE; System HBM, According to IEC 61000−4−2. (Note 3) −8 +8 kV VESD_HBM Electrostatic Discharge Voltage at Pins CANH, CANL, VB and WAKE; Component HBM, According to JEDEC JESD22−A114. (Note 4) −8 +8 kV www.onsemi.com 4 NCV7343 MAXIMUM RATINGS (continued) Symbol Parameter Conditions Max Unit −4 +4 kV −750 +750 V VESD_INT Electrostatic Discharge Voltage at All Other Pins; Component HBM, According to JEDEC JESD22−A114. VESD_CDM Electrostatic Discharge Voltage at All Pins; Component CDM, According to JEDEC JESD22−C101. VESD_MM Electrostatic Discharge Voltage at All Pins; Component MM, According to JEDEC JESD22−A115. (Note 5) −200 +200 V VTRAN Voltage Transients, Pins CANH, CANL. Test Pulses According to ISO7637−2, Class C, (Note 6) Test pulses 1 −100 − V Test pulses 2a − +75 V Test pulses 3a −150 − V Test pulses 3b − +100 V Test pulse 5 Load dump − 40 V Voltage Transients, Pin VB, According to ISO7637−2 (Note 4) Min Latch−up Static Latch−up at All Pins, According to JEDEC JESD78 − 150 mA TJ Maximum Junction Temperature −40 +160 °C TSTG Storage Temperature −55 +150 °C MSL Moisture Sensitivity Level 260 °C TSLD SOIC−14 2 DFNW14 1 Peak Soldering Temperature (Note 7) − Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 3. Equivalent to discharging a 150 pF capacitor through a 330 W resistor, referenced to GND. WAKE pin stressed through an external series resistor 3.3 kW and with 10 nF capacitor on the module input. VB pin decoupled with 100 nF during stressing. Results were verified by an external test house. 4. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor. 5. Equivalent to discharging a 200 pF capacitor through a 10 W resistor and 0.75 mH coil. 6. Results were verified by an external test house. 7. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Characteristics, SOIC−14 (Note 8) Thermal Resistance Junction−to−Air, (Note 9) Thermal Resistance Junction−to−Air, (Note 10) RqJA_1 RqJA_2 100 63 K/W Thermal Characteristics, DFNW14 (Note 8) Thermal Resistance Junction−to−Air, (Note 9) Thermal Resistance Junction−to−Air, (Note 10) RqJA_1 RqJA_2 115 65 K/W 8. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 9. Test board according to EIA/JEDEC Standard JESD51−3 (1S0P PCB), signal layer with 10% trace coverage. 10. Test board according to EIA/JEDEC Standard JESD51−7 (2S2P PCB), signal layers with 10% trace coverage. RECOMMENDED OPERATING RANGES Symbol Parameter Conditions Min Max Unit VB Supply Voltage, Pin VB 5.0 40 V VCC Supply Voltage, Pin VCC 4.5 5.5 V VIO Supply Voltage, Pin VIO 2.8 5.5 V VCAN DC Voltage at Pins CANH and CANL −36 36 V VDIG_IN DC Voltage at Pins TxD, STBN, and EN 0 5.5 V VDIG_OUT DC Voltage at Pins RxD and ERRN 0 VIO V VINH DC Voltage at Pin INH 0 VB V IINH DC Current on Pin INH −1 0 mA www.onsemi.com 5 NCV7343 RECOMMENDED OPERATING RANGES (continued) Symbol Parameter Conditions Min Max Unit VWAKE DC Voltage at Pin WAKE −42 VB V TJ Junction Temperature −40 150 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V; VB= 5.0 V to 40 V; for typical values TA = 25°C, for min/max values TJ = −40 to +150°C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2). Positive current flow into the respective pin) Symbol Parameter Conditions Min Typ Max Unit 4.5 − 5.5 V Normal mode, Dominant, VTxD = 0 V − 47 61 mA Normal mode, Recessive, VTxD = VIO − 3.2 6.2 mA Silent mode, Recessive − 1.0 3.2 mA Normal mode, Dominant, VTxD = 0 V, one of bus wires shorted (Note 11) −3 V ≤ VCANH, VCANL ≤ +18 V − − 103 mA Standby or Sleep mode, VCC = 5 V VB > VCC, TJ ≤ 100°C (Note 11) − 11 20 mA VCC SUPPLY (Pin VCC) VCC Power Supply Voltage ICC Supply Current ICC_LP Supply Current in Low−power Modes (Standby or Sleep Mode) Vuv_VCC Undervoltage Detection Threshold 3.5 3.8 4.3 V Vuvh_VCC Undervoltage Threshold Hysteresis − 120 − mV VIO SUPPLY VOLTAGE (Pin VIO) VIO Supply Voltage on Pin VIO 2.8 − 5.5 V IIO Normal−power Mode Supply Current Normal or Silent mode; VTxD = 0 V − 110 300 mA Normal or Silent mode, VTxD = VIO − 1.5 7.0 mA IIO_LP Low−power Mode Supply Current Standby or Sleep mode; VTxD = VIO; TJ ≤ 100°C (Note 11) − 1.0 4.0 mA Vuv_VIO Undervoltage Detection Threshold 2.0 2.2 2.8 V Vuvh_VIO Undervoltage Threshold Hysteresis − 280 − mV VB SUPPLY VOLTAGE (Pin VB) VB Supply Voltage on Pin VB 5.0 − 40 V IB Normal−power Mode Supply Current Normal and Silent mode; VB = 5 V to 38 V − 3.5 7.0 mA IB_LP Low−power Mode Supply Current Standby mode VWAKE = VB; VB = 5 V to 38 V − 3.5 7.0 mA Sleep mode VVCC = VVIO = 0 V, VWAKE = VB; VB = 5 V to 38 V TJ ≤ 100°C (Note 11) − 13 20 mA Sleep and Standby Mode VVCC = VVIO = 5 V, VB = 5 V to 38 V TJ ≤ 100°C (Note 11) − 14 23 mA IB_LP_VB&VCC Sum of Low−power Mode Supply Current to Battery and VCC Pin www.onsemi.com 6 NCV7343 ELECTRICAL CHARACTERISTICS (VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V; VB= 5.0 V to 40 V; for typical values TA = 25°C, for min/max values TJ = −40 to +150°C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2). Positive current flow into the respective pin) (continued) Symbol Parameter Conditions Min Typ Max Unit VB SUPPLY VOLTAGE (Pin VB) Vuvd_VB Undervoltage Detection Threshold VB falling 3.7 4.1 4.5 V Vuvr_VB Undervoltage Recovery Threshold VB rising 3.9 4.4 4.9 V Vuvh_VB Undervoltage Threshold Hysteresis 100 300 400 mV 2.0 − − V TRANSMITTER DATA INPUT (PIN TxD) VIH High−level Input Voltage Output recessive VIL Low−level Input Voltage Output dominant IIH High−level Input Current VTxD = VIO RPU Pull−up Resistor ILEAK Leakage Current VTxD = 5.5 V, VIO = 0 V Ci Input Capacitance (Note 11) − − 0.8 V −5.0 0 +5.0 mA 10 25 50 kW −1.0 0 +1.0 mA − 5 10 pF RECEIVER DATA OUTPUT (Pin RxD) IOH High−level Output Current VRxD = VIO − 0.4 V −8.0 −3.0 −1.0 mA IOL Low−level Output Current VRxD = 0.4 V 1.0 6.0 12 mA TRANSMITTER MODE SELECT (Pin STBN, EN) VIH High−level Input Voltage Standby mode 2.0 − − V VIL Low−level Input Voltage Normal mode − − 0.8 V RPD Pull−down Resistor 300 650 1000 kW IIL Low−level Input Current VSTBN = 0 V −1.0 0 +1.0 mA ILEAK Leakage Current VSTBN = 5.5 V, VB = VCC = VIO = 0 V −1.0 0 +1.0 mA Ci Input Capacitance (Note 11) − 5 10 pF −100 −50 −10 mA 0.1 0.5 1.0 mA ERROR SIGNALING (Pin ERRN) IOH High Level Output Current VERRN = VIO − 0.4 V IOL Low Level Output Current VERRN = 0.4 V LOCAL WAKE−UP INPUT (Pin WAKE) VIH High−level Input Voltage Standby or Sleep VB − 2 − − V VIL Low−level Input Voltage Standby or Sleep − − VB − 4 V IIH High−level Input Current VWAKE = VB − 2 V; VWAKE = High for t ≥ twake_filt (Pull−up active) −11 − −3.0 mA IIL Low−level Input Current VWAKE = VB − 4 V; VWAKE = Low for t ≥ twake_filt (Pull−down active) 3.0 − 11 mA VB − 0.6 VB − 0.27 VB − 0.1 V −5 0 +5 mA 2.75 3.65 4.5 V INHIBIT OUTPUT (Pin INH) VOH High−level Output Voltage IINH = −1 mA ILEAK Leakage Current Sleep or Power−off mode, VINH = 0 V CAN TRANSMITTER (Pins CANH and CANL) Vo(dom)(CANH) Dominant Output Voltage at Pin CANH Normal mode; VTxD = Low; t < tdom(TxD); 45 W ≤ RLT ≤ 65 W www.onsemi.com 7 NCV7343 ELECTRICAL CHARACTERISTICS (VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V; VB= 5.0 V to 40 V; for typical values TA = 25°C, for min/max values TJ = −40 to +150°C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2). Positive current flow into the respective pin) (continued) Symbol Parameter Conditions Min Typ Max Unit CAN TRANSMITTER (Pins CANH and CANL) Vo(dom)(CANL) Dominant Output Voltage at Pin CANL Normal mode; VTxD = Low; t < tdom(TxD); 45 W ≤ RLT ≤ 65 W 0.5 1.35 2.25 V Vo(rec) Recessive Output Voltage at Pins CANH and CANL Normal or Silent mode; VTxD = High or VTxD = Low and t > tdom(TxD); no load 2.0 2.5 3.0 V Vo(off) Recessive Output Voltage at Pins CANH and CANL Standby or Sleep mode; no load −0.1 0 +0.1 V Vo(dom)(diff) Differential Dominant Output Voltage (VCANH − VCANL) Normal mode; VTxD = Low; t < tdom(TxD); 50 W ≤ RLT ≤ 65 W 1.5 2.3 3.0 V Normal mode; VTxD = Low; t < tdom(TxD); 45 W ≤ RLT ≤ 70 W 1.4 2.3 3.3 V Normal mode; VTxD = Low; t < tdom(TxD); RLT = 2 240 W 1.5 − 5.0 V Vo(dom)(diff)_E Vo(dom)(diff)_ARB Vo(rec)(diff) Differential Recessive Output Voltage (VCANH − VCANL) Normal or Silent mode; VTxD = High or VTxD = Low and t > tdom(TxD); no load −50 0 +50 mV Vo(off)(diff) Differential Recessive Output Voltage (VCANH − VCANL) Standby or Sleep Mode; no load −0.2 0 +0.2 V Vo(sym) Driver Output Voltage Symmetry Vo(sym) = VCANH + VCANL TxD = square wave up to 1 MHz; CST = 4.7 nF 0.9 1.0 1.1 VCC Io(sc)(CANH) Short Circuit Output Current at Pin CANH in Dominant Normal mode; VTxD = Low, t < tdom(TxD); −3 V ≤ VCANH ≤ +18 V NCV7343xx0 NCV7343xx1 Io(sc)(CANL) Io(sc)(rec) Short Circuit Output Current at Pin CANL in Dominant Short Circuit Output Current at Pins CANH and CANL in Recessive Normal mode; VTxD = Low, t < tdom(TxD); −3 V ≤ VCANL ≤ +36 V NCV7343xx0 NCV7343xx1 Normal or Silent mode; −27 V < VCANH, VCANL < +32 V NCV7343xx0 NCV7343xx1 mA −100 −100 −70 −70 +2.0 +5.0 mA −2.0 −2.0 +70 +70 +100 +100 mA −3.0 −6.0 − − +3.0 +6.0 0 W < R(VCC to GND) < 1 MW VCANH = VCANL = 5 V −5.0 0 +5.0 mA VB = VCC = VIO = 0 V VCANH = VCANL = 5 V −5.0 0 +5.0 mA Normal or Silent mode; −12 V ≤ VCANH, VCANL ≤ +12 V; no load −3.0 − +0.5 V Standby or Sleep mode; −12 V ≤ VCANH, VCANL ≤ +12 V; no load −3.0 − +0.4 V Normal or Silent mode; −12 V ≤ VCANH, VCANL ≤ +12 V; no load 0.9 − 8.0 V Standby or Sleep mode; −12 V ≤ VCANH, VCANL ≤ +12 V; no load 1.05 − 8.0 V CAN RECEIVER (Pins CANH and CANL) ILEAK(off) Vi(rec)(diff)_NM Input Leakage Current Differential Input Voltage Range Recessive State Vi(rec)(diff)_LP Vi(dom)(diff)_NM Vi(dom)(diff)_LP Differential Input Voltage Range Dominant State www.onsemi.com 8 NCV7343 ELECTRICAL CHARACTERISTICS (VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V; VB= 5.0 V to 40 V; for typical values TA = 25°C, for min/max values TJ = −40 to +150°C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2). Positive current flow into the respective pin) (continued) Symbol Parameter Conditions Min Typ Max Unit Normal or Silent mode; −12 V ≤ VCANH, VCANL ≤ +12 V; no load 0.5 − 0.9 V Vi(th)(diff)_NM_E Normal or Silent mode; Extended, −30 V ≤ VCANH, VCANL ≤ +35 V; no load 0.4 − 1.0 V Vi(th)(diff)_LP Standby or Sleep mode; −12 V ≤ VCANH, VCANL ≤ +12 V; no load 0.4 − 1.05 V CAN RECEIVER (Pins CANH and CANL) Vi(th)(diff)_NM Differential Receiver Threshold Voltage Ri(cm) Common−mode Input Resistance at Pins CANH and CANL −2 V ≤ VCANH, VCANL ≤ +7 V 6.0 − 50 kW Ri(cm)(m) Matching between Pin CANH and Pin CANL Common Mode Input Resistance VCANH = VCANL = +5 V −1 0 +1 % Ri(diff) Differential Input Resistance Ri(diff) = Ri(cm)(CANH) + Ri(cm)(CANL) −2 V ≤ VCANH, VCANL ≤ +7 V 12 − 100 kW Ci Input Capacitance at Pins CANH and CANL VTxD = High; (Note 11) − 7.5 20 pF Ci(diff) Differential Input Capacitance VTxD = High; (Note 11) − 3.75 10 pF 160 180 200 °C 2.0 3.5 6.0 °C THERMAL SHUTDOWN TJSD Shutdown Junction Temperature TJSD_HYST Shutdown Junction Temperature Hysteresis Junction temperature rising TIMING CHARACTERISTICS (see Figure 18) td(TxD−BUSon) Propagation Delay TxD to Bus Active Normal mode (Note 12, Figure 16) − 75 − ns td(TxD−BUSoff) Propagation Delay TxD to Bus Inactive Normal mode (Note 12, Figure 16) − 85 − ns td(BUSon−RxD) Propagation Delay Bus Active to RxD Normal or Silent mode (Note 12, Figure 16) − 25 − ns td(BUSoff−RxD) Propagation Delay Bus Inactive to RxD Normal or Silent mode (Note 12, Figure 16) − 35 − ns tpd_dr Propagation Delay TxD to RxD Dominant to Recessive Transition Normal mode (Note 12, Figure 17) tbit(TxD) = 200 ns / 500 ns / 1000 ns 50 100 170 ns tpd_rd Propagation Delay TxD to RxD Recessive to Dominant Transition Normal mode (Note 12, Figure 17) tbit(TxD) = 200 ns / 500 ns / 1000 ns 50 120 170 ns tdom(TxD) TxD Dominant Timeout Normal mode; VTxD = Low 1.2 2.4 6.0 ms ten(TxD) Transmitter Activation Time after Clearing TxD Dominant Timeout Flag Condition Normal mode 7.0 − 50 ms tdom(BUS) Bus Dominant Timeout Normal or Silent mode; bus dominant 1.5 2.8 6.5 ms ten(RxD) Receiver Activation Time after Clearing Bus Dominant Timeout Flag Condition Normal or Silent mode 14 − 50 ms tbit(RxD) Bit Time on RxD Pin tbit(TxD) = 500 ns (Note 12, Figure 17) 400 − 550 ns tbit(TxD) = 200 ns (Note 12, Figure 17) 120 − 220 ns www.onsemi.com 9 NCV7343 ELECTRICAL CHARACTERISTICS (VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V; VB= 5.0 V to 40 V; for typical values TA = 25°C, for min/max values TJ = −40 to +150°C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2). Positive current flow into the respective pin) (continued) Symbol Parameter Conditions Min Typ Max Unit Bit Time on Bus Pins (CANH − CANL) tbit(TxD) = 500 ns (Note 12, Figure 17) 435 − 530 ns tbit(TxD) = 200 ns (Note 12, Figure 17) 155 − 210 ns Receiver Timing Symmetry Dtrec = tbit(RxD) − tbit(Vi(diff)) tbit(TxD) = 500 ns (Note 12, Figure 17) −65 − +40 ns tbit(TxD) = 200 ns (Note 12, Figure 17) −45 − +15 ns td(startup) Power−on Event Device Sartup Time VB > Vuvr_VB to Standby Mode Delay (Figure 5) − − 100 ms td(mode) Operating Mode Change Delay Mode change by STBN/EN pins (Figure 7 and Figure 8) 7.0 16 50 ms td(mode_wake) Mode change after local wake−up (Figure 12 and Figure 13) 10 16 38 ms td(mode_wup) Mode change after remote wake−up (Figure 14) 10 22 63 ms TIMING CHARACTERISTICS (see Figure 18) tbit(Vi(diff)) Dtrec th(mode) Operating Mode Change Hold Time Figure 7 and Figure 8 3.0 − 50 ms th(go−to−sleep) Go−to−Sleep Mode Entering Hold Time STBN = Low, EN = High (Figure 9) 3.0 − 50 ms td(wake_startup) Power−on Event WAKE Pin Enable Time Standby mode to WAKE input enable delay (Power−on event only) (Figure 5) 40 70 200 ms twake_filt WAKE Pin Input Filter Time Standby or Sleep mode (Figure 12 and Figure 13) 5.0 21 60 ms td(wake_flg) Wake−up Flag Set Delay Time Local wake−up detected, Standby or Sleep mode (Figure 12 and Figure 13) 3.0 5.5 13 ms twup_filt Bus Wake−up Pattern Filter Time (Short) Standby or Sleep mode (Figure 14) 0.15 − 1.8 ms twup_to Bus Wake−up Pattern Timeout Standby or Sleep mode (Figure 14) 1.0 2.0 5.0 ms td(wup_flg) Wake−up Flag Set Delay Time Remote wake−up detected, Standby or Sleep mode (Figure 14) 3.0 11 38 ms tuv_det Transmitter Deactivation Time after VCC or VIO Undervoltage Condition Detection VCC < Vuvd_VCC or VIO < Vuvd_VIO (Figure 6) − 0.7 − ms tuv_rec Transmitter Activation Time after VCC and VIO Undervoltage Condition Removal VCC > Vuvr_VCC and VIO > Vuvr_VIO (Figure 6) 14 25 75 ms tuvd_VCC VCC Undervoltage Detection Timeout VCC < Vuvd_VCC to VCC UV flag set 100 160 400 ms tuvd_VIO VIO Undervoltage Detection Timeout VIO < Vuvd_VIO to VIO UV flag set 100 160 400 ms tuvr_VCC VCC Undervoltage Recovery Timeout VCC > Vuvr_VCC to VCC UV flag reset 0.35 0.6 1.3 ms tuvr_VIO VIO Undervoltage Recovery Timeout VIO > Vuvr_VIO to VIO UV flag reset 0.35 0.6 1.3 ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 11. Values based on design and characterization, not tested in production. 12. CLT = 100 pF, CST not present, CRxD = 15 pF www.onsemi.com 10 NCV7343 FUNCTIONAL DESCRIPTION POWER SUPPLY In Normal mode, the transmitter is disabled tuv_det after VCC or VIO voltage falls below respective undervoltage detection thresholds. The transmitter is re−enabled tuv_rec after both VCC and VIO voltage rises above the undervoltage recovery thresholds (Figure 6). VB undervoltage is detected if VB supply voltage falls below undervoltage detection threshold, Vuvd_VB. VB undervoltage recovery is detected if VB supply voltage rises above the undervoltage recovery threshold, Vuvr_VB. VCC undervoltage flag is set if VCC supply voltage is lower than Vuv_VCC for longer than VCC undervoltage detection time tuvd_VCC. VCC undervoltage recovery is detected and the flag is reset if VCC supply voltage is higher than Vuv_VCC for longer than VCC undervoltage recovery time tuvr_VCC. Similarly, VIO undervoltage flag is set if VIO supply voltage is lower than Vuv_VIO for longer than VIO undervoltage detection time tuvd_VIO. VIO undervoltage recovery is detected and the flag is reset if VIO supply voltage is higher than Vuv_VIO for longer than VIO undervoltage recovery time tuvr_VIO. Both VCC and VIO undervoltage flags and the undervoltage detection timers are also reset after local or remote wake−up detection event or STBN pin rising edge detection in Sleep mode. Once the VCC and/or VIO undervoltage flag is set the device changes to Sleep mode. The Sleep mode can be left and the operation mode control by STBN and EN pin is re−enabled as soon as both VCC and VIO supplies are recovered. The operating mode control state machine is not reset when an undervoltage condition is detected. Thus if Sleep mode was requested by the host prior to VCC and/or VIO undervoltage condition detection and the EN pin was set Low in Sleep mode, the device stays in Sleep once the undervoltage is recovered, although STBN and EN pins are both set Low, which is otherwise considered a Standby mode request. NCV7343 implements three power supply inputs – battery supply input VB, CAN transceiver supply input VCC and digital IOs supply input VIO. VB Supply Pin VB is the main supply pin of the NCV7343. The NCV7343 proceeds from Power−off mode to Standby mode as soon as the VB supply is available. This supply input is used to provide the minimum power required for the operation in case of absence of the remaining supplies. Typically this is the only active supply in a low−power Sleep mode providing power supply to the low−power wake−up detector. VCC Supply Pin VCC pin is the CAN transceiver main supply input in Normal and Silent mode. VIO Supply Pin Digital pins interfacing with the microcontroller have a separate IO supply. The VIO pin should be connected to microcontroller supply pin. By using VIO supply pin shared with microcontroller the IO levels between microcontroller and transceiver are properly adjusted. See Figure 1. VB Vuvr_VB td(startup) STBN EN td(mode) Power off INH Standby Normal < tuvd_VCC/VIO VCC Normal mode VIO < tuvd_VCC/VIO VCC or VIO td(wake_startup) Vuv_VCC/VIO tuv_det WAKE disabled > tuv_rec enabled Transmitter active Figure 5. Typical Power−up Sequence disabled active TxD Power Supplies Monitoring CAN VB, VCC and VIO supply inputs are monitored by undervoltage detectors with individual thresholds and filtering times both for undervoltage detection and undervoltage recovery. Figure 6. Transmitter Deactivation/Activation in Case of Undervoltage Event www.onsemi.com 11 NCV7343 INH Pin disabled, CAN bus pins are left floating and the INH pin is deactivated. The RxD pin is left High at VIO level. As soon as the VB voltage rises above battery undervoltage recovery threshold Vuvr_VB, the device proceeds to Standby mode. The INH output pin is a high−voltage high−side switch to VB supply. It can be used to control the VCC or VIO external supply voltage regulators. The output is switched high in all operating modes except for the Sleep mode. In Sleep mode the pin is left floating (high−impedance) which can be used to deactivate the external regulators in order to minimize the ECU current consumption. The INH switch is also deactivated in Power−off mode. Standby Mode Standby mode is a low−power mode. In Standby mode both the transmitter and receiver are disabled and a very low−power differential receiver monitors the bus lines for CAN bus activity. The bus lines are biased to ground and supply current is reduced to a minimum. A wake−up event can be detected either on the CAN bus or on the WAKE pin. A valid wake−up is signaled on pins ERRN and RxD. Pin INH remains active (pulled high) so that the external regulators controlled by the INH pin remain switched on. Standby mode is entered automatically upon Power−on event (VB > Vuvr_VB). It can be requested during normal operation by setting STBN and EN pins to Low. Standby mode is also entered if wake−up event is detected in Sleep mode or if VCC and VIO recovers after undervoltage condition has been detected. HIGH SPEED CAN TRANSCEIVER NCV7343 implements high−speed physical layer CAN FD transceiver compatible with ISO11898−2:2016, implementing following optional features or alternatives: • Extended bus load range • Transmit dominant timeout, long • Support of bit rates up to 5 Mbit/s • Low−power modes with wake−up via wake−up pattern, Short CAN activity filter time and long wake−up timeout • Normal Bus biasing OPERATIONS MODES NCV7343 provides five operation modes. These modes are either selectable through pins STBN and EN or entered automatically upon detection of specific event, such as power−on, undervoltage of wake−up (see Figure 11). Any mode transition is completed within a time given by operating mode change delay td(mode). STBN Normal Mode In the Normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give low EME. The bus lines (CANH and CANL) are internally biased to VCC/2. Pin INH is active (pulled high) so that the external regulators controlled by INH pin are switched on. Normal mode can be requested by setting STBN and EN pin to High. < th(mode) EN td(mode) Standby Normal Silent Mode In Silent mode, the CAN transmitter is disabled. The CAN controller can still receive data from the bus via RxD Pin as the receiver part remains active. Equally to Normal mode, the bus lines (CANH and CANL) are internally biased to VCC/2. Pin INH is also active (pulled high). Silent mode can be requested by setting STBN to High and EN pin to Low. Figure 7. Operating Mode Transition Timing STBN > th(mode) EN td(mode) Standby td(mode) Silent Normal Go−to−Sleep Mode Go−to−sleep mode is an intermediate state used to put the transceiver into Sleep mode in a controlled way. Go−to−sleep mode is entered when EN is set to High and STBN pin is set to Low. If the logical state of pins EN and STBN is kept unchanged for a minimum period of th(go−to−sleep) and neither a wake−up nor a power−up event occur during this time, the transceiver enters Sleep mode. Figure 8. Operating Mode Transition Timing Power−off This virtual mode is entered as soon as the VB voltage falls below the battery undervoltage detection threshold Vuvd_VB and a VB undervoltage condition is detected. The internal logic is reset. The transceiver and wake−up detection is www.onsemi.com 12 NCV7343 While in Go−to−sleep mode, the transceiver behaves identically to Standby mode. the mode change via STBN is requested by the host or a valid wake−up is detected. Sleep Mode Operating Modes Transition Sleep mode is a low−power mode in which the consumption is further reduced compared to Standby mode. Sleep mode can be entered via Go−to−sleep mode or is forced in case an undervoltage on either VCC and/or VIO occurs for longer than the undervoltage detection time. The transceiver behaves identically to Standby mode, but the INH Pin is deactivated (left floating) and the external regulators controlled by INH pin are switched off. In this way, the VB consumption is reduced to a minimum. The device will leave sleep mode either after a wake−up event (in case of a CAN bus wake−up or wake−up via WAKE pin) or by changing STBN pin from Low to High (as long as an undervoltage on VIO is not detected). In case the Sleep mode was forced due to undervoltage detection, the device enters Standby mode and the operation mode control by STBN and EN pin is re−enabled as soon as both VCC and VIO supplies are recovered. In case the Sleep mode was requested by the host, any potential VCC and/or VIO undervoltage detection and subsequent undervoltage recovery does not lead to any mode change and the device stays in Sleep mode until > th(go−to−sleep) STBN EN th(go−to−sleep) Normal td(mode) Go−to−Sleep Sleep Figure 9. Correct Sleep Mode Entry Sequence STBN EN < th(go−to−sleep) Normal td(mode) Standby Figure 10. Sleep Mode Entry Sequence Interrupted www.onsemi.com 13 NCV7343 Power off VB UV detected Any active mode VB < V uvd_VB 1 CAN: off (no bias) Wake−up: Disabled INH = OFF RxD: High(VIO) VB > V uvr_VB Standby mode STBN = L EN = L STBN = L, EN = L STBN = L EN = L STBN = H EN = H CAN: off (weak GND) Wake−up: Enabled 4 INH = High ERRN, RxD: wake−up STBN = H EN = L (STBN = L EN = H)5 no wake flag Normal mode STBN = H, EN = H CAN: Normal (VCC/2) INH = High Silent mode STBN = H EN = L STBN = H, EN = L CAN: Receive only (VCC/2) INH = High STBN = H EN = H ERRN: Local wake−up / Bus failure ERRN: Power−on / Local failure STBN = L EN = L Go−to−Sleep mode STBN = H EN = H STBN = L, EN = H (STBN = L EN = H)5 CAN: off (weak GND) Wake−up: Enabled INH = High ERRN, RxD: wake−up STBN = H EN = L (STBN = L EN = H)5 no wake flag no wake flag Sleep mode STBN L³H EN = H and V IO OK STBN = L, EN = L or H CAN: off (weak GND) Wake−up: Enabled INH = OFF ERRN, RxD: wake−up2 Wake−up detected or ( VCC OK and V IO OK )3 STBN L³H EN = L and V IO OK VCC UV detected and/or VIO UV detected Any active mode Notes: 1 Highest priority 2 If VIO is active 3 In case Sleep mode was requested by host command VCC /V IO undervoltage recovery event does not lead to mode change 4 Upon Power−on event, Local wake−up detection is enabled after t d(wake_startup) 5 For t > t h(go−to−sleep) VCC UV detected: VCC < Vuv_VCC for t > t uvd_VCC ; VCC > Vuv_VCC for t > t uvr_VCC ; VCC OK: VIO UV detected: VIO OK: Figure 11. Operation Modes www.onsemi.com 14 VIO < Vuv_VIO VIO > Vuv_VIO for t > t uvd_VIO for t > t uvr_VIO NCV7343 WAKE−UP A Wake−up flag is set if Local wake−up via WAKE pin (positive or negative edge) is detected or Remote wake−up via bus (wake−up pattern) is detected. If the Wake−up flag is set in Sleep mode, the device changes to Standby mode. Undervoltage detection flags are cleared and the corresponding timers are restarted upon detection of valid wake−up event. The Wake−up flag is cleared when entering Normal mode or when VCC or VIO undervoltage is detected. Wake−up flag is signaled on ERRN and RxD pin in Standby, Go−to−sleep and Sleep mode provided the VIO supply voltage is available. w twake_filt WAKE VIH(WAKE) twake_filt > twake_filt < twake_filt td(mode_wake) td(wake_flg) WAKE pin pull−down pull−up RxD, ERRN Wake−up Sleep mode Local Wake−up (WAKE pin) Standby INH The high−voltage input WAKE is monitored in Low−power Standby mode, Go−to−Sleep and Sleep mode. If a negative or positive edge is recognized on WAKE pin, a local wake−up is detected and a Wake−up flag is set. In order to avoid false wake−ups, the negative or positive edge must be followed by stable Low or High level, respectively, longer than twake_filt for the wake−up to be valid. The WAKE pin can be used, for example, for switch or contact monitoring. Internal pull−up and pull−down current sources are connected to WAKE pin in order to minimize the risk of parasitic toggling. The current source polarity is automatically selected based on the WAKE input signal polarity – when the voltage on WAKE stays stable High (Low) for longer than twake_filt, the internal current source is switched to pull−up (pull−down). Negative edge detection is depicted in Figure 12. Positive edge detection is depicted in Figure 13. Besides, in order to be able to distinguish between local and remote wake−up events, a Wake−up source indication flag is set if local wake−up is detected. Wake−up source indication flag is reset upon Normal mode leaving. Wake−up source indication flag is signaled on ERRN pin in Normal mode, before first four consecutive dominant symbols are sent. Figure 13. Local Wake−up Behavior (Positive Edge) Remote Wake−up (Wake−up pattern) When a valid wake−up pattern (phase in order dominant – recessive – dominant) is detected during the Standby, Go−to−Sleep or Sleep mode a Wake−up flag is set. Minimum length of each phase is twup_filt – see Figure 14. Pattern must be received within twup_to to be recognized as valid wake−up otherwise internal logic is reset. w t wup_filt w twup_filtw t wup_filt CANH CANL Vi(diff) Vi(dom)(diff)_LP (1.05 V) Vi(rec)(diff)_LP (400 mV) twup_filt < twup_to RxD, ERRN td(mode_wup) twup_flg Wake−up w t wake_filt WAKE Sleep VIL(WAKE) Standby INH twake_filt > twake_filt < twake_filt WAKE pin pull−up RxD, ERRN td(mode_wake) td(wake_flg) Figure 14. Remote Wake−up Behavior (Wake−up Pattern) pull−down Wake−up Sleep mode Standby INH Figure 12. Local Wake−up Behavior (Negative Edge) www.onsemi.com 15 NCV7343 FAILURE DETECTION Local Failures The transmitter can be re−enabled when either Normal mode is entered or bus dominant symbol is received on the bus, driving RxD Low, while TxD is High. A Local failure flag is set if any of the flowing flags are set: • TxD Dominant Timeout • Bus Dominant Timeout • Short−TxD to RxD • Overtemperature Detection Overtemperature Detection An overtemperature flag is set if the junction temperature exceeds a shutdown temperature TJSD. The thermal protection circuit protects the IC from damage by switching off the transmitter if the overtemperature is detected. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is expected to be reduced once the transmitter is disabled. All other IC functions continue to operate. The overtemperature flag is reset when the junction temperature decreases below the thermal shutdown threshold and either Normal mode is entered or bus dominant symbol is received on the bus while TxD is High. The transmitter can be re−enabled when the flag is cleared. The thermal protection circuit is particularly needed in case of a bus line short circuit. The local failure flag is signaled on ERRN pin in Silent mode entered from Normal mode. The flag is cleared if all of the mentioned flags are cleared. TxD Dominant Timeout A TxD dominant timeout timer circuit prevents the bus lines being driven to a permanent dominant state if pin TxD is forced permanently low. The timer is triggered by a negative edge on pin TxD in Normal mode. If the duration of the Low level on pin TxD exceeds the internal timer value tdom(TxD), the TxD dominant timeout flag is set. The transmitter is disabled, driving the bus into a recessive state, as long as the TxD dominant flag is set. The timer and the flag is reset when TxD is High and either Normal mode is entered or bus dominant is received in Normal mode. The transmitter is reactivated latest ten(TxD) after TxD dominant flag has been cleared. The minimum value of TxD dominant timeout time tdom(TxD) limits the minimum bit rate to 17 kbps. CAN Bus Failure Flag The transmitter of the NCV7343 device allows for bus failure detection. During dominant bit transmission in Normal mode, a short of the CANH or CANL line to supply or ground (VB, VCC or GND) is internally detected. If the short circuit condition lasts for four consecutive TxD dominant symbol requests, an internal bus failure flag is set. Minimum dominant symbol length for correct bus failure detection is 4 ms. The flag is visible on ERRN pin in Normal mode. The transmission and reception circuitry continues to function. The bus failure flag is reset when Normal mode is entered or if four consecutive TxD dominant symbols are sent while no bus short circuit condition is present. Bus Dominant Timeout Bus dominant timeout timer is started when CAN bus changes from recessive to dominant state. If the dominant state on the bus is kept for longer time than tdom(BUS), the RxD pin is released to High level and a Bus dominant timeout flag is set. No other action is taken upon Bus dominant timeout condition detection. The timer and the flag is reset when CAN bus changes back from dominant to recessive state in Normal or Silent mode, or when low−power mode is entered. The receiver is reactivated latest ten(RxD) after Bus dominant flag has been cleared. This feature prevents potential bus dominant clamping condition from blocking the communication controller transmit task. INTERNAL FLAGS AND THEIR SIGNALING The transceiver keeps several internal flags reflecting conditions and events encountered during its operation. Some flags influence the transceiver operation mode. Beside the undervoltage flags all others can be read by the host microcontroller on pin ERRN. Pin ERRN signals internal flags depending on the operation mode of the transceiver. An overview of the flags and their visibility on pin ERRN is given in following table. Because the ERRN pin uses negative logic, it will be pulled low if the corresponding signaled flag is set and will be pulled high if the signaled flag is reset. Short – TxD to RxD If a short between TxD and RxD signal lines is detected during data transmission. Short TxD to RxD flag is set and the transmitter is disabled. www.onsemi.com 16 NCV7343 INTERNAL FLAGS AND THEIR VISIBILITY Set Conditions Reset Conditions VCC or VIO Undervoltage Internal Flag VCC < Vuv_VCC for t > tuvd_VCC or VIO < Vuv_VIO for t > tuvd_VIO (VCC > Vuv_VCC for t > tuvr_VCC and VIO > Vuv_VIO for t > tuvr_VIO) or power−on flag is set or wake flag is set or STBN is changed to High No Visibility on ERRN Pin VB Undervoltage VB < Vuvd_VB VB > Vuvr_VB No Power−on VB > Vuvr_VB Normal mode is entered In Silent mode entered from other than Normal mode Wake−up Local or remote wake−up is detected Normal mode is entered or VCC and/or VIO flag is set In Standby, Go−to−sleep or Sleep mode (if VIO is active) Wake−up Source indication Local wake−up is detected Normal mode is left In Normal mode before first four consecutive dominant symbols are sent TxD Dominant Timeout TxD is Low for longer than tdom(TxD) while in Normal operation mode TxD is High and either Normal mode is entered or bus dominant is received (RxD Low) in Normal mode See Local Failure flag Bus Dominant Timeout Bus is dominant for longer than tdom(BUS) Bus is recessive in Normal or Silent mode, or Low−power mode is entered TxD Shorted to RxD TxD is shorted to RxD during data transmission TxD is High and either Normal mode is entered or bus dominant is received (RxD Low) Overtemperature Junction temperature TJ > TJSD Junction temperature TJ < TJSD and either Normal mode is entered or bus dominant is received while TxD is High Local Failure Any of the following flags is set • TxD dominant timeout • Bus dominant timeout • TxD shorted to RxD • Overtemperature detection All of the following flags are reset • TxD dominant timeout • Bus dominant timeout • TxD shorted to RxD • Overtemperature detection In Silent mode entered from Normal mode Bus Failure Bus failure detected during four consecutive TxD dominant symbol requests Normal mode is entered or four consecutive TxD dominant symbols sent while no bus failure condition present In Normal mode after first four consecutive dominant symbols are sent STBN EN Events Power off Power−on 4th dominant symbol requested Wake−up Standby Silent ERRN High Wake−up Power−on RxD High Wake−up Data Normal Local Wake−up Silent Bus Failure Data Figure 15. ERRN and RxD Pin Signaling www.onsemi.com 17 th(go−to−sleep) GTS Sleep Local Failure Wake−up Data Wake−up NCV7343 FAIL SAFE The pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see Figure 19). Pin TxD is pulled high and pins STBN and EN are pulled low internally should the input become disconnected. Digital pins, TxD, STBN and EN will be floating, preventing reverse supply should the VIO supply be removed. RxD and ERRN have forward diode to VIO supply. A current−limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. Undervoltage on supply pins prevents the chip from sending data on the bus when there is not enough VCC supply voltage to build required bus differential voltage, or when VIO supply voltage is low and thus the digital input or output signals might be interpreted falsely. After supply is recovered TxD pin must be first released to High to allow sending dominant bits again. MEASUREMENT SETUPS AND DEFINITIONS recessive TxD1 dominant recessive 0.7 × VIO 0.3 × VIO CANH CANL Vi(diff) = VCANH * VCANL 900 mV 500 mV RxD td(TxD−BUSon) 1 0.7 × VIO 0.3 × VIO td(BUSon−RXD) td(TxD−BUSoff) td(BUSoff−RXD) TxD Edge length below 10 ns Figure 16. Transceiver Timing Diagram − Propagation Delays TxD1 0.7 × VIO 0.3 × VIO 5 × tbit(TxD) 0.3 × VIO tbit(TxD) Vi(diff) = VCANH * VCANL tpd_rd 900 mV 500 mV tbit(Vi(diff)) 0.7 × VIO RxD 1 tpd_dr TxD Edge length below 10 ns 0.3 × VIO tbit(RxD) Figure 17. Transceiver Timing Diagram − Loop Delay and Recessive Bit Time www.onsemi.com 18 NCV7343 +5 V 22 μF +14 V 100 nF 22 μF 100 nF +3.3 V VCC VIO 22 μF 100 nF 5 STBN EN ERRN TxD RxD INH VB 7 3 10 14 9 6 13 WAKE CANH RLT /2 NCV7343 8 CLT 100 pF CST RLT /2 1 12 4 CANL 2x 30 Ω 2 15 pF GND Figure 18. Test Circuit for Timing Characteristics +5 V 22 μF +14 V 100 nF 100 nF 22 μF +3.3 V VCC VIO 22 μF 100 nF 5 STBN EN ERRN TxD INH 7 3 VB 10 14 9 6 13 8 WAKE CANH 1 nF NCV7343 Test Pulse Generator 1 1 nF RxD 12 4 CANL 2 15 pF GND Figure 19. Test Circuit for Automotive Transients www.onsemi.com 19 NCV7343 ISO 11898−2:2016 PARAMETER CROSS−REFERENCE TABLE ISO 11898−2:2016 Specification Parameter NCV7343 Datasheet Notation Symbol Single Ended Voltage on CAN_H VCAN_H Vo(dom)(CANH) Single Ended Voltage on CAN_L VCAN_L Vo(dom)(CANL) Differential Voltage on Normal Bus Load VDiff Vo(dom)(diff) Differential Voltage on Effective Resistance During Arbitration VDiff Vo(dom)(diff)_ARB Differential Voltage on Extended Bus Load Range VDiff Vo(dom)(diff)_E VSYM Vo(sym) Absolute Current on CAN_H ICAN_H Io(SC)(CANH) Absolute Current on CAN_L ICAN_L Io(SC)(CANL) Single Ended Output Voltage on CAN_H VCAN_H Vo(rec) Single Ended Output Voltage on CAN_L VCAN_L Vo(rec) VDiff Vo(rec)(diff) Single Ended Output Voltage on CAN_H VCAN_H Vo(off) Single Ended Output Voltage on CAN_L VCAN_L Vo(off) VDiff Vo(off)(diff) Transmit Dominant Timeout tdom tdom(TxD) Transmit Dominant Timeout, Short tdom NA Recessive State Differential Input Voltage Range VDiff Vi(rec)(diff)_NM Dominant State Differential Input Voltage Range VDiff Vi(dom)(diff)_NM Recessive State Differential Input Voltage Range VDiff Vi(rec)(diff)_LP Dominant State Differential Input Voltage Range VDiff Vi(dom)(diff)_LP RDiff Ri(diff) RCAN_H RCAN_L Ri(cm) mR Ri(cm)(m) tLoop tpd_rd tpd_dr DOMINANT OUTPUT CHARACTERISTICS DRIVER SYMMETRY Driver Symmetry DRIVER OUTPUT CURRENT RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING ACTIVE Differential Output Voltage RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING INACTIVE Differential Output Voltage TRANSMIT DOMINANT TIMEOUT STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING ACTIVE STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING INACTIVE RECEIVER INPUT RESISTANCE Differential Internal Resistance Single Ended Internal Resistance RECEIVER INPUT RESISTANCE MATCHING Matching of Internal Resistance LOOP DELAY REQUIREMENT Loop Delay DATA SIGNAL TIMING REQUIREMENTS FOR USE WITH BIT RATES ABOVE 1 Mbit/s AND UP TO 2 Mbit/s Transmitted Recessive Bit Width @ 2 Mbit/s tBit(Bus) tbit(Vi(diff)) Received Recessive Bit Width @ 2 Mbit/s tBit(RXD) tbit(RxD) DtRec Dtrec Receiver Timing Symmetry @ 2 Mbit/s www.onsemi.com 20 NCV7343 ISO 11898−2:2016 PARAMETER CROSS−REFERENCE TABLE (continued) Parameter Notation Symbol DATA SIGNAL TIMING REQUIREMENTS FOR USE WITH BIT RATES ABOVE 2 Mbit/s AND UP TO 5 Mbit/s Transmitted Recessive Bit Width @ 5 Mbit/s tBit(Bus) tbit(Vi(diff)) Received Recessive Bit Width @ 5 Mbit/s tBit(RXD) tbit(RxD) DtRec Dtrec Receiver Timing Symmetry @ 5 Mbit/s MAXIMUM RATINGS OF VCAN_H, VCAN_L AND VDiff Maximum Rating VDiff VDiff VDiff General Maximum Rating VCAN_H and VCAN_L VCAN_H VCAN_L VCAN VCAN Optional: Extended Maximum Rating VCAN_H and VCAN_L VCAN_H VCAN_L NA ICAN_H ICAN_L ILEAK(off) tFilter NA CAN Activity Filter Time, Short tFilter twup_filt Wake−up Timeout, Short tWake NA Wake−up Timeout, Long tWake twup_to Timeout for Bus Inactivity (Required for Selective Wake−up Implementation Only) tSilence NA Bus Bias Reaction Time (Required for Selective Wake−up Implementation Only) tBias NA MAXIMUM LEAKAGE CURRENTS ON CAN_H and CAN_L, UNPOWERED Leakage Current on CAN_H, CAN_L BUS BIASING CONTROL TIMINGS CAN Activity Filter Time, Long Table 1. ORDERING INFORMATION Description Package Shipping† NCV7343D20R2G CAN FD Transceiver, High Speed, Low Power, with WAKE, INH and VIO Pin SOIC−14 (Pb−free) 3000 / Tape & Reel NCV7343MW0R2G CAN FD Transceiver, High Speed, Low Power, with WAKE, INH and VIO Pin DFNW14 Wettable Flank (Pb−free) 5000 / Tape & Reel NCV7343D21R2G CAN FD Transceiver, High Speed, Low Power, with WAKE, INH and VIO Pin, EMC Improved SOIC−14 (Pb−free) 3000 / Tape & Reel NCV7343MW1R2G CAN FD Transceiver, High Speed, Low Power, with WAKE, INH and VIO Pin, EMC Improved DFNW14 Wettable Flank (Pb−free) 5000 / Tape & Reel Part Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 21 NCV7343 PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L D A B 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 8 A3 E H L 1 0.25 M DETAIL A 7 B 13X M b 0.25 M C A S B S X 45 _ M A1 e DETAIL A h A 0.10 DIM A A1 A3 b D E e H h L M C SEATING PLANE SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 22 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ NCV7343 PACKAGE DIMENSIONS DFNW14 4.5x3, 0.65P CASE 507AC ISSUE D PIN ONE REFERENCE L3 A B D ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ L3 L L ALTERNATE CONSTRUCTION E DETAIL A EXPOSED COPPER NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMESNION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. THIS DEVICE CONTAINS WETTABLE FLANK DESIGN FEATURES TO AID IN FILLET FORMATION ON THE LEADS DURING MOUNTING. TOP VIEW A DETAIL B 0.10 C 0.08 C NOTE 4 PLATING A1 A4 C C DETAIL B A3 SIDE VIEW SEATING PLANE C A4 DETAIL A D2 1 14X L 7 L3 PLATED SURFACES SECTION C−C E2 K 8 14 e BOTTOM VIEW 14X MILLIMETERS MIN NOM MAX 0.80 0.85 0.90 −−− −−− 0.05 0.20 REF 0.10 −−− −−− 0.25 0.30 0.35 4.40 4.50 4.60 4.13 4.20 4.27 2.90 3.00 3.10 1.53 1.60 1.67 0.65 BSC 0.30 REF 0.35 0.40 0.45 0.00 0.05 0.10 DIM A A1 A3 A4 b D D2 E E2 e K L L3 RECOMMENDED SOLDERING FOOTPRINT* 14X 4.35 4.23 b 14 0.10 M C A B 0.05 M C 0.75 8 3.60 1.75 NOTE 3 1 7 0.65 PITCH PACKAGE OUTLINE 14X 0.33 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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