0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
NCV8508PD50R2

NCV8508PD50R2

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    SOIC8_150MIL_EP

  • 描述:

    IC REG LDO 5V 8SOIC

  • 数据手册
  • 价格&库存
NCV8508PD50R2 数据手册
NCV8508 5.0 V, 250 mA LDO with Watchdog and RESET The NCV8508 is a precision micropower Low Dropout (LDO) voltage regulator. The part contains many of the required features for powering microprocessors. Its robustness makes it suitable for severe automotive environments. In addition, the NCV8508 is ideal for use in battery operated, microprocessor controlled equipment because of its extremely low quiescent current. http://onsemi.com MARKING DIAGRAMS 16 Features •Output Voltage: 5.0 V •±3.0% Output Voltage •IOUT Up to 250 mA •Quiescent Current Independent of Load •Micropower Compatible Control Functions: 16 NCV85085 AWLYYWWG 1 SO-16L DW SUFFIX CASE 751G 1 ♦Wakeup ♦Watchdog ♦RESET •Low Quiescent Current (100 mA typ) •Protection Features: NCV85085 AWLYWWG ♦Thermal Shutdown Circuit ♦45 V Operation •Internally Fused Leads in SO-16L Package •NCV Prefix for Automotive and Other Applications Requiring Site and Change Control •AEC Qualified •PPAP Capable •Pb-Free Package is Available* ♦Short 1 8 8 V8508 ALYW G 1 SO-8 EP PD SUFFIX CASE 751AC 1 C1* 0.1 mF VOUT VIN WDI Delay RDelay 60 k GND RESET WAKEUP C2 1.0 mF VDD I/O RESET Microprocessor NCV8508 MRA4004T3 VBAT D2PAK-7 DPS SUFFIX CASE 936AB I/O A WL, L YY, Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 23 of this data sheet. *C1 required if regulator is located far from power supply filter. Figure 1. Application Circuit *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2007 October, 2007 - Rev. 25 1 Publication Order Number: NCV8508/D NCV8508 PIN CONNECTIONS 1 16 Delay RESET Wakeup GND GND WDI NC VIN NC NC NC GND GND NC Sense VOUT 1 SO-16L Tab = GND Lead 1. VOUT 2. VIN 3. WDI 4. GND 5. Wakeup 6. RESET 7. Delay D2PAK-7 1 8 Delay RESET GND Wakeup Sense WDI VOUT VIN SO-8 EP PACKAGE PIN DESCRIPTION PACKAGE PIN # D2PAK-7 SO-16L SO-8 EP PIN SYMBOL 1 8 4 VOUT 2 9 5 VIN Supply Voltage to the IC. 3 11 6 WDI CMOS compatible input lead. The Watchdog function monitors the falling edge of the incoming signal. 4 4, 5, 12, 13 2 GND Ground connection. 5 14 7 Wakeup CMOS compatible output consisting of a continuously generated signal used to “wake up” the microprocessor from sleep mode. 6 15 8 RESET CMOS compatible output lead RESET goes low whenever VOUT drops by more than 7.0% from nominal, or during the absence of a correct Watchdog signal. 7 16 1 Delay Buffered bandgap voltage used to create timing current for RESET and Wakeup from RDelay. - 1-3, 6, 10 - NC - 7 3 Sense FUNCTION Regulated output voltage ± 3.0%. No Connection. Kelvin connection which allows remote sensing of the output voltage for improved regulation. Connect to VOUT if remote sensing is not required. http://onsemi.com 2 NCV8508 VIN - Internally connected on 7 lead D2PAK Charge Pump + 11 V Sense Current Limit 1.25 V Bandgap Reference VOUT Thermal Shutdown + - - RESET + Watchdog Circuit WDI Falling Edge Detect Timing Circuit Delay Wakeup Circuit Wakeup Figure 2. Block Diagram MAXIMUM RATINGS Rating Input Voltage, VIN (DC) Peak Transient Voltage (46 V Load Dump @ VIN = 14 V) Output Voltage, VOUT Value Unit -0.3 to 45 V 60 V -0.3 to 18 V 2.0 150 kV V -0.3 to +7.0 V -40 to150 °C -55 to +150 °C 240 Peak 260 Peak (Pb-Free) (Note 3) °C ESD Susceptibility: Human Body Model Machine Model Logic Inputs/Outputs (RESET, WDI, Wakeup) Operating Junction Temperature, TJ Storage Temperature Range, TS Peak Reflow Soldering Temperature: Reflow: (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 60 second maximum above 183°C. 2. Depending on thermal properties of substrate RqJA = RqJC + RqJCA. 3. -5°C/+0°C allowable conditions, applies to both Pb and Pb-Free devices. THERMAL CHARACTERISTICS See Package Thermal Data Section (Page 10) http://onsemi.com 3 NCV8508 ELECTRICAL CHARACTERISTICS (-40°C ≤ TJ ≤ 125°C; 6.0 V ≤ VIN ≤ 28 V, 100 mA ≤ IOUT ≤ 150 mA, C2 = 1.0 mF, RDelay = 60 k; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit - 4.85 5.00 5.15 V OUTPUT Output Voltage Dropout Voltage (VIN - VOUT) IOUT = 150 mA. Note 4 - 450 900 mV Load Regulation VIN = 14 V, 100 mA ≤ IOUT ≤ 150 mA - 5.0 30 mV Line Regulation 6.0 V ≤ VIN ≤ 28 V, IOUT = 5.0 mA - 5.0 50 mV - 250 400 - mA Thermal Shutdown Guaranteed by Design 150 180 210 °C Quiescent Current VIN = 12 V, IOUT = 150 mA, (see Figure 6) - 100 150 mA 4.50 4.65 4.80 V - 0.2 0.4 0.4 0.8 V VOUT - 0.5 VOUT - 1.0 VOUT - 0.25 VOUT - 0.5 - V 2.0 - 3.0 6.0 4.0 - ms ms Current Limit RESET Threshold - Output Low RLOAD = 10 k to VOUT, VOUT ≥ 1.0 V RLOAD = 5.1 k to VOUT, VOUT ≥ 1.0 V Output High RLOAD = 10 k to GND RLOAD = 5.1 k to GND Delay Time VIN = 14 V, RDelay = 60 k, IOUT = 5.0 mA VIN = 14 V, RDelay = 120 k, IOUT = 5.0 mA WATCHDOG INPUT Threshold High - 70 - - %VOUT Threshold Low - - - 30 %VOUT Hysteresis - - 100 - mV - 0.1 +10 mA 5.0 - - ms Input Current WDI = 6.0 V Pulse Width 50% WDI falling edge to 50% WDI rising edge and 50% WDI rising edge to 50% WDI falling edge, (see Figure 5) WAKEUP OUTPUT (VIN = 14 V, IOUT = 5.0 mA) Wakeup Period See Figures 4 and 5, RDELAY = 60 k See Figures 4 and 5, RDELAY = 120 k 18 - 25 50 32 - ms ms Wakeup Duty Cycle Nominal See Figure 3 45 50 55 % RESET HIGH to Wakeup Rising Delay Time RDELAY = 60 k 50% RESET rising edge to 50% Wakeup edge, RDELAY = 120 k (see Figures 3 and 4) 9.0 - 12.5 25 16 - ms ms Wakeup Response to Watchdog Input 50% WDI falling edge to 50% Wakeup falling edge - 0.1 5.0 ms Wakeup Response to RESET 50% RESET falling edge to 50% Wakeup falling edge. VOUT = 5.0 V→ 4.5 V - 0.1 5.0 ms Output Low RLOAD = 10 k to VOUT, VOUT ≥ 1.0 V RLOAD = 5.1 k to VOUT, VOUT ≥ 1.0 V - 0.2 0.4 0.4 0.8 V Output High RLOAD = 10 k to GND RLOAD = 5.1 k to GND VOUT - 0.5 VOUT - 1.0 VOUT - 0.25 VOUT - 0.5 - V IDELAY = 50 mA. Note 5 - 1.25 - V DELAY Output Voltage 4. Measured when the output voltage has dropped 100 mV from the nominal value. (see Figure 12) 5. Current drain on the Delay pin directly affects the Delay Time, Wakeup Period, and the RESET to Wakeup Delay Time. http://onsemi.com 4 NCV8508 TIMING DIAGRAMS VIN RESET Wakeup Duty Cycle = 50% Wakeup WDI VOUT WDI Pulse Must Occur with Wakeup in Low State for 50% Duty Cycle. Reference Figure 17 for Occurrence of WDI with Wakeup in High State. POR RESET High to Wakeup Delay Time Power Up Microprocessor Sleep Mode Normal Operation with Varying Watchdog Signal Figure 3. Power Up, Sleep Mode and Normal Operation VIN RESET Delay Time RESET Wakeup WDI VOUT POR RESET High to Wakeup Delay Time Wakeup Period RESET High to Wakeup Delay Time Figure 4. Error Condition: Watchdog Remains Low and a RESET Is Issued RESET Wakeup Period Wakeup WDI RESET Threshold VOUT Watchdog Pulse Width Power Down POR POR Watchdog Pulse Width Figure 5. Power Down and Restart Sequence http://onsemi.com 5 NCV8508 TYPICAL PERFORMANCE CHARACTERISTICS 120 -700 -40°C VOUT Transient, mV -600 IQ, mA 110 +25°C 100 0 50 100 150 IOUT, mA -400 -300 10 mF ESR = 3.4 W -200 100 mF ESR = 1.3 W -100 +125°C 90 1.0 mF ESR = 4.6 W -500 200 0 250 0 Figure 6. Quiescent Current vs Output Current 100 150 Switching Current, mA 200 250 Figure 7. Load Transient Response 14 3.7 3.6 12 3.5 3.4 10 POR Delay, ms POR Delay, ms 50 3.3 3.2 3.1 3.0 8 6 4 2.9 2 2.8 2.7 -40 -20 0 20 40 60 80 Temperature, °C 100 120 0 15 140 60 105 150 RDELAY, kW 195 240 Figure 9. POR Delay vs RDELAY Figure 8. POR Delay vs Temp, RDELAY = 60 kW 27.0 100 90 26.5 70 25.5 RDELAY, ms Wakeup Period, ms 80 26.0 25.0 24.5 60 50 40 30 24.0 20 23.5 23.0 -40 10 -20 0 20 40 60 80 Temperature (°C) 100 120 0 15 140 60 105 150 RDELAY, kW 195 Figure 11. Wakeup Period vs RDELAY Figure 10. Wakeup Period vs Temp, RDELAY = 60 kW http://onsemi.com 6 240 NCV8508 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 5.10 0.9 Dropout Voltage (V) Output Voltage (V) +125°C 0.8 0.7 0.6 +25°C 0.5 -40°C 0.4 0.3 5.05 5.00 VIN = 14 V IOUT = 5.0 mA 4.95 0.2 0.1 0.0 0 25 50 75 4.90 -40 -25 -10 100 125 150 175 200 225 250 Output Current (mA) Figure 12. Dropout Voltage vs Output Current 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 13. Output Voltage vs Temperature 1000 160 140 120 Unstable Region 100 ESR (W) IOUT (mA) 100 80 60 Stable Region 10 40 RL = 33 W 20 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 C = 1.0 mF, 10 mF 1 6.0 0 5 10 15 20 25 30 35 40 45 Output Current (mA) Figure 14. Output Current vs Input Voltage Figure 15. Output Capacitor ESR DEFINITION OF TERMS Dropout Voltage: The input-output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage: The DC voltage applied to the input terminals with respect to ground. Line Regulation: The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Load Regulation: The change in output voltage for a change in load current at constant chip temperature. Quiescent Current: The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple Rejection: The ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. Current Limit: Peak current that can be delivered to the output. http://onsemi.com 7 NCV8508 DETAILED OPERATING DESCRIPTION The NCV8508 is a precision micropower voltage regulator with very low quiescent current (100 mA typical at 250 mA load). A typical dropout voltage is 450 mV at 150 mA. Microprocessor control logic includes Watchdog, Wakeup and RESET. This unique combination of extremely low quiescent current and full microprocessor control makes the NCV8508 ideal for use in battery operated, microprocessor controlled equipment in addition to being a good fit in the automotive environment. The NCV8508 Wakeup function brings the microprocessor out of Sleep mode. The microprocessor in turn signals its Wakeup status back to the NCV8508 by issuing a Watchdog signal. The Watchdog logic function monitors an input signal (WDI) from the microprocessor. The NCV8508 responds to the falling edge of the Watchdog signal which it expects at least once during each Wakeup period. When the correct Watchdog signal is received, a falling edge is issued on the Wakeup signal line. RESET is independent of VIN and operates correctly to an output voltage as low as 1.0 V. A signal is issued in any of three situations. During power up, the RESET is held low until the output voltage is in regulation. During operation, if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. Finally, a RESET signal is issued if the regulator does not receive a Watchdog signal within the Wakeup period. The RESET pulse width, Wakeup signal frequency, and Wakeup delay time are all set by one external resistor, RDelay. The Delay pin is a buffered bandgap voltage (1.25 V). It can be used as a reference for an external tracking regulator as shown in Figure 16. The regulator is protected against short circuit and thermal runaway conditions. The device runs through 45 volt transients, making it suitable for use in automotive environments. MRA4004T3 200 mA VIN VIN VBAT 0.1 mF 1.0 mF NCV8508 12 k CS8182 Adj 3.9 k Delay GND VREF/ENABLE 60 k 0.1 mF Figure 16. Application Circuit http://onsemi.com 8 5V VOUT GND 10 mF NCV8508 CIRCUIT DESCRIPTION Functional Description Resistor temperature coefficient and tolerance as well as the tolerance of the NCV8508 must be taken into account in order to get the correct system tolerance for each parameter. To reduce the drain on the battery, a system can go into a low current consumption mode whenever it is not performing a main routine. The Wakeup signal is generated continuously and is used to interrupt a microcontroller that is in sleep mode. The nominal output is a 5.0 volt square wave (voltage generated from VOUT) with a duty cycle of 50% at a frequency that is determined by a timing resistor, RDelay. When the microprocessor receives a rising edge from the Wakeup output, it must issue a Watchdog pulse and check its inputs to decide if it should resume normal operations or remain in the sleep mode. The first falling edge of the Watchdog signal causes the Wakeup to go low within 2.0 ms (typ) and remain low until the next Wakeup cycle (see Figure 17). Other Watchdog pulses received within the same cycle are ignored (Figure 3). During power up, RESET is held low until the output voltage is in regulation. During operation, if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. After the RESET delay, RESET returns high. The Watchdog circuitry continuously monitors the input Watchdog signal (WDI) from the microprocessor. The absence of a falling edge on the Watchdog input during one Wakeup cycle will cause a RESET pulse to occur at the end of the Wakeup cycle. (see Figure 4). The Wakeup output is pulled low during a RESET regardless of the cause of the RESET. After the RESET returns high, the Wakeup cycle begins again (see Figure 4). The RESET Delay Time, Wakeup signal frequency and RESET high to Wakeup delay time are all set by one external resistor RDelay. Wakeup Period = (4.17 × 10-7)RDelay RESET Delay Time = (5.21 × 10-8)RDelay RESET HIGH to Wakeup Delay Time = (2.08 × 10-7)RDelay WDI Wakeup Wakeup Response to WDI Figure 17. Wakeup Response to WDI RESET Wakeup Wakeup Response to RESET Figure 18. Wakeup Response to RESET (Low Voltage) http://onsemi.com 9 NCV8508 THERMAL DATA Recommend Thermal Data for SOIC-16 Package Parameter Test Conditions Typical Value Units min-pad board (Note 6) 1”-pad board (Note 7) Junction-to-Lead (psi-JL, YJL) 20 15 °C/W Junction-to-Ambient (RqJA, qJA) 100 83 °C/W mm2 6. 1 oz. copper, 94 copper area, 0.062” thick FR4. 7. 1 oz. copper, 767 mm2 copper area, 0.062” thick FR4. Figure 19. Min Pad PCB Layout Figure 21. Internal Construction of the Package (notice pins 4, 5 and 12, 13 are connected to flag) Figure 20. Min Pad PCB Layout http://onsemi.com 10 NCV8508 Table 1. SOIC 16-Lead Thermal RC Network Models 96 mm2 767 mm2 96 mm2 Cauer network 767 mm2 Cu Area Foster network C's C's Units Tau Tau units 1 1.84E-06 1.84E-06 W-s/C 2.99E-07 2.99E-07 sec 2 8.69E-06 8.69E-06 W-s/C 4.40E-06 4.40E-06 sec 3 2.61E-05 2.61E-05 W-s/C 4.62E-05 4.62E-05 sec 4 8.98E-05 8.98E-05 W-s/C 5.08E-04 5.08E-04 sec 5 2.30E-03 2.30E-03 W-s/C 8.93E-03 8.95E-03 sec 6 2.99E-02 3.07E-02 W-s/C 2.04E-01 2.19E-01 sec 7 1.79E-01 1.90E-01 W-s/C 3.26E+00 2.75E+00 sec 8 7.79E-01 9.94E-01 W-s/C 3.21E+01 2.19E+01 sec 9 5.34E+00 3.98E+00 W-s/C 1.24E+02 1.20E+02 sec R's R's R's R's 1 0.199 0.199 C/W 0.123 0.123 C/W 2 0.598 0.598 C/W 0.349 0.349 C/W 3 1.795 1.795 C/W 1.057 1.057 C/W 4 4.085 4.085 C/W 4.61 4.61 C/W 5 3.977 3.977 C/W 3.87 3.89 C/W 6 7.509 7.833 C/W 5.77 5.99 C/W 7 19.886 15.247 C/W 13.17 11.38 C/W 8 40.307 24.781 C/W 28.85 15.52 C/W 9 18.193 21.446 C/W 38.75 37.05 C/W NOTE: Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network are computed by the square root of time constant R(t) = 225 * sqrt(time(sec)). The constant is derived based on the active area of the device with silicon and epoxy at the interface of the heat generation. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: n R(t) + S Riǒ1-e-tńtauiǓ i+1 http://onsemi.com 11 NCV8508 qJA vs Copper Spreader Area 100 THERMAL RESISTANCE, JUNCTION-AMBIENT, RqJA, (°C/W) 100 qJA (°C/W) 95 1 oz 90 2 oz 85 80 75 70 0 100 200 300 400 500 600 700 90 80 70 60 50 40 800 0 0.5 1.0 COPPER AREA (mm2) 1.5 COPPER AREA Figure 22. SOIC 16-Lead qJA as a Function of the Pad Copper Area Including Traces, Board Material 2.0 2.5 3.0 (inch2) Figure 23. 16 Lead SOW (4 Leads Fused), qJA as a Function of the Pad Copper Area (2 oz. Cu Thickness), Board Material = 0.0625, G-10/R-4 100 Cu Area 94 mm2 Cu Area 767 mm2 R(t) (°C/W) 10 1 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 Time (sec) 1 10 100 1000 Figure 24. SOIC 16-Lead Single Pulse Heating Curve 100 R(t) (°C/W) 50% Duty Cycle 10 20% 10% 5% 1 1% Single Cu Area 767 mm2, 1 oz Cu 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 Time (sec) Figure 25. SOIC 16-Lead Thermal Duty Cycle Curves on 1” Spreader Test Board http://onsemi.com 12 100 1000 NCV8508 R1 Junction C1 R2 C2 R3 C3 Rn Cn Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Ambient (thermal ground) Figure 26. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 C1 R2 C2 R3 C3 Rn Cn Each rung is exactly characterized by its RC-product time constant; amplitudes are the resistances. Ambient (thermal ground) Figure 27. Non-Grounded Capacitor Thermal Ladder (“Foster” Ladder) http://onsemi.com 13 NCV8508 Recommend Thermal Data for D2PAK-7 Package Parameter Test Conditions Typical Value Units min-pad board (Note 8) 1”-pad board (Note 9) Junction-to-Lead (psi-JL, YJL) 6.0 6.0 °C/W Junction-to-Ambient (RqJA, qJA) 78 44 °C/W 8. 1 oz. copper, 118 mm2 copper area, 0.062” thick FR4. 9. 1 oz. copper, 626 mm2 copper area, 0.062” thick FR4. Package construction Without mold compound Various copper areas used for heat spreading Active Area (red) times 2 (only showing 1/2 symmetry) Figure 28. PCB Layout and Package Construction for Simulation http://onsemi.com 14 NCV8508 Table 2. D2PAK 7-Lead Thermal RC Network Models 118 mm2 626 mm2 118 mm2 Cauer Network 626 mm2 Cu Area Foster Network C's C's Units Tau Tau units 1 1.45E-06 1.45E-06 W-s/C 1.00E-07 1.00E-07 sec 2 5.55E-06 5.58E-06 W-s/C 1.00E-06 1.00E-06 sec 3 1.57E-05 1.59E-05 W-s/C 1.00E-05 1.00E-05 sec 4 5.11E-05 5.22E-05 W-s/C 0.000 0.000 sec 5 3.48E-04 5.94E-04 W-s/C 0.001 0.002 sec 6 1.07E-02 6.62E-02 W-s/C 0.006 0.029 sec 7 2.65E-02 1.55E-01 W-s/C 0.020 0.080 sec 8 0.524 0.413 W-s/C 1.43 2.63 sec 9 0.490 2.441 W-s/C 6.52 3.6 sec 10 0.843 0.410 W-s/C 104.512 95.974 sec R's R's R's R's 1 0.089 0.089 C/W 5.25E-02 5.25E-02 C/W 2 0.210 0.208 C/W 1.14E-01 1.14E-01 C/W 3 0.637 0.624 C/W 3.59E-01 3.59E-01 C/W 4 1.899 2.107 C/W 1.5 1.9 C/W 5 1.883 2.454 C/W 2.6 3.0 C/W 6 1.398 0.952 C/W 0.1 0.1 C/W 7 0.315 0.360 C/W 1.7 0.9 C/W 8 14.348 7.042 C/W 0.1 0.1 C/W 9 5.621 20.823 C/W 7.2 4.6 C/W 10 51.986 9.649 C/W 64.8 33.3 C/W NOTE: Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network are computed by the square root of time constant R(t) = 166 * sqrt(time(sec)). The constant is derived based on the active area of the device with silicon and epoxy at the interface of the heat generation. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: n R(t) + S Riǒ1-e-tńtauiǓ i+1 http://onsemi.com 15 NCV8508 qJA vs Copper Spreader Area 120 qJA (°C/W) 100 80 1 oz 60 2 oz 40 20 0 0 100 200 300 400 COPPER AREA 500 600 700 800 (mm2) Figure 29. D2PAK 7-lead qJA as a Function of the Pad Copper Area Including Traces, Board Material 100 Cu Area 118 mm2 R(t) (°C/W) 10 Cu Area 626 mm2 1 0.1 0.01 0.000001 0.00001 0.0001 0.001 0.1 0.01 Time (sec) 1 10 100 1000 10 100 1000 Figure 30. D2PAK 7-Lead Single Pulse Heating Curve 100 50% Duty Cycle 10 20% R(t) (°C/W) 10% 1 5% 1% 0.1 Single 0.01 0.000001 Cu Area 626 mm2, 1 oz Cu 0.00001 0.0001 0.001 0.1 0.01 Pulse Duration (sec) 1 Figure 31. D2PAK 7-Lead Thermal Duty Cycle Curves on 1” Spreader Test Board http://onsemi.com 16 NCV8508 R1 Junction C1 R2 C2 R3 C3 Rn Cn Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Ambient (thermal ground) Figure 32. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 C1 R2 C2 R3 C3 Rn Cn Each rung is exactly characterized by its RC-product time constant; amplitudes are the resistances. Ambient (thermal ground) Figure 33. Non-Grounded Capacitor Thermal Ladder (“Foster” Ladder) http://onsemi.com 17 NCV8508 Recommend Thermal Data for SOIC-8 EP Package Parameter Test Conditions Typical Value Pad is soldered to PCB copper Units min-pad board (Note 10) 1”-pad board (Note 11) Junction-to-Lead (psi-JL, YJL) 64 54 °C/W Junction-to-Lead (psi-JPad, YJp) 14 11 °C/W Junction-to-Ambient (RqJA, qJA) 122 84 °C/W 10. 1 oz. copper, 54 mm2 copper area, 0.062” thick FR4. 11. 1 oz. copper, 717 mm2 copper area, 0.062” thick FR4. 8-SOIC EP Half Symmetry Top view Without and without mold compound Bottom view With mold compound Copper Pad Layout 25 x 25mm Figure 34. Internal Construction of the Package and PCB Layout for Multiple Pad Area http://onsemi.com 18 NCV8508 Table 3. SOIC 8-Lead EP Thermal RC Network Models 54 mm2 717 mm2 54 mm2 Cauer Network 717 mm2 Cu Area Foster Network C's C's Units Tau Tau units 1 2.28E-06 2.28E-06 W-s/C 2.99E-07 2.99E-07 sec 2 1.08E-05 1.08E-05 W-s/C 4.40E-06 4.40E-06 sec 3 3.24E-05 3.24E-05 W-s/C 4.36E-05 4.36E-05 sec 4 9.71E-05 9.71E-05 W-s/C 3.59E-04 3.74E-04 sec 5 6.28E-04 7.55E-04 W-s/C 3.17E-03 4.59E-03 sec 6 7.13E-03 1.49E-02 W-s/C 0.030 0.162 sec 7 1.54E-02 9.28E-02 W-s/C 0.341 0.473 sec 8 6.16E-02 1.72E-01 W-s/C 2.909 1.653 sec 9 1.94E-01 3.83E-01 W-s/C 16.126 8.488 sec 10 1.52E+00 2.41E+00 W-s/C 54.334 71.562 sec R's R's R's R's 1 0.161 0.161 C/W 0.11 0.11 C/W 2 0.482 0.482 C/W 0.26 0.26 C/W 3 1.445 1.445 C/W 0.73 0.73 C/W 4 3.00 3.00 C/W 2.60 2.83 C/W 5 4.47 5.34 C/W 4.80 5.82 C/W 6 5.92 12.21 C/W 2.98 8.95 C/W 7 20.11 16.03 C/W 12.20 0.61 C/W 8 51.85 4.89 C/W 26.10 12.91 C/W 9 68.87 15.34 C/W 62.22 16.96 C/W 10 27.52 22.36 C/W 71.83 32.09 C/W NOTE: Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network are computed by the square root of time constant R(t) = 225 * sqrt(time(sec)). The constant is derived based on the active area of the device with silicon and epoxy at the interface of the heat generation. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: n R(t) + S Riǒ1-e-tńtauiǓ i+1 http://onsemi.com 19 NCV8508 qJA (°C/W) qJA vs Copper Spreader Area 200 190 180 170 160 150 140 130 120 110 1 oz 100 90 2 oz 80 70 60 0 50 100150200250300350400450500550600650700750800 COPPER AREA (mm2) Figure 35. SOIC 8-Lead EP qJA as a Function of the Pad Copper Area Including Traces, Board Material 1000 Cu Area 54 mm2 R(t) (°C/W) 100 Cu Area 717 mm2 10 1 0.1 0.000001 0.00001 0.0001 0.001 0.1 0.01 1 10 100 1000 Time (sec) Figure 36. SOIC 8-Lead EP Single Pulse Heating Curve 100 50% Duty Cycle R(t) (°C/W) 20% 10 10% 5% 1 1% Cu Area 767 mm2, 1 oz Cu Single 0.1 0.000001 0.00001 0.0001 0.001 0.1 0.01 Time (sec) 1 10 Figure 37. SOIC 8-Lead Thermal Duty Cycle Curves on 1” Spreader Test Board http://onsemi.com 20 100 1000 NCV8508 R1 Junction C1 R2 C2 R3 C3 Rn Cn Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Ambient (thermal ground) Figure 38. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 C1 R2 C2 R3 C3 Rn Cn Each rung is exactly characterized by its RC-product time constant; amplitudes are the resistances. Ambient (thermal ground) Figure 39. Non-Grounded Capacitor Thermal Ladder (“Foster” Ladder) http://onsemi.com 21 NCV8508 APPLICATION NOTES Calculating Power Dissipation in a Single Output Linear Regulator The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJAs less than the calculated value in Equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. The maximum power dissipation for a single output regulator (Figure 40) is: PD(max) + [VIN(max) * VOUT(min)]IOUT(max) (1) ) VIN(max)IQ where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). IIN VIN Heatsinks A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: IOUT SMART REGULATOR® } RqJA + RqJC ) RqCS ) RqSA VOUT where: RqJC = the junction-to-case thermal resistance, RqCS = the case-to-heatsink thermal resistance, and RqSA = the heatsink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in data sheets of heatsink manufacturers. Control Features IQ Figure 40. Single Output Regulator with Key Performance Parameters Labeled Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: T RqJA + 150°C * A PD (3) (2) http://onsemi.com 22 NCV8508 ORDERING INFORMATION Device NCV8508DW50 NCV8508DW50G NCV8508DW50R2 NCV8508DW50R2G NCV8508D2T50 NCV8508D2T50G NCV8508D2T50R4 NCV8508D2T50R4G NCV8508PD50 NCV8508PD50G NCV8508PD50R2 NCV8508PD50R2G Output Voltage Package Shipping† 5.0 V SO-16L 47 Units / Rail 5.0 V SO-16L (Pb-Free) 47 Units / Rail 5.0 V SO-16L 1000 / Tape & Reel 5.0 V SO-16L (Pb-Free) 1000 / Tape & Reel 5.0 V D2PAK-7 50 Units / Rail 5.0 V D2PAK-7 (Pb-Free) 50 Units / Rail 5.0 V D2PAK-7 750 / Tape & Reel 5.0 V D2PAK-7 (Pb-Free) 750 / Tape & Reel 5.0 V SO-8 EP 98 Units / Rail 5.0 V SO-8 EP (Pb-Free) 98 Units / Rail 5.0 V SO-8 EP 2500 / Tape & Reel 5.0 V SO-8 EP (Pb-Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 23 NCV8508 PACKAGE DIMENSIONS SO-16L DW SUFFIX CASE 751G-03 ISSUE C A D 9 1 8 16X M 14X e T A S B h X 45 _ S L A 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ B B SEATING PLANE A1 H E 0.25 8X M B M 16 q T C http://onsemi.com 24 NCV8508 PACKAGE DIMENSIONS SOIC-8 EP PD SUFFIX CASE 751AC-01 ISSUE A 2X NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS (ANGLES IN DEGREES). 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE “b” DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. 0.10 C A-B D 8 E1 2X 0.10 C D 1 F EXPOSED PAD 5 ÉÉÉ ÉÉÉ PIN ONE LOCATION DETAIL A D A 5 8 G E h 2X 4 4 0.20 C e 8X b 0.25 C A-B D B 1 BOTTOM VIEW A TOP VIEW A 0.10 C A2 b1 GAUGE PLANE 0.10 C L SEATING PLANE C SIDE VIEW ÉÉ ÉÉ ÇÇ ÉÉ ÇÇ ÉÉ c H 8X A END VIEW A1 0.25 (L1) DETAIL A q c1 (b) SECTION A-A SOLDERING FOOTPRINT* 2.72 0.107 1.52 0.060 7.0 0.275 Exposed Pad 4.0 0.155 2.03 0.08 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 25 DIM A A1 A2 b b1 c c1 D E E1 e L L1 F G h q MILLIMETERS MIN MAX 1.35 1.75 0.00 0.10 1.35 1.65 0.31 0.51 0.28 0.48 0.17 0.25 0.17 0.23 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 1.04 REF 2.24 3.20 1.55 2.51 0.25 0.50 0_ 8_ NCV8508 PACKAGE DIMENSIONS D2PAK-7 (SHORT LEAD) DP SUFFIX CASE 936AB-01 ISSUE A K NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. TERMINAL 8 A U E S B DIM A B C D E G H K L M N P R S U V V M H L P D G N R INCHES MIN MAX 0.396 0.406 0.326 0.336 0.170 0.180 0.026 0.036 0.045 0.055 0.050 REF 0.539 0.579 0.055 0.066 0.000 0.010 0.100 0.110 0.017 0.023 0.058 0.078 0° 8° 0.095 0.105 0.256 REF 0.305 REF MILLIMETERS MIN MAX 10.05 10.31 8.28 8.53 4.31 4.57 0.66 0.91 1.14 1.40 1.27 REF 13.69 14.71 1.40 1.68 0.00 0.25 2.54 2.79 0.43 0.58 1.47 1.98 0° 8° 2.41 2.67 6.50 REF 7.75 REF C SOLDERING FOOTPRINT* 9.5 0.374 2.16 0.085 1.27 0.050 3.25 0.128 CL 10.54 0.415 CL 3.8 0.150 1 0.96 0.038 8.26 0.325 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT:  Literature Distribution Center for ON Semiconductor  P.O. Box 5163, Denver, Colorado 80217 USA  Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada  Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada  Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free  USA/Canada Europe, Middle East and Africa Technical Support:  Phone: 421 33 790 2910 Japan Customer Focus Center  Phone: 81-3-5773-3850 http://onsemi.com 26 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCV8508/D
NCV8508PD50R2 价格&库存

很抱歉,暂时无法提供与“NCV8508PD50R2”相匹配的价格&库存,您可以联系我们找货

免费人工找货