NCV887302D1R2G

DATA SHEET www.onsemi.com Automotive Grade Non-Synchronous Boost Controller 8 1 SOIC−8 D SUFFIX CASE 751 NCV8873 The NCV8873 is an adjustable output non−synchronous boost controller which drives an external N−channel MOSFET. The device uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate driver. Protection features include internally−set soft−start, undervoltage lockout, cycle−by−cycle current limiting and thermal shutdown. Additional features include low quiescent current sleep mode and externally−synchronizable switching frequency. Features • • • • • • • • • • • Peak Current Mode Control with Internal Slope Compensation 0.2 V $3% Reference Voltage for Constant Current Loads Fixed Frequency Operation Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump Input Undervoltage Lockout (UVLO) Internal Soft−Start Low Quiescent Current in Sleep Mode Cycle−by−Cycle Current Limit Protection Thermal Shutdown (TSD) This is a Pb−Free Device NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable MARKING DIAGRAM 8 8873xxG ALYW G 1 8873xxG= Specific Device Code xx = 02 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package PIN CONNECTIONS EN/SYNC 1 8 VFB ISNS 2 7 VC GND 3 6 VIN GDRV 4 5 VDRV (Top View) ORDERING INFORMATION Device NCV887302D1R2G Package SOIC−8 (Pb−Free) Shipping† 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2017 November, 2021 − Rev. 11 1 Publication Order Number: NCV8873/D NCV8873 6 TEMP VDRV FAULT LOGIC EN/SYNC 1 CLK OSC SC VC DRIVE LOGIC 4 2 CL 7 CSA 3 + RC 8 Gm CC Cg CDRV VDRV L SS MURA110T3G Vo Q GDRV NVTFS5826NL PWM EN/ SYNC 5 Vg VIN D2 Co ISNS GND RSNS Dn VFB RF1 Vref Figure 1. Simplified Block Diagram and Example Application Schematic PACKAGE PIN DESCRIPTIONS Pin No. Pin Symbol 1 EN/SYNC 2 ISNS Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense resistor to ground to sense the switching current for regulation and current limiting. 3 GND Ground reference. 4 GDRV Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance. 5 VDRV Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass with a 1.0 mF ceramic capacitor to ground. 6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addition to a diode from the output voltage to VDRV and/or VIN. 7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize the converter. 8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND creates a voltage divider for regulation and programming of the output voltage. Function Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled into sleep mode when this pin is brought low for longer than the enable time−out period. www.onsemi.com 2 NCV8873 ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated) Rating Value Unit −0.3 to 40 V Peak Transient Voltage (Load Dump on VIN) 45 V Dc Supply Voltage (VDRV, GDRV) 12 V −0.3 to 6 V −0.3 to 3.6 V Dc Voltage (EN/SYNC) −0.3 to 6 V Dc Voltage Stress (VIN − VDRV)* −0.7 to 40 V Operating Junction Temperature −40 to 150 °C Storage Temperature Range −65 to 150 °C Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C 265 peak °C Dc Supply Voltage (VIN) Peak Transient Voltage (VFB) Dc Voltage (VC, VFB, ISNS) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. *An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage. PACKAGE CAPABILITIES Characteristic ESD Capability (All Pins) Human Body Model Machine Model Moisture Sensitivity Level 1. 1 Unit w2.0 w200 KV V 1 Package Thermal Resistance in2, Value 100 Junction−to−Ambient, RqJA (Note 1) °C/W 1 oz copper area used for heatsinking. Ordering Options The NCV8873 features several variants to better fit a multitude of applications. The table below shows the typical values of parameters for the parts that are currently available. TYPICAL VALUES YY Dmax fs tss Sa Vcl Isrc Isink VDRV NCV887302 92.5% 400 kHz 4.0 ms 51 mV/ms 200 mV 800 mA 600 mA 6.3 V DEFINITIONS Symbol Dmax Characteristic Maximum duty cycle Symbol Characteristic Symbol Characteristic fs Switching frequency tss Soft−start time Current limit trip voltage Isrc Gate drive sourcing current Sa Slope compensating ramp Vcl Isink Gate drive sinking current VDRV Drive voltage www.onsemi.com 3 NCV8873 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. Characteristic Symbol Conditions Min Typ Max Unit mA GENERAL Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, TJ = 25°C − 2.0 − Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, −40°C < TJ < 125°C − 2.0 6.0 mA Quiescent Current, No switching Iq,off Into VIN pin, EN = 1, No switching − 1.5 2.5 mA Quiescent Current, Switching, normal operation Iq,on Into VIN pin, EN = 1, Switching − 4.0 6.0 mA 90 115 140 ns OSCILLATOR Minimum pulse width ton,min Maximum duty cycle Dmax YY = 02 90 92.5 95 % Switching frequency fs YY = 02 360 400 440 kHz Soft−start time tss From start of switching with VFB = 0 until reference voltage = VREF YY = 02 3.3 4.0 4.7 From EN → 1 until start of switching with VFB = 0 with floating VC pin − 240 280 YY = 02 44 51 58 mV/ms VEN/SYNC = 5 V − 5.0 10 mA 2.0 − 5.0 V 0 − 800 mV From SYNC falling edge, to oscillator control (EN high) or shutdown (EN low), Percent of typical switching frequency − − 350 % Percent of fs − − 80 % 1.1 − − MHz − 50 100 ns 25 − 75 % Input−to−output gain at dc, ISNS v 1 V 0.9 1.0 1.1 V/V 2.5 − − MHz − 30 50 mA 180 200 220 − 80 125 ns 125 150 175 % − 80 125 ns 0.8 1.2 1.63 mS 2.0 − − MW Soft−start delay Slope compensating ramp tss,dly Sa ms ms ENABLE/SYNCHRONIZATION EN/SYNC pull−down current IEN/SYNC EN/SYNC input high voltage Vs,ih EN/SYNC input low voltage Vs,il EN/SYNC time−out ratio %ten SYNC minimum frequency ratio SYNC maximum frequency %fsync,min VIN > VUVLO fsync,max Synchronization delay ts,dly Synchronization duty cycle Dsync From SYNC falling edge to GDRV falling edge under open loop conditions. CURRENT SENSE AMPLIFIER Low−frequency gain Acsa Bandwidth BWcsa Gain of Acsa − 3 dB ISNS input bias current Isns,bias Out of ISNS pin Current limit threshold voltage Vcl Voltage on ISNS pin YY = 02 Current limit, Response time tcl CL tripped until GDRV falling edge, VISNS = Vcl(typ) + 60 mV Overcurrent protection, Threshold voltage %Vocp Overcurrent protection, Response Time tocp Percent of Vcl From overcurrent event, Until switching stops, VISNS = VOCP + 40 mV mV VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER Transconductance gm,vea VEA output resistance Ro,vea VFB input bias current Ivfb,bias Reference voltage VFB – Vref = ± 20 mV Current out of VFB pin Vref www.onsemi.com 4 − 0.5 2.0 mA 0.194 0.200 0.206 V NCV8873 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. Characteristic Symbol Conditions Min Typ Max Unit VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER VEA maximum output voltage Vc,max 2.5 − − V VEA minimum output voltage Vc,min − − 0.3 V VEA sourcing current Isrc,vea VEA output current, Vc = 2.0 V 80 100 − mA VEA sinking current Isnk,vea VEA output current, Vc = 0.7 V 80 100 − mA GATE DRIVER Sourcing current Isrc VDRV ≥ 6 V, VDRV − VGDRV = 2 V YY = 02 600 800 − Sinking current Isink VGDRV ≥ 2 V YY = 02 500 600 − VIN − VDRV, IvDRV = 25 mA − 0.3 0.6 V VIN − VDRV = 1 V 35 45 − mA − − 0.7 V 6.0 6.3 6.6 − 15 − kW Driving voltage dropout Vdrv,do Driving voltage source current Idrv Backdrive diode voltage drop Vd,bd VDRV − VIN, Id,bd = 5 mA Driving voltage VDRV IVDRV = 0.1 − 25 mA YY = 02 Pull−down resistance Rpd mA mA V UVLO Undervoltage lock−out, Threshold voltage Vuvlo VIN falling 2.95 3.05 3.15 V Undervoltage lock−out, Hysteresis Vuvlo,hys VIN rising 50 150 250 mV Thermal shutdown threshold Tsd TJ rising 160 170 180 °C Thermal shutdown hysteresis Tsd,hys TJ falling 10 15 20 °C Thermal shutdown delay tsd,dly From TJ > Tsd to stop switching − − 100 ns THERMAL SHUTDOWN Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 5 NCV8873 TYPICAL PERFORMANCE CHARACTERISTICS 6 TJ = 25°C 6 Iq,sleep, SLEEP CURRENT (mA) Iq,sleep, SLEEP CURRENT (mA) 7 5 4 3 2 1 0 0 10 20 30 VIN, INPUT VOLTAGE (V) 4 3 2 1 0 −50 40 Figure 2. Sleep Current vs. Input Voltage 125 ton,min MINIMUM ON TIME (ns) Iq,on, QUIESCENTCURRENT (mA) 200 VIN = 13.2 V 4.7 4.6 4.5 4.4 400 kHz 4.3 4.2 4.1 −40 10 60 110 TJ, JUNCTION TEMPERATURE (°C) 123 121 119 117 115 −40 160 Figure 4. Quiescent Current vs. Temperature 10 60 110 TJ, JUNCTION TEMPERATURE (°C) 160 Figure 5. Minimum On Time vs. Temperature 202.2 1.010 Vref, REFERENCE VOLTAGE (V) NORMALIZED CURRENT LIMIT (25°C) 150 0 50 100 TJ, JUNCTION TEMPERATURE (°C) Figure 3. Sleep Current vs. Temperature 4.9 4.8 VIN = 13.2 V 5 1.005 202 201.8 1.000 201.6 0.995 0.990 −40 201.4 10 60 110 TJ, JUNCTION TEMPERATURE (°C) 160 201.2 −40 10 60 110 TJ, JUNCTION TEMPERATURE (°C) Figure 6. Normalized Current Limit vs. Temperature Figure 7. Reference Voltage vs. Temperature www.onsemi.com 6 160 NCV8873 TYPICAL PERFORMANCE CHARACTERISTICS 8.0 TJ = 25°C 6 Ienable, PULLDOWN CURRENT (mA) Ienable, PULLDOWN CURRENT (mA) 7 5 4 3 2 1 0 0 1 2 3 4 Venable, VOLTAGE (V) 5 6 7.5 7.0 6.5 6.0 5.5 5.0 −40 10 60 110 TJ, JUNCTION TEMPERATURE (°C) Figure 8. Enable Pulldown Current vs. Voltage Figure 9. Enable Pulldown Current vs. Temperature www.onsemi.com 7 160 NCV8873 THEORY OF OPERATION Vg L D1 Oscillator VO S GDRV Q Q D2 Gate Driver R PWM CO ISNS Comparator RSNS CSA Slope Compensation Dn VFB Gm RF1 VREF NCV8873 Compensation Figure 10. Current Mode Control Schematic Current Mode Control EN/SYNC The NCV8873 incorporates a current mode control scheme, in which the PWM ramp signal is derived from the power switch current. This ramp signal is compared to the output of the error amplifier to control the on−time of the power switch. The oscillator is used as a fixed−frequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over conventional voltage mode control. First, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the output filter and error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from inherent pulse−by−pulse current limiting by merely clamping the peak switching current. Finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. This allows for a simpler compensation. The NCV8873 also includes a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. A proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. This pin has three modes. When a dc logic high (CMOS/TTL compatible) voltage is applied to this pin the NCV8873 operates at the programmed frequency. When a dc logic low voltage is applied to this pin the NCV8873 enters a low quiescent current sleep mode. When a square wave of at least %fsync,min of the free running switching frequency is applied to this pin, the switcher operates at the same frequency as the square wave. If the signal is slower than this, it will be interpreted as enabling and disabling the part. The falling edge of the square wave corresponds to the start of the switching cycle. If an Enable command is received during normal operation, the minimum duration of the Enable low−state must be greater than 7 clock cycles. If the VIN pin voltage falls below VUVLO when EN/SYNC pin is at logic−high, the IC may not power up when VIN returns back above the UVLO. To resume a normal operating state, the EN/SYNC pin must be cycled with a single logic−low to logic−high transition. UVLO Input Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VIN is too low to support the internal rails and power the controller. The IC will start up when enabled and VIN surpasses the UVLO threshold plus the UVLO hysteresis and will shut down when VIN drops below the UVLO threshold or the part is disabled. To avoid any lock state under UVLO conditions, the EN/SYNC pin should be in logic−low state. For further details, please refer to EN/SYNC paragraph. Current Limit The NCV8873 features a peak current−mode current limit protection. When the current sense amplifier detects a voltage above the peak current limit between ISNS and GND after the current limit leading edge blanking time, the peak current limit causes the power switch to turn off for the remainder of the cycle. Set the current limit with a resistor from ISNS to GND, with R = VCL / Ilimit. If the voltage across the current sense resistor exceeds the over current threshold voltage the part enters soft−start mode. Internal Soft−Start To insure moderate inrush current and reduce output overshoot, the NCV8873 features a soft start which charges a capacitor with a fixed current to ramp up the reference voltage. www.onsemi.com 8 NCV8873 This fixed current is based on the switching frequency, so that if the NCV8873 is synchronized to twice the default switching frequency the soft start will last half as long. APPLICATION INFORMATION Design Methodology Both duty cycles will actually be slightly higher due to power loss in the conversion. The exact duty cycles depend on conduction and switching losses. If the maximum input voltage is higher than the output voltage, the minimum duty cycle will be a complex value. This is because a Boost converter cannot have an output voltage lower than the input voltage. In situations where the input voltage is higher than the output, the output will follow the input (minus the diode drop of the Boost diode) and the converter will not attempt to switch. If the inductor value is too large, continuous conduction mode (CCM) operation will occur and a right-half-plane (RHP) zero appears which can result in operation instability. If the calculated Dmax is higher than the Dmax of the NCV8873, the conversion will not be possible. It is important for a Boost converter to have a restricted Dmax, because while the ideal conversion ration of a Boost converter goes up to infinity as D approaches 1, a real converter’s conversion ratio starts to decrease as losses overtake the increased power transfer. If the converter is in this range it will not be able to maintain output regulation. If the following equation is not satisfied, the device will skip pulses at high VIN: This section details an overview of the component selection process for the NCV8873 in discontinuous conduction mode (DCM) Boost converter operation with a high brightness LED (100−150 mA typical) string as a load. LED current is used for the feedback signal. It is intended to assist with the design process but does not remove all engineering design work. Many of the equations make use of the small ripple approximation. This process entails the following steps: 1. Define Operational Parameters 2. Select Current Sense Resistor 3. Select Output Inductor 4. Select Output Capacitors 5. Select Input Capacitors 6. Select Feedback Resistors 7. Select Compensator Components 8. Select MOSFET(s) 9. Select Diode 1. Define Operational Parameters Before beginning the design, define the operating parameters of the application. These include: VIN(min): minimum input voltage [V] VIN(max): maximum input voltage [V] VOUT: output voltage [V] ILED: LED current [A] ICL: desired typical cycle-by-cycle current limit [A] Vref: NCV8873 feedback reference voltage = 0.2 V IL: inductor current [A] D min w t on(min) fs Where: fs: switching frequency [Hz] ton(min): minimum on time [s] 2. Select Current Sense Resistor Current sensing for peak current mode control and current limit relies on the MOSFET current signal, which is measured with a ground referenced amplifier. The easiest method of generating this signal is to use a current sense resistor between the MOSFET source and ground. The sense resistor should be selected as follows: From this the ideal minimum and maximum duty cycles can be calculated as follows: M min + V out V in(max) M max + V out V in(min) R out + D max + Ǹ Ǹ ƪ V CL I CL Where: RSNS: sense resistor [W] VCL: current limit threshold voltage [V] ICL: desired current limit [A] V out I LED D min + d+ R SNS + ƫ 2 Lf s ǒ2M min * 1Ǔ * 1 2R out 3. Select the Boost Inductor The Boost inductor controls the current ripple that occurs over a switching period. A discontinuous current ripple will result in superior transient response and lower switching noise at the expense of higher transistor conduction losses and operating ripple current requirements. A low current ripple will result in CCM operation having a slower response current slew rate in case of load steps (e.g. introducing an Lf s ƪ(2Mmax * 1)2 * 1ƫ 2R out 2V out 2 *D, V inR outI L,peak Where: (D + d) < 1 for DCM operation IL. www.onsemi.com 9 NCV8873 the dynamic response according to system requirements. A transconductance amplifier is used, so compensation components must be connected between the compensation pin and ground. LED series dimming circuit). A good starting point is to select components for DCM operation at Vin(min), but operation should be verified empirically. Calculate the maximum inductor value as follows: L max + ǒ1 * M1 ǓV max in(min) 2 ǒ Ǔ Vout ILED 8. Select MOSFET(s) In order to ensure the gate drive voltage does not drop out, the selected MOSFET must not violate the following inequality: 2f sV out 2 The maximum average inductor current can be calculated as follows: I L,avg + Q g(total) v V OUTI OUT(max) Where: Qg(total): Total Gate Charge of MOSFET(s) [C] Idrv: Drive voltage current [A] fs: Switching Frequency [Hz] The maximum RMS Current can be calculated as follows: V IN(min) The peak inductor current can be calculated as follows: I L,peak + V IN(min)D max Lf s I Q(max) + I L,peak Where: IL,peak: Peak inductor current value [A] The output capacitor smoothes the output voltage and reduces the overshoot and undershoot associated with line transients. The steady state output ripple associated with the output capacitors can be calculated as follows: 9. Select Diode The output diode rectifies the output current. The average current through diode will be equal to the output current: The capacitors must withstand an RMS ripple current as follows: I Cout(RMS) + Ǹ I LED ) d(M max) ǒ I L,pk 2 3 I D(avg) + I OUT(max) Additionally, the diode must block voltage equal to the higher of the output voltage or the maximum input voltage: Ǔ * I L,pkI LED V D(max) + V OUT A 2.2 mF ceramic capacitor is usually sufficient for high brightness LED applications for fs = 1 MHz. The maximum power dissipation in the diode can be calculated as follows: P D + V f (max)I OUT(max) 5. Select Input Capacitors The input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. I Cin(RMS) + Ǹǒ Where: Pd: Power dissipation in the diode [W] Vf(max): Maximum forward voltage of the diode [V] Ǔ D(M max) ) d (M max) I L,pk 2 * I L,avg 2 3 Low Voltage Operation If the input voltage drops below the UVLO or MOSFET threshold voltage, another voltage may be used to power the device. Simply connect the voltage you would like to boost to the inductor and connect the stable voltage to the VIN pin of the device. In Boost configuration, the output of the converter can be used to power the device. In some cases it may be desirable to connect 2 sources to VIN pin, which can be accomplished simply by connecting each of the sources through a diode to the VIN pin. 6. Select Feedback Resistors The feedback resistor provides LED current sensing for the feedback signal. It may be calculated as follows: R F1 + max) V Q(max) + V OUT(max) I LEDǒ1 * d (M max)Ǔ f sC OUT 2 ǸD(M3 The maximum voltage across the MOSFET will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltage: 4. Select Output Capacitor V OUT(ripple) + I drv fs V ref I LED 7. Select Compensator Components Current Mode control method employed by the NCV8873 allows the use of a simple Type II compensation to optimize www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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