NDD04N50ZT4G

NDP04N50Z, NDD04N50Z N-Channel Power MOSFET 500 V, 2.7 W Features • • • • Low ON Resistance Low Gate Charge 100% Avalanche Tested These Devices are Pb−Free and are RoHS Compliant VDSS 500 V http://onsemi.com RDS(on) (MAX) @ 1.5 A 2.7 W ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Continuous Drain Current RqJC Continuous Drain Current RqJC, TA = 100°C Pulsed Drain Current, VGS @ 10 V Power Dissipation RqJC Gate−to−Source Voltage Single Pulse Avalanche Energy, ID = 3.4 A ESD (HBM) (JESD22−A114) Peak Diode Recovery Continuous Source Current (Body Diode) Maximum Temperature for Soldering Leads Operating Junction and Storage Temperature Range Symbol VDSS ID ID IDM PD VGS EAS Vesd dv/dt IS TL TJ, Tstg 3.4 2.1 14 75 ±30 120 2800 4.5 (Note 1) 3.4 260 − 55 to 150 NDP 500 3.0 1.9 12 61 NDD Unit V A A A W V mJ N−Channel D (2) G (1) S (3) V V/ns A °C °C 12 4 4 1 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. ID v 3.4 A, di/dt ≤ 200 A/ms, VDD ≤ BVDSS, TJ ≤ 150°C. 3 TO−220AB CASE 221A STYLE 5 2 3 IPAK CASE 369D STYLE 2 2 3 DPAK CASE 369AA STYLE 2 MARKING AND ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2010 July, 2010 − Rev. 0 1 Publication Order Number: NDD04N50Z/D NDP04N50Z, NDD04N50Z THERMAL RESISTANCE Parameter Junction−to−Case (Drain) Junction−to−Ambient Steady State NDP04N50Z NDD04N50Z (Note 2) NDP04N50Z (Note 3) NDD04N50Z (Note 2) NDD04N50Z−1 Symbol RqJC RqJA Value 1.6 2.0 51 40 80 Unit °C/W 2. Insertion mounted 3. Surface mounted on FR4 board using 1″ sq. pad size, (Cu area = 1.127 in sq [2 oz] including traces). ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Drain−to−Source Leakage Current BVDSS DBVDSS/ DTJ IDSS IGSS RDS(on) VGS(th) gFS Ciss Coss Crss Qg Qgs Qgd VGP Rg td(on) tr td(off) tf VDD = 250 V, ID = 3.4 A, VGS = 10 V, RG = 5 W VDD = 250 V, ID = 3.4 A, VGS = 10 V VGS = 0 V, ID = 1 mA Reference to 25°C, ID = 1 mA VDS = 500 V, VGS = 0 V VGS = ±20 V VGS = 10 V, ID = 1.5 A VDS = VGS, ID = 50 mA VDS = 15 V, ID = 1.5 A 3.0 2.1 308 VDS = 25 V, VGS = 0 V, f = 1.0 MHz 43 9 12 2.6 6.1 6.6 5.4 9 9 16 10 V W ns nC 2.3 25°C 150°C 500 0.6 1 50 ±10 2.7 4.5 mA W V S pF V V/°C mA Symbol Test Conditions Min Typ Max Unit Gate−to−Source Forward Leakage ON CHARACTERISTICS (Note 4) Static Drain−to−Source On−Resistance Gate Threshold Voltage Forward Transconductance DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate−to−Source Charge Gate−to−Drain (“Miller”) Charge Plateau Voltage Gate Resistance Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time RESISTIVE SWITCHING CHARACTERISTICS SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C unless otherwise noted) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge 4. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%. VSD trr Qrr IS = 3.4 A, VGS = 0 V VGS = 0 V, VDD = 30 V IS = 3.4 A, di/dt = 100 A/ms 240 0.9 1.6 V ns mC http://onsemi.com 2 NDP04N50Z, NDD04N50Z 4.0 3.5 ID, DRAIN CURRENT (A) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 5.0 V 5.0 10.0 15.0 20.0 25.0 5.5 V 6.0 V VGS = 10 V 7.0 V 6.5 V ID, DRAIN CURRENT (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3 TJ = 150°C TJ = 25°C VDS = 25 V TJ = −55°C 5 6 7 8 9 10 4 Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 4.00 3.75 3.50 3.25 3.00 2.75 2.50 2.25 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 ID = 1.5 A TJ = 25°C 4.00 3.75 VGS = 10 V TJ = 25°C 3.50 3.25 3.00 2.75 2.50 2.25 2.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 10.0 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Region versus Gate−to−Source Voltage BVDSS, NORMALIZED BREAKDOWN VOLTAGE (V) Figure 4. On−Resistance versus Drain Current and Gate Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 −50 −25 0 25 50 75 100 125 ID = 1.5 A VGS = 10 V 1.15 ID = 1 mA 1.10 1.05 1.00 0.95 0.90 −50 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature Figure 6. BVDSS Variation with Temperature http://onsemi.com 3 NDP04N50Z, NDD04N50Z 10.0 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 TJ = 25°C VGS = 0 V f = 1 MHz Ciss Coss Crss 1.0 TJ = 150°C TJ = 125°C 0.1 0 50 100 150 200 250 300 350 400 450 500 VDS, DRAIN−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) IDSS, LEAKAGE (mA) 0.01 0.1 1 10 100 Figure 7. Drain−to−Source Leakage Current versus Voltage VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 8. Capacitance Variation 10 VDS 8 6 4 2 0 QGD QT VGS QGS 250 200 150 100 VDS = 250 V ID = 3.4 A TJ = 25°C 0 1 2 3 4 5 6 7 8 9 10 11 50 0 12 Qg, TOTAL GATE CHARGE (nC) Figure 9. Gate−to−Source Voltage and Drain−to−Source Voltage versus Total Charge 1000 IS, SOURCE CURRENT (A) VDD = 250 V ID = 3.4 A VGS = 10 V 100 t, TIME (ns) td(off) tr tf td(on) 10.0 1.0 TJ = 150°C 10 125°C 25°C −55°C 0.1 0.3 1 1 10 RG, GATE RESISTANCE (W) 100 0.4 0.5 0.6 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.7 0.8 VGS, GATE−TO−SOURCE VOLTAGE (V) 12 300 0.9 1.0 1.1 1.2 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 10. Resistive Switching Time Variation versus Gate Resistance Figure 11. Diode Forward Voltage versus Current http://onsemi.com 4 NDP04N50Z, NDD04N50Z 100 VGS v 30 V SINGLE PULSE TC = 25°C ID, DRAIN CURRENT (A) 10 100 ms 10 ms 1 ms 10 ms dc 1 0.1 0.01 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 1000 Figure 12. Maximum Rated Forward Biased Safe Operating Area NDD04N50Z VDS, DRAIN−TO−SOURCE VOLTAGE (V) 10 1 R(t) (C/W) 50% (DUTY CYCLE) 20% 10% 5.0% 0.1 2.0% 1.0% SINGLE PULSE RqJA = 2°C/W Steady State 1E−04 1E−03 1E−02 1E−01 PULSE TIME (s) 1E+00 1E+01 1E+02 1E+03 0.01 1E−06 1E−05 Figure 13. Thermal Impedance (Junction−to−Case) for NDD04N50Z 100 R(t) (C/W) 10 50% (DUTY CYCLE) 20% 10% 5.0% 1 2.0% 1.0% 0.1 RqJA = 40°C/W Steady State 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03 0.01 1E−06 SINGLE PULSE 1E−05 PULSE TIME (s) Figure 14. Thermal Impedance (Junction−to−Ambient) for NDD04N50Z http://onsemi.com 5 NDP04N50Z, NDD04N50Z ORDERING INFORMATION Order Number NDP04N50ZG NDD04N50Z−1G NDD04N50ZT4G Package TO−220AB (Pb−Free) IPAK (Pb−Free) DPAK (Pb−Free) Shipping† 50 Units / Rail (In Development) 75 Units / Rail 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS 4 Drain YWW 4N 50ZG 4 Drain YWW 4N 50ZG 2 1 Drain 3 Gate Source NDP04N50ZG AYWW Gate Source 1 23 Gate Drain Source Drain A Y WW G = Location Code = Year = Work Week = Pb−Free Package http://onsemi.com 6 NDP04N50Z, NDD04N50Z PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AF −T− B 4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.161 0.095 0.105 0.110 0.155 0.014 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ----0.080 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 4.09 2.42 2.66 2.80 3.93 0.36 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ----2.04 F T C S Q 123 A U K H Z L V G D N R J STYLE 5: PIN 1. 2. 3. 4. http://onsemi.com 7 NDP04N50Z, NDD04N50Z PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B C A B c2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− E b3 L3 1 4 A D 2 3 Z DETAIL A H L4 b2 e b 0.005 (0.13) M c C L2 GAUGE PLANE H C L L1 DETAIL A SEATING PLANE A1 ROTATED 90 CW 5 SOLDERING FOOTPRINT* 6.20 0.244 3.00 0.118 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 2.58 0.102 5.80 0.228 1.60 0.063 6.17 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 NDP04N50Z, NDD04N50Z PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE B B V R 4 C E Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− S −T− SEATING PLANE A 1 2 3 K F D G 3 PL J H M 0.13 (0.005) T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. 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