NDS8435

May 1996 NDS8435 Single P-Channel Enhancement Mode Field Effect Transistor General Description Features SO-8 P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. -7A, -30V. RDS(ON) = 0.028Ω @ VGS = -10V RDS(ON) = 0.045Ω @ VGS = -4.5V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. ___________________________________________________________________________________________ Absolute Maximum Ratings 4 6 3 7 2 8 1 T A = 25°C unless otherwise noted Symbol Parameter VDSS VGSS ID Drain Current - Continuous PD Maximum Power Dissipation NDS8435 Units Drain-Source Voltage -30 V Gate-Source Voltage -20 V -7 A (Note 1a) - Pulsed TJ,TSTG 5 -25 (Note 1a) 2.5 (Note 1b) 1.2 (Note 1c) 1 Operating and Storage Temperature Range W -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W © 1997 Fairchild Semiconductor Corporation NDS8435 Rev. B2 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min -30 Typ Max Units -1 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V V -10 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA V TJ = 55°C ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA TJ = 125°C RDS(ON) Static Drain-Source On-Resistance -1 -1.5 -3 -0.7 -1.1 -2.2 0.023 0.028 0.038 0.06 0.037 0.045 VGS = -10 V, ID = -7.0 A TJ = 125°C VGS = -4.5 V, ID = -5.8 A ID(on) On-State Drain Current gFS Forward Transconductance VGS = -10 V, VDS = -5 V -25 VGS = -4.5, VDS = -5 V -10 Ω A VDS = -10 V, ID = -7.0 A 10 S VDS = -15 V, VGS = 0 V, f = 1.0 MHz 1500 pF 950 pF 370 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time 12 30 ns 18 30 ns tD(off) tf Turn - Off Delay Time 65 120 ns Turn - Off Fall Time 49 80 ns Qg Total Gate Charge Qgs Gate-Source Charge 47 60 nC Qgd Gate-Drain Charge VDD = -10 V, ID = -1 A, VGEN = -10 V, RGEN = 6 Ω VDS = -15 V, ID = -7.0 A, VGS = -10 V 5.5 nC 14 nC NDS8435 Rev. B2 Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units -2.1 A -1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -2.1 A -0.8 (Note 2) Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t ) = T J−TA R θJ A(t ) = T J−TA R θJ C+RθCA(t ) = I 2D (t ) × RDS(ON ) TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 50oC/W when mounted on a 1 in2 pad of 2oz copper. b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper. c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS8435 Rev. B2 Typical Electrical Characteristics 3 -6.0 -5.0-4.5 -25 -4.0 -20 R DS(on), NORMALIZED I D , DRAIN-SOURCE CURRENT (A) VGS = -10V -3.5 -15 -3.0 -10 -5 -2.5 DRAIN-SOURCE ON-RESISTANCE -30 0 VGS = -3.0V 2.5 -3.5 2 -4.0 -4.5 1.5 -5.0 -6.0 -10 1 0.5 0 -0.5 -1 -1.5 -2 V DS , DRAIN-SOURCE VOLTAGE (V) -2.5 0 -3 Figure 1. On-Region Characteristics. I D =-7.0A 1.4 R DS(on) , NORMALIZED V GS = -10V 1.2 1 0.8 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED -25 -30 2 0.6 -50 V GS = -10V T J = 125°C 1.5 25°C 1 -55°C 0.5 -25 0 25 50 75 100 125 150 0 -5 TJ , JUNCTION TEMPERATURE (°C) -10 -15 -20 -25 -30 I D , DRAIN CURRENT (A) Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. 1.2 V DS = -10V T = -55°C J 125°C -16 V th , NORMALIZED 25°C -12 -8 -4 0 -1 -2 -3 -4 -5 V GS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. -6 GATE-SOURCE THRESHOLD VOLTAGE -20 ID , DRAIN CURRENT (A) -10 -15 -20 I D , DRAIN CURRENT (A) Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 DRAIN-SOURCE ON-RESISTANCE -5 VDS = VGS 1.1 I D = -250µA 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 6. Gate Threshold Variation with Temperature. NDS8435 Rev. B2 Typical Electrical Characteristics (continued) 20 I D = -250µA 1.08 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 -25 0 V GS = 0V 10 -I S , REVERSE DRAIN CURRENT (A) BV DSS, NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.1 25 50 75 100 125 5 T = 125°C J 1 0.01 0.4 T J , JUNCTION TEMPERATURE (°C) 0.6 0.8 1.2 Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 10 4000 V DS = -5.0V -V GS , GATE-SOURCE VOLTAGE (V) I D = -7.0A 2000 CAPACITANCE (pF) 1 -VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 7. Breakdown Voltage Variation with Temperature. C iss C oss 1000 800 500 C rss f = 1 MHz V GS = 0V 300 200 0.1 -15V 8 -10V 6 4 2 0 0.2 0.5 1 2 5 10 30 0 10 -V DS , DRAIN TO SOURCE VOLTAGE (V) 30 40 50 Figure 10. Gate Charge Characteristics. t on -VDD t d(on) t off tr RL V IN 20 Q g , GATE CHARGE (nC) Figure 9. Capacitance Characteristics. t d(off) tf 90% 90% V OUT D VGS -55°C 0.1 0.001 0.2 150 25°C 0.5 VOUT R GEN 10% 10% DUT G 90% S V IN 50% 50% 10% PULSE W IDTH Figure 11. Switching Test Circuit. INVERTED Figure 12. Switching Waveforms. NDS8435 Rev. B2 Typical Electrical and Thermal Characteristics (continued) 25 2.5 STEADY-STATE POWER DISSIPATION (W) TJ = -55°C 20 25°C 15 125°C 10 5 g FS , TRANSCONDUCTANCE (SIEMENS) V DS = -10V 0 0 -5 -10 -15 -20 I D , DRAIN CURRENT (A) -25 -30 1.5 1b 1c 1 4.5"x5" FR-4 Board o TA = 2 5 C Still Air 0.5 0 Figure 13. Transconductance Variation with Drain Current and Temperature. 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 50 30 10 -I D , DRAIN CURRENT (A) 1a 7 6 1b 1c 5 1 Figure 14. SO-8 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 8 4.5"x5" FR-4 Board IM )L 10 IT 1m 10 10 1 0m 0u s s ms s 1s 10 0.3 V 0.1 0.03 Still Air RD N S(O 3 TA = 2 5 o C GS DC = -10V s SINGLE PULSE RθJ A = See Note 1c TA = 25°C VG S = - 1 0 V 4 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 0.01 0.1 1 0.2 0.5 1 2 5 10 - V DS , DRAIN-SOURCE VOLTAGE (V) 30 50 Figure 16. Maximum Safe Operating Area. Figure 15. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. TRANSIENT THERMAL RESISTANCE 1 r(t), NORMALIZED EFFECTIVE -I D , STEADY-STATE DRAIN CURRENT (A) 1a 2 0 .5 D = 0.5 0 .2 0.2 0 .1 0 .0 5 R JA (t) = r(t) * R JA θ θ R JA = See Note 1c θ 0.1 0.05 P(pk) 0.02 0 .0 2 0.01 0 .0 1 t1 Single Pulse 0 .0 0 5 t2 TJ - T = P * R JA (t) θ Duty Cycle, D = t 1 / t 2 A 0 .0 0 2 0 .0 0 1 0 .0001 0 .001 0 .0 1 0 .1 1 10 100 300 t 1 , TIME (sec) Figure 17. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDS8435 Rev. B2