NLSX3373MUTAG

NLSX3373 2-Bit 20 Mb/s Dual-Supply Level Translator The NLSX3373 is a 2−bit configurable dual−supply bidirectional auto sensing translator that does not require a directional control pin. The VCC I/O and VL I/O ports are designed to track two different power supply rails, VCC and VL respectively. The VCC supply rail is configurable from 1.65 V to 4.5 V while VL supply rail is configurable to 1.2 V to 4.1 V. This allows lower voltage logic signals on the VL side to be translated into higher voltage logic signals on the VCC side, and vice−versa. The NLSX3373 translator has open−drain outputs with integrated 10 kW pullup resistors on the I/O lines. The integrated pullup resistors are used to pullup the I/O lines to either VL or VCC. The NLSX3373 is an excellent match for open−drain applications such as the I2C communication bus. http://onsemi.com MARKING DIAGRAM UDFN8 MU SUFFIX CASE 517AJ 8 1 VBM G VB = Specific Device Code M = Date Code G = Pb−Free Package Features • Wide High−Side VCC Operating Range: 1.65 V to 4.5 V Wide Low−Side VL Operating Range: 1.2 V to 4.1 V • High−Speed with 20 Mb/s Guaranteed Date Rate for VL > 2.5 V • Low Bit−to−Bit Skew • Enable Input and I/O Lines have Overvoltage Tolerant (OVT) to • • • • 4.5 V Nonpreferential Powerup Sequencing Integrated 10 kW Pullup Resistors Small Space Saving Package − 1.8 x 1.2 x 0.5 mm UDFN8 This is a Pb−Free Device LOGIC DIAGRAM VL EN VCC GND I/O VL1 I/O VCC1 I/O VL2 I/O VCC2 Typical Applications • I2C, SMBus, PMBus • Low Voltage ASIC Level Translation • Mobile Phones, PDAs, Cameras PIN ASSIGNMENT Important Information VL 1 8 VCC I/O VL1 2 7 I/O VCC1 I/O VL2 3 6 I/O VCC2 GND 4 5 EN • ESD Protection for Power, Enable and I/O Pins: Human Body Model (HBM): $7.5 kV Machine Model (MM): 400 V (Top View) ORDERING INFORMATION Device NLSX3373MUTAG Package Shipping† UDFN8 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 July, 2008 − Rev. 5 1 Publication Order Number: NLSX3373/D NLSX3373 VL VCC One−Shot Block PU1 One−Shot Block PU2 Gate Bias RPullup 10 kW RPullup 10 kW I/O VL I/O VCC N Figure 1. Block Diagram (1 I/O Line) PIN ASSIGNMENT Pins FUNCTION TABLE Description EN Operating Mode VCC VCC Input Voltage L Hi−Z VL VL Input Voltage H I/O Buses Connected GND Ground EN Output Enable I/O VCCn VCC I/O Port, Referenced to VCC I/O VLn VL I/O Port, Referenced to VL http://onsemi.com 2 NLSX3373 MAXIMUM RATINGS Symbol Parameter Value Condition Unit VCC High−side DC Supply Voltage −0.3 to +7.0 V VL High−side DC Supply Voltage −0.3 to +7.0 V I/O VCC VCC−Referenced DC Input/Output Voltage −0.3 to (VCC + 0.3) V I/O VL VL−Referenced DC Input/Output Voltage −0.3 to (VL + 0.3) V VEN Enable Control Pin DC Input Voltage −0.3 to +7.0 V II/O_SC Short−Circuit Duration (I/O VL and I/O VCC to GND) TSTG Storage Temperature 40 Continuous mA −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC High−side Positive DC Supply Voltage 1.65 4.5 V VL High−side Positive DC Supply Voltage 1.2 4.1 V VEN Enable Control Pin Voltage GND 4.5 V VIO Enable Control Pin Voltage GND 4.5 V TA Operating Temperature Range −40 +85 °C http://onsemi.com 3 NLSX3373 DC ELECTRICAL CHARACTERISTICS (VCC = 1.65 V to 4.5 V and VL = 1.2 V to 4.1 V, unless otherwise specified) −405C to +855C Symbol Parameter Test Conditions Min Typ (Notes 1, 2) Max Unit VCC − 0.4 − − V VIHC I/O VCC Input HIGH Voltage VILC I/O VCC Input LOW Voltage − − 0.15 V VIHL I/O VL Input HIGH Voltage VL − 0.2 − − V VILL I/O VL Input LOW Voltage − − 0.15 V VIH Control Pin Input HIGH Voltage VL − 0.2 − − V VIL Control Pin Input LOW Voltage − − 0.15 V VOHC I/O VCC Output HIGH Voltage I/O VCC Source Current = 20 mA 2/3 * VCC − − V VOLC I/O VCC Output LOW Voltage I/O VCC Sink Current = 20 mA − − 1/3 * VCC V VOHL I/O VL Output HIGH Voltage I/O VL Source Current = 20 mA 2/3 * VL − − V VOLL I/O VL Output LOW Voltage I/O VL Sink Current = 20 mA − − 1/3 * VL V IQVCC VCC Supply Current I/O VCC and I/O VL Unconnected, VEN = VL − 45 75 mA VL Supply Current I/O VCC and I/O VL Unconnected, VEN = VL − 1.0 5.0 mA VCC Tristate Output Mode Supply Current I/O VCC and I/O VL Unconnected, VEN = GND − 0.1 2.5 mA VL Tristate Output Mode Supply Current I/O VCC and I/O VL Unconnected, VEN = GND − 0.1 2.5 mA IQVL ITS−VCC ITS−VL IOZ I/O Tristate Output Mode Leakage Current TA = +25°C − − 2.5 mA RPU Pullup Resistor I/O VL and VCC TA = +25°C − 10 − kW 1. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. 2. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 4 NLSX3373 TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS (I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW) −405C to +855C (Notes 3 and 4) Symbol Parameter Test Conditions Min Typ Max Unit +1.2 v VL v VCC v +4.5 V tRVCC I/O VCC Risetime 25 ns tFVCC I/O VCC Falltime 37 ns tRVL I/O VL Risetime 30 ns tFVL I/O VL Falltime 30 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 30 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 30 ns Part−to−Part Skew 20 nS tPPSKEW Maximum Data Rate 8 Mb/s +1.2 v VL v VCC v +3.3 V tRVCC I/O VCC Risetime 25 ns tFVCC I/O VCC Falltime 30 ns tRVL I/O VL Risetime 30 ns tFVL I/O VL Falltime 30 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 20 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 20 ns Part−to−Part Skew 10 nS tPPSKEW Maximum Data Rate 10 Mb/s +1.8 v VL v VCC v +2.5 V tRVCC I/O VCC Risetime 15 ns tFVCC I/O VCC Falltime 15 ns tRVL I/O VL Risetime 15 ns tFVL I/O VL Falltime 15 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 15 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 15 ns Part−to−Part Skew 10 nS tPPSKEW Maximum Data Rate 16 Mb/s +2.5 v VL v VCC v +3.3 V tRVCC I/O VCC Risetime 15 ns tFVCC I/O VCC Falltime 15 ns tRVL I/O VL Risetime 15 ns tFVL I/O VL Falltime 15 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 15 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 15 ns Part−to−Part Skew 10 nS tPPSKEW Maximum Data Rate 20 3. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C. 4. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 5 Mb/s NLSX3373 TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS (I/O test circuit of Figures 4 and 5, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW) −405C to +855C (Notes 5 and 6) Symbol Parameter Test Conditions Min Typ Max Unit +1.2 v VL v VCC v +4.5 V tRVCC I/O VCC Risetime 400 ns tFVCC I/O VCC Falltime 50 ns tRVL I/O VL Risetime 400 ns tFVL I/O VL Falltime 60 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 1000 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 1000 ns 50 nS tPPSKEW MDR Part−to−Part Skew Maximum Data Rate 2 Mb/s 5. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C. 6. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 6 NLSX3373 TEST SETUPS NLSX3373 VL VCC NLSX3373 VL EN Source I/O VL I/O VCC I/O VL I/O VCC CLOAD CLOAD RLOAD NLSX3373 Figure 3. Rail−to−Rail Driving I/O VCC I/O VCC I/O VL CLOAD I/O VCC VCC CLOAD RLOAD Figure 4. Open−Drain Driving I/O VL Figure 5. Open−Drain Driving I/O VCC tRISE/FALL v 3 ns tPD_VL−VCC I/O VCC VCC EN RLOAD I/O VL NLSX3373 VL VCC EN 90% 50% 10% Source RLOAD Figure 2. Rail−to−Rail Driving I/O VL VL VCC EN I/O VCC tRISE/FALL v 3 ns 90% 50% 10% tPD_VCC−VL I/O VL tPD_VL−VCC 90% 50% 10% tPD_VCC−VL 90% 50% 10% tF−VCC tR−VCC tF−VL Figure 6. Definition of Timing Specification Parameters http://onsemi.com 7 tR−VL NLSX3373 VCC PULSE GENERATOR 2xVCC OPEN R1 DUT RT CL Test RL Switch tPZH, tPHZ Open tPZL, tPLZ 2 x VCC CL = 15 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 50 kW or equivalent RT = ZOUT of pulse generator (typically 50 W) Figure 7. Test Circuit for Enable/Disable Time Measurement tR tF Input tPLH Output 90% 50% 10% tR EN VCC 90% 50% 10% tPHL GND VL 50% tPZL Output 50% tPZH tF Output 50% GND tPLZ tPHZ HIGH IMPEDANCE 10% VOL 90% VOH Figure 8. Timing Definitions for Propagation Delays and Enable/Disable Measurement http://onsemi.com 8 HIGH IMPEDANCE NLSX3373 APPLICATIONS INFORMATION Level Translator Architecture Enable Input (EN) The NLSX3373 auto sense translator provides bi−directional voltage level shifting to transfer data in multiple supply voltage systems. This device has two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the VL to the VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the VCC to VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX3373 consists of two bi−directional channels that independently determine the direction of the data flow without requiring a directional pin. The one−shot circuits are used to detect the rising or falling input signals. In addition, the one shots decrease the rise and fall time of the output signal for high−to−low and low−to−high transitions. Each input/output channel has an internal 10 kW pull. The magnitude of the pullup resistors can be reduced by connecting external resistors in parallel to the internal 10 kW resistors. The NLSX3373 has an Enable pin (EN) that provides tri−state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O VCC and I/O VL pins to a high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Overvoltage Tolerant (OVT) protection. Power Supply Guidelines During normal operation, supply voltage VL should be less than or equal to VCC. The sequencing of the power supplies will not damage the device during the power up operation. The enable pin should be used to enter the low current tri−state mode, rather than setting either the VL or VCC supplies to 0 V. The NLSX3373 will not be damaged if either VL or VCC is equal to 0 V while the other supply voltage is at a nominal operating value; however, the operation of the translator cannot be guaranteed during single supply operation. For optimal performance, 0.01 mF to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces. Input Driver Requirements The rise (tR) and fall (tF) timing parameters of the open drain outputs depend on the magnitude of the pull−up resistors. In addition, the propagation times (tPD), skew (tPSKEW) and maximum data rate depend on the impedance of the device that is connected to the translator. The timing parameters listed in the data sheet assume that the output impedance of the drivers connected to the translator is less than 50 kW. http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN8 1.8x1.2, 0.4P CASE 517AJ−01 ISSUE O 8 1 DATE 08 NOV 2006 SCALE 4:1 A B D ÉÉ ÉÉ 0.10 C PIN ONE REFERENCE 0.10 C L1 E DETAIL A NOTE 5 TOP VIEW (A3) 0.05 C DIM A A1 A3 b b2 D E e L L1 L2 A 0.05 C SIDE VIEW e/2 (b2) A1 e 1 4 8 5 C SEATING PLANE DETAIL A 8X L 8X b 0.10 M C A B 0.05 M C NOTE 3 MOUNTING FOOTPRINT SOLDERMASK DEFINED 8X 0.66 7X 0.22 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 0.30 REF 1.80 BSC 1.20 BSC 0.40 BSC 0.45 0.55 0.00 0.03 0.40 REF GENERIC MARKING DIAGRAM* (L2) BOTTOM VIEW NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. 4. MOLD FLASH ALLOWED ON TERMINALS ALONG EDGE OF PACKAGE. FLASH MAY NOT EXCEED 0.03 ONTO BOTTOM SURFACE OF TERMINALS. 5. DETAIL A SHOWS OPTIONAL CONSTRUCTION FOR TERMINALS. XXM G XX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 1.50 1 0.32 0.40 PITCH DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98AON23417D UDFN8 1.8X1.2, 0.4P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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