NM93C86A
16K-Bit Serial EEPROM
(MICROWIRE™ Bus Interface)
General Description
Features
The NM93C86A is 16,384 bits of CMOS nonvolatile, electrically
erasable memory available in user organized as either 1024 16bit registers or 2048 8-bit registers. The user organization is
determined by the status of the ORG input. The memory device is
fabricated using Fairchild Semiconductor’s floating gate CMOS
process for high reliability, high endurance and low power consumption. The NM93C86A is available in 8-pin SO and TSSOP
packages for space considerations.
■ 2.7V to 5.5V operation in all modes
■ Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
■ Device status indication during programming mode
■ No erase required before write
■ Reliable CMOS floating gate technology
The EEPROM is MICROWIRE™ compatible for simple interfacing to a wide variety of microcontrollers and microprocessors.
There are 7 instructions that operate the NM93C86A: Read,
Erase/Write Enable, Erase, Write, Erase/Write Disable, Write All,
and Erase All.
■ MICROWIRE™ compatible serial I/O
■ Self-timed programming cycle
■ 40 years data retention
■ Endurance: 1,000,000 data changes
The NM93C86A defaults to the 1024 x 16 configuration if the ORG
pin (Pin 6) is left floating, as it is internally pulled up to VCC.
■ Packages available: 8-pin SO, 8-pin DIP
Block Diagram
CS
VCC
Instruction
Decoder
Control Logic,
And Clock
Generators
SK
Instruction
Register
DI
ORG
Address
Register
VPP
High Voltage
Generator
And
Program
Timer
EEPROM Array
16384 Bits
(1024x16) or (2048x8)
Decoder
1 of 1024
(or 2048)
Read/Write Amps
Data In/Out Register
16 (or 8) Bits
GND
Data Out Buffer
DO
© 1999 Fairchild Semiconductor Corporation
NM93C86A Rev. E.2
DS011254-12
1
www.fairchildsemi.com
NM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
March 1999
Dual-In-Line Package (N)
and 8-Pin SO Package (M8)
CS
1
SK
2
DI
DO
8
VCC
7
NC
3
6
ORG
4
5
VSS
NM93C86A
Top View
See Package Number
N08E and M08A
DS011254-14
Pin Names
Pin
Description
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
VSS
Ground
ORG
Memory Organization Select
NC
No Connect
VCC
Positive Power Supply
Ordering Information
NM
93
C
XX
A
LZ
E
XX
Letter Description
Package
N
M8
8-Pin DIP
8-Pin SO8
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 4.5V
2.7V to 4.5V and
1 µA when in the x8 mode ude to an internal pull-up transistor.
Note 4: The shortest allowable SK clock period = 1/fSK (as shown under the fSK fSK parameter).
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed.
Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 5: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in
the opcode diagrams in the following pages.)
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
VIL/VIH
Timing Level
VOL/VOH
Timing Level
IOL/IOH
2.7V ≤ VCC ≤ 5.5V
.03V/1.8V
1.0V
0.8V/1.5V
±10µA
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
-2.1mA/0.4mA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
NM93C86A Rev. E.2
www.fairchildsemi.com
NM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings (Note 1)
Serial Clock (SK):
Chip Select (CS):
This pin is the clock input (rising edge active) for clocking in all
opcodes and data on the DI pin and clocking out all data on the DO
pin. However, this pin has no effect on the asynchronous programming cycle (see the CD pin section) as the BUSY/READY status
is a function of the CD pin only.
This pin enables and disables the MICROWIRE device and
performs 2 general functions:
1. When in the low state, the MICROWIRE device is disabled
and the output tri-stated (high impedance). If this pin is
brought high (rising edge active), all internal registers are
reset and the device is enabled, allowing MICROWIRE
communication via DI/DO pins. To restate, the CS pin must
be held high during all device communication and opcode
functions. If the CS pin is brought low, all functions will be
disabled and reset when CS is brought high again. The
exception to this is when a programming cycle is initiated.
Again, all activity on the CS, DI and DO pins is ignored until
CS is brought high.
Data-In (DI):
All serial communication into the device is performed using this
input pin (rising edge active). In order to avoid false Start Bits, or
related issues, it is advised to keep the DI pin in the low state
unless actually clocking in data bits (Start Bit, Opcode, Address or
incoming data bits to be programmed). Please note that the first
'1' clocked into the device (after CS is brought high) is seen as a
Start Bit and the beginning of a serial command string, so caution
must be observed when bringing CS high.
2. When programming is in progress, the Data-Out pin will
display the programming status as either BUSY (DO low) or
READY (DO high) when CS is brought high. (Again, the
output will be tri-stated when CS is low.) To restate, during
programming, the CS pin may be brought high and low any
number of times to view the programming status without
affect the programming operation. Once programming is
completed (Output in READY state), the output is 'cleared'
(returned to normal tri-state condition) by clocking in a Start
Bit. After the Start Bit is clocked in, the output will return to a
tri-stated condition. When clocked in, this Start Bit can be the
first bit in a command string, or CS can be brought low again
to reset all internal circuits.
Data-Out (DO):
All serial communication out of the device (READ opcode) is
performed using this output pin (rising edge active) as well as
indicating the READY/BUSY status duting the asynchronous
programming cycle. Note that, during READ operations, the
output data is clocked out after the last address bit (A0) is clocked
in. If a 3-wire application is required (where DI and DO are tied
together), sections in AN-758, or related application notes, must
be followed for correct operation.
Organization (ORG):
This pin controls the device architecture (8-bit data word vs. 16-bit
data word). If the ORG pin is brought to VCC, the device is
configured with a 16-bit data word and if the ORG pin is brought
to VSS (Ground), the device is configured with an 8-bit data word
(refer to other sections for details of both configurations). If the
ORG pin is left floating, the device will default to a 16-bit data word.
Unlike the lower density members of the Microwire product
family (NM93C06, NM93C46, NM93C56, NM93C66)
programming is not initiated by bringing CS low.
Instruction Set for the NM93C86A
ORG
Memory
Pin
Logic
Configuration
# of Address Bits
0
2048 x 8
11 Bits
1
1024 x 16
10 Bits
5
NM93C86A Rev. E.2
www.fairchildsemi.com
NM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
MICROWIRE I/O Pin Description
Instruction
SB
Op Code
2 Bits
Address
10 Bits
Data
16 Bits
Function
READ
1
10
A9–A0
Read data stored in selected registers.
EWEN
1
00
11XXXXXXXX
Enables programming modes.
EWDS
1
00
00XXXXXXXX
Disables all programming modes.
ERASE
1
11
A9–A0
WRITE
1
01
A9–A0
ERAL
1
00
10XXXXXXXX
WRAL
1
00
01XXXXXXXX
Erases selected register.
D15–D0
Writes data pattern D15–D0 into selected register.
Erases all registers.
D15–D0
Writes data pattern D15–D0 into all registers.
2048 by 8-Bit Organization (NM93C86A when ORG = GND)
Instruction
SB
Op Code
2 Bits
Address
11 Bits
Data
8 Bits
READ
1
10
A10–A0
Read data stored in selected registers.
EWEN
1
00
11XXXXXXXXX
Enables programming modes.
EWDS
1
00
00XXXXXXXXX
Disables all programming modes.
ERASE
1
11
A10–A0
Erases selected register.
WRITE
1
01
A10–A0
ERAL
1
00
10XXXXXXXXX
WRAL
1
00
01XXXXXXXXX
D7–D0
The programming cycle is automatically started after entering the
LAST bit of the programming instruction string (unlike other
Microwire family members which use CS to initiate programming).
This feature, counting the number of instruction bits, decreases
the likelihood of inadvertent programming and allows the programming to be cancelled before sending out the last bit in the
string (be bringing CS low).
WRITE
D0
WRAL
D0
ERASE
A0
ERAL
A0
Read (READ)
The READ instruction outputs serial data on the DO pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a serial-out shift register. A dummy bit (logical 0)
precedes the serial data output string. Output data changes are
initiated by a low to high transition of SK clock after the last address
bit (A0) is clocked in.
Erase/Write Enable (EWEN)
When VCC is applied to the part, it “powers up” in the Erase/Write
Disable (EWDS) state. Therefore, all programming modes must
be preceded by an Erase/Write Enable (EWEN) instruction. Once
an Erase/Write Enable instruction is executed, programming
remains enabled until an Erase/Write Disable (EWDS) instruction
is executed or VCC is removed from the part.
Note that, in the ERASE/ERAL instructions, the A0 bit is the last
bit in the string and clocking in that bit will initiate programming. In
order to maintain compatibility, CS may be brought low after
clocking in the last bit, but it is not necessary.
In all programming modes the READY/BUSY status of the device
can be determined by polling the DO pin. After clocking in the last
bit of the instruction sequence and with the CS held “high”, the DO
pin will exit the high impedance state and indicate the READY/
BUSY status of the device. DO = logical “0” indicates that programming is still in progress and no other instruction can be executed.
6
NM93C86A Rev. E.2
Writes data pattern D7–D0 into all registers.
DO = logical “1” indicates that the device is READY for another
instruction. If CS is forced “low” the DO pin will return to the high
impedance state. After the programming cycle has been completed and DO = logical “1”, the DO pin can be reset back to the
high impedance state by clocking a logical “1” into the DI pin. (This
is also performed with the start bit on all op codes, thus clocking
an instruction has the same effect.)
Programming
Last Bit in String
Writes data pattern D7–D0 into selected register.
Erases all registers.
D7–D0
Functional Description
Programming Instruction
Function
www.fairchildsemi.com
NM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
1024 by 16-Bit Organization (NM93C86A when ORG = VCC or NC)
instruction will be aborted. The self-timed programming cycle is
initiated on the rising edge of the SK clock as the last data bit (D0)
is clocked in. At this point, CS, SK and DI become don’t care
states. No separate ERASE cycle is required before a WRITE
instruction.
Erase/Write Disable (EWDS)
To protect against accidental data overwrites, the Erase/Write
Disable (EWDS) instruction disables all programming modes and
should follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS instructions.
As in the ERASE instruction, after starting a WRITE cycle, the DO
pin indicates the READY/BUSY status of the chip if CS is held
“high”. DO = logical “0” indicates that programming is still in
progress. DO = logical “1” indicates that the register, at the
address specified in the instruction, has been written and that the
part is ready for another instruction.
Erase (ERASE)
The ERASE instruction will program all bits in the specified
register to the logical “1” state. The self-timed programming cycle
is initiated on the rising edge of the SK clock as the last address
bit (A0) is clocked in. At this point CS, SK and DI become don’t care
states. After starting an Erase cycle the DO pin indicates the
READY/BUSY status of the chip if CS is held “high”. DO = logical
“0” indicates that programming is still in progress. DO = logical “1”
indicates that the register, at the address specified in the instruction, has been erased.
Erase All (ERAL)
The ERAL instruction will simultaneously program all registers in
the memory array to the logical “1” state.
Write All (WRAL)
The WRAL instruction will simultaneously program all registers
with the data pattern specified in the instruction.
Write (WRITE)
The WRITE instruction is followed by 16 bits of data (or 8 bits of
data when using the NM93C86A in the x8 organization) to be
written into the specified address. Note that if the CS is brought
“low” before clocking in all of the data bits, then the WRITE
Timing Diagrams for the NM93C86A
Synchronous Data Timing
CS
SK
DI
VIH
VIL
VIH
VIL
VIH
tCSS
tSKS
tDIS
VIL
VOH
DO (READ)
VOL
VOH
DO (PROGRAM)
VOL
tSKH
tSKL
tDIH
tPD0
tSV
tDH
tDH
tPD1
tDF
tDF
STATUS VALID
7
NM93C86A Rev. E.2
tCSH
DS011254-3
www.fairchildsemi.com
NM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Functional Description (Continued)
ORG
Organization
AN
DN
VCC or NC
1024 x 16
A9
D15
VSS
2048 x 8
A10
D7
READ
CS
tCS
SK
1
DI
1
0
...
AN
A0
DO
0
...
DN
D0
DS011254-4
EWEN
DO = TRI-STATE
tcs
CS
SK
DI
1
0
0
1
1
...
X
X
ORG = VCC, 8 X's
ORG = VSS, 9 X's
DS011254-5
EWDS
DO = TRI-STATE
tcs
CS
SK
DI
1
0
0
0
0
...
X
X
ORG = VCC, 8 X's
ORG = VSS, 9 X's
DS011254-6
ERASE
CS
SK
DI
1
1
1
AN
...
A0
DO
BUSY
tWP
8
NM93C86A Rev. E.2
READY
READY STATUS SIGNAL RESETS
TO TRI-STATE AFTER CLOCKING
IN ONE SK CYCLE WITH DI = 1
DS011254-7
www.fairchildsemi.com
NM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams for the NM93C86A (Continued)
Key for Timing Diagrams
Organization of Address and Data Fields for the NM93C86A
WRITE
CS
SK
1
DI
0
1
AN
...
A0
DN
...
D0
DO
BUSY
READY
tWP
READY STATUS SIGNAL RESETS
TO TRI-STATE AFTER CLOCKING
IN ONE SK CYCLE WITH DI = 1
DS011254-8
ERAL
CS
SK
1
DI
0
0
1
0
X
...
X
ORG = VCC, 8 X's
ORG = VSS, 9 X's
DO
BUSY
tWP
READY
READY STATUS SIGNAL RESETS
TO TRI-STATE AFTER CLOCKING
IN ONE SK CYCLE WITH DI = 1
DS011254-9
WRAL
CS
SK
DI
DO
1
0
0
0
1
X
...
X
DN
ORG = VCC, 8 X's
ORG = VSS, 9 X's
...
D0
BUSY
tWP
READY
READY STATUS SIGNAL RESETS
TO TRI-STATE AFTER CLOCKING
IN ONE SK CYCLE WITH DI = 1
DS011254-10
9
NM93C86A Rev. E.2
www.fairchildsemi.com
NM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Timing Diagrams for the NM93C86A (Continued)
0.189 - 0.197
(4.800 - 5.004)
8 7
6 5
0.228 - 0.244
(5.791 - 6.198)
0.010
Max.
(0.254)
1 2
3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.008 - 0.010
(0.203 - 0.254)
Typ. all leads
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
30° Typ.
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.008
Typ
(0.203)
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Small Outline Package (M8)
Package Number M08A
10
NM93C86A Rev. E.2
www.fairchildsemi.com
NM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Physical Dimensions inches (millimeters) unless otherwise noted
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
8
Pin #1
IDENT
1
Option 1
1
0.280 MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
7
2
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
3
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-in-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
11
NM93C86A Rev. E.2
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
www.fairchildsemi.com
NM93C86A 16K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
0.373 - 0.400
(9.474 - 10.16)