NTB90N02T4

NTB90N02, NTP90N02 Power MOSFET 90 Amps, 24 Volts N−Channel D2PAK and TO−220 Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. Features V(BR)DSS http://onsemi.com RDS(on) TYP 5.0 mW @ 10 V 7.5 mW @ 4.5 V N−Channel D ID MAX • Pb−Free Packages are Available Typical Applications 24 V 90 A • • • • Power Supplies Converters Power Motor Controls Bridge Circuits G Unit Vdc Vdc 4 A A W W/°C °C mJ 1 2 3 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Gate−to−Source Voltage − Continuous Drain Current − Continuous @ TA = 25°C − Single Pulse (tp = 10 ms) Total Power Dissipation @ TA = 25°C Derate above 25°C Operating and Storage Temperature Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 28 Vdc, VGS = 10 Vdc, L = 5.0 mH, IL(pk) = 17 A, RG = 25 W) Thermal Resistance Junction−to−Case Junction−to−Ambient (Note 1) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg EAS Value 24 "20 90* 200 85 0.66 −55 to +150 733 S MARKING DIAGRAMS 4 Drain TO−220AB CASE 221A STYLE 5 NTx90N02 AYWW 1 Gate 2 Drain 4 Drain 3 Source °C/W RqJC RqJA TL 1.55 70 260 °C 4 1 2 3 1 Gate NTx90N02 x A Y WW = Device Code = P or B = Assembly Location = Year = Work Week D2PAK CASE 418B STYLE 2 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2). *Chip current capability limited by package. NTx90N02 AYWW 2 Drain 3 Source ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2005 1 March, 2005 − Rev. 2 Publication Order Number: NTB90N02/D NTB90N02, NTP90N02 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 150°C) Gate−Body Leakage Current (VGS = $ 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain−to−Source On−Resistance (Note 3) (VGS = 10 Vdc, ID = 90 Adc) (VGS = 4.5 Vdc, ID = 40 Adc) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 4.5 Vdc, ID = 20 Adc) Forward Transconductance (Note 3) (VDS = 15 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDS = 20 Vdc, ID = 20 Adc, VGS = 4.5 Vdc) (Note 3) 5 (VDD = 20 Vdc, ID = 20 Adc, VGS = 4.5 Vdc RG = 2.5 W) 5 Vdc, 5 td(on) tr td(off) tf QT Q1 Q2 SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 2.3 Adc, VGS = 0 Vdc) (IS = 40 Adc, VGS = 0 Vdc) (Note 3) (IS = 2.3 Adc, VGS = 0 Vdc, TJ = 150°C) (IS = 2.3 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3) VSD − − − − − − − 0.75 1.2 0.65 40 21 18 0.036 1.0 − − − − − − mC Vdc − − − − − − − 16 90 28 60 29 8.0 20 − − − − − − − nC ns (VDS = 20 Vdc, VGS = 0 Vdc, f = 1 0 MHz) 1.0 Ciss Coss Crss − − − 2120 900 360 − − − pF VGS(th) 1.0 − RDS(on) − − − − gFS − 5.0 7.5 5.0 7.5 25 5.8 9.0 5.8 9.0 − mhos 1.9 −3.8 3.0 − Vdc mV/°C mW V(BR)DSS 24 − IDSS − − IGSS − − − − 1.0 10 ±100 nAdc 27 25 − − Vdc mV/°C mAdc Symbol Min Typ Max Unit Reverse Recovery Time trr ta tb ns Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. QRR http://onsemi.com 2 NTB90N02, NTP90N02 100 90 ID, DRAIN CURRENT (AMPS) 80 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 3.4 V 3.2 V VGS = 3.0 V 6.5 V 9V 8V 4.4 V 4.6 V 4.8 V 5V 5.2 V 6V TJ = 25°C 4.2 V 4V 3.8 V 3.6 V 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 VDS ≥ 24 V ID, DRAIN CURRENT (AMPS) TJ = 25°C TJ = 125°C TJ = −55°C 2 3 4 5 6 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 2 4 6 8 10 VGS, GATE−TO−SOURCE VOLTAGE (V) ID = 10 A TJ = 25°C RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.015 TJ = 25°C 0.01 VGS = 4.5 V VGS = 10 V 0.005 0 55 60 65 70 75 80 85 90 ID, DRAIN CURRENT (A) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) Figure 3. On−Resistance versus Gate−To−Source Voltage 0.015 0.0125 0.001 0.0075 0.005 0.0025 0 −50 ID = 10 A VDS = 10 V ID = 90 A VDS = 4.5 V IDSS, LEAKAGE (nA) Figure 4. On−Resistance versus Drain Current and Gate Voltage 1000 VGS = 0 V 100 TJ = 125°C TJ = 100°C 10 1 TJ = 25°C 0.1 −25 0 25 50 75 100 125 150 0.01 4 8 12 16 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 NTB90N02, NTP90N02 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 5000 VGS, GATE−TO−SOURCE VOLTAGE (V) VGS = 0 V TJ = 25°C 10 28 8 VD Q1 Q2 QT VGS 24 20 16 4 12 8 2 ID = 1.0 A TJ = 25°C 0 0 10 20 30 40 50 4 0 C, CAPACITANCE (pF) 4000 3000 Ciss 2000 Coss 1000 0 −8 −6 −4 −2 0 2 4 VGS VDS Crss 6 6 8 10 12 14 16 18 20 22 24 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 1000 IS, SOURCE CURRENT (AMPS) VDD = 20 V ID = 20 A VGS = 10 V t, TIME (ns) 100 tr tf td(off) td(on) 90 80 70 60 50 40 30 20 10 0 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 VSD, SOURCE−TO−DRAIN VOLTAGE (V) VGS = 0 V TJ = 25°C 10 1 1 10 RG, GATE RESISTANCE (W) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current ORDERING INFORMATION Device NTP90N02 NTP90N02G NTB90N02 NTB90N02G NTB90N02T4 NTB90N02T4G Package TO−220AB TO−220AB (Pb−Free) D2PAK D2PAK (Pb−Free) D2PAK D2PAK (Pb−Free) Shipping† 50 Units / Rail 50 Units / Rail 50 Units / Rail 50 Units / Rail 800 Tape & Reel 800 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 NTB90N02, NTP90N02 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t + Q IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr + Q2 tf + Q2 R2 10(VGG * VGSP) R2 VGSP where: VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) + RG Ciss In [VGG (VGG * VGSP)] td(off) + RG Ciss In (VGG VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. http://onsemi.com 5 NTB90N02, NTP90N02 PACKAGE DIMENSIONS D2PAK CASE 418AA−01 ISSUE O −B− 4 C E V W NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.036 0.045 0.055 0.310 −−− 0.100 BSC 0.018 0.025 0.090 0.110 0.280 −−− 0.575 0.625 0.045 0.055 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.92 1.14 1.40 7.87 −−− 2.54 BSC 0.46 0.64 2.29 2.79 7.11 −−− 14.60 15.88 1.14 1.40 1 2 3 S A −T− SEATING PLANE G K D 3 PL M W J 0.13 (0.005) VARIABLE CONFIGURATION ZONE TB M DIM A B C D E F G J K M S V STYLE 2: PIN 1. 2. 3. 4. U M M M F VIEW W−W 1 F VIEW W−W 2 F VIEW W−W 3 SOLDERING FOOTPRINT* 8.38 0.33 10.66 0.42 1.016 0.04 5.08 0.20 3.05 0.12 17.02 0.67 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 NTB90N02, NTP90N02 PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 B 4 F C T A S −T− SEATING PLANE Q 123 H K Z L V G D N U R J STYLE 5: PIN 1. 2. 3. 4. http://onsemi.com 7 NTB90N02, NTP90N02 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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