NTB65N02RT4G

NTB65N02R, NTP65N02R Power MOSFET 65 A, 24 V N−Channel TO−220, D2PAK Features • • • • • http://onsemi.com V(BR)DSS 24 V RDS(on) TYP 8.4 mW @ 10 V ID MAX 65 A Planar HD3e Process for Fast Switching Performance Low RDSon to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge Pb−Free Packages are Available* D MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified) Parameter Drain−to−Source Voltage Gate−to−Source Voltage − Continuous Thermal Resistance − Junction−to−Case Total Power Dissipation @ TC = 25°C Drain Current − Continuous @ TC = 25°C, Chip Continuous @ TC =25°C, Limited by Package Single Pulse (tp = 10 ms) Thermal Resistance − Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C Thermal Resistance − Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10 Vdc, IL = 11 Apk, L = 1 mH, RG = 25 W) Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 Seconds Symbol VDSS VGS RqJC PD ID ID IDM RqJA PD ID RqJA PD ID TJ and Tstg EAS Value 25 ±20 2.0 62.5 65 58 160 67 1.86 10 120 1.04 7.6 −55 to 150 60 Unit Vdc Vdc °C/W W A A A °C/W W A 1 °C/W W A °C mJ 2 13 2 3 G S MARKING DIAGRAMS 4 TO−220AB CASE 221A STYLE 5 P65N02RG AYWW 4 D2PAK CASE 418AA STYLE 2 65N02RG AYWW TL 260 °C 65N02R = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1 in. pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2). PIN ASSIGNMENT PIN 1 2 3 4 FUNCTION Gate Drain Source Drain *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. 1 May, 2005 − Rev. 6 Publication Order Number: NTB65N02R/D NTB65N02R, NTP65N02R ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified) Characteristics OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C) Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain−to−Source On−Resistance (Note 3) (VGS = 4.5 Vdc, ID = 15 Adc) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 30 Adc) Forward Transconductance (Note 3) (VDS = 10 Vdc, ID = 15 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 30 Adc, VDS = 10 Vdc) (Note 3) dc SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3) dc dc (Note 3) ( (IS = 30 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 125°C) 15 125 VSD SD − − − − − − − 0.88 0.88 1.10 0.80 0 80 29.1 13.6 15.5 0.02 1.2 1.2 − − − − − − mC Vdc dc (VGS = 10 Vdc, VDD = 10 Vdc, dc dc ID = 30 Adc, RG = 3 W) td(on) tr td(off) tf QT Q1 Q2 − − − − − − − 7.0 53 14 10 9.5 3.0 4.4 − − − − − − − nC ns ( (VDS = 20 Vdc, VGS = 0 V, f = 1 MHz) ) Ciss Coss Crss − − − 948 456 160 1330 640 225 pF VGS(th) 1.0 − RDS(on) − − − gFS − 27 − 11.2 8.4 8.2 12.5 10.5 − Mhos 1.5 4.1 2.0 − Vdc mV/°C mW V(BR)DSS 24 − IDSS − − IGSS − − − − 1.5 10 ±100 nAdc 27.5 25.5 − − Vdc mV/°C mAdc Symbol Min Typ Max Unit Reverse Recovery Time (IS = 30 Ad , VGS = 0 Vd , 30 dc dc dIS/dt = 100 A/ms) (Note 3) )( ) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. trr ta tb QRR ns http://onsemi.com 2 NTB65N02R, NTP65N02R 120 100 80 60 40 VGS = 3.0 V 20 0 0 2 4 6 VGS = 2.5 V 8 10 VGS = 10 V ID, DRAIN CURRENT (A) VGS = 8.0 V VGS = 6.0 V VGS = 5.5 V VGS = 5.0 V VGS = 3.5 V VGS = 4.5 V 120 VDS w 10 V 100 80 60 40 TJ = 25°C 20 0 0 1 2 3 5 6 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ = 150°C TJ = −55°C ID, DRAIN CURRENT (A) VGS = 4.0 V VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.028 VGS = 10 V 0.024 0.02 0.016 0.012 0.008 0.004 10 20 30 40 50 60 70 80 90 100 110 120 ID, DRAIN CURRENT (A) TJ = 150°C TJ = 125°C TJ = −55°C RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.028 VGS = 4.5 V 0.024 0.02 0.016 TJ = 25°C 0.012 0.008 0.004 10 TJ = −55°C TJ = 150°C TJ = 125°C TJ = 25°C 20 30 40 50 60 70 80 90 100 110 120 ID, DRAIN CURRENT (A) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Temperature RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 −50 ID = 30 A VGS = 4.5 V and 10 V 10000 TJ = 150°C IDSS, LEAKAGE (nA) 1000 TJ = 125°C 100 TJ = 100°C 10 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 NTB65N02R, NTP65N02R TJ = 25°C VGS, GATE−TO−SOURCE VOLTAGE (V) 2000 Ciss 1600 C, CAPACITANCE (pF) VDS = 0 V VGS = 0 V 5 QT 4 VDS QGS 3 QGD VGS 8 6 2 4 1 ID = 30 A TJ = 25°C 0 2 4 6 8 10 12 2 0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 10 1200 Ciss 800 Crss Coss 400 Crss 0 10 5 VGS 0 VDS 5 10 15 20 0 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 1000 IS, SOURCE CURRENT (A) VDS = 10 V ID = 30 A VGS = 10 V t, TIME (ns) 100 tr td(off) 10 tf td(on) 60 50 40 30 20 TJ = 150°C 10 0 TJ = 25°C 1 1 10 RG, GATE RESISTANCE (W) 100 0 0.2 0.4 0.6 0.8 1 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 1000 VGS = 20 V SINGLE PULSE TC = 25°C ID, DRAIN CURRENT (A) 100 10 ms 100 ms 10 RDS(ON) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 1 ms 10 ms dc 100 1 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 NTB65N02R, NTP65N02R r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1 D = 0.5 0.2 0.1 0.05 0.01 SINGLE PULSE 0.1 0.0001 0.001 0.01 t, TIME (s) 0.1 1 10 Figure 12. Thermal Response ORDERING INFORMATION Device NTB65N02R NTB65N02RG NTB65N02RT4 NTB65N02RT4G NTP65N02R NTP65N02RG Package D2PAK D2PAK (Pb−Free) D2PAK D2PAK (Pb−Free) TO−220AB TO−220AB (Pb−Free) 50 Units / Rail 50 Units / Rail 800 / Tape & Reel 800 / Tape & Reel Shipping† 50 Units / Rail 50 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTB65N02R, NTP65N02R PACKAGE DIMENSIONS TO−220AB CASE 221A−09 ISSUE AA −T− B 4 SEATING PLANE F T S C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 Q 123 A U K H Z L V G D N R J STYLE 5: PIN 1. 2. 3. 4. http://onsemi.com 6 NTB65N02R, NTP65N02R PACKAGE DIMENSIONS D2PAK CASE 418AA−01 ISSUE O C E −B− 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.036 0.045 0.055 0.310 −−− 0.100 BSC 0.018 0.025 0.090 0.110 0.280 −−− 0.575 0.625 0.045 0.055 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.92 1.14 1.40 7.87 −−− 2.54 BSC 0.46 0.64 2.29 2.79 7.11 −−− 14.60 15.88 1.14 1.40 V W A 1 2 3 S −T− SEATING PLANE K G D 3 PL 0.13 (0.005) J W DIM A B C D E F G J K M S V M TB M VARIABLE CONFIGURATION ZONE U STYLE 2: PIN 1. 2. 3. 4. M M M F VIEW W−W 1 F VIEW W−W 2 F VIEW W−W 3 SOLDERING FOOTPRINT* 8.38 0.33 10.66 0.42 1.016 0.04 5.08 0.20 3.05 0.12 17.02 0.67 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 NTB65N02R, NTP65N02R ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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