NTD6415ANT4G

NTD6415AN N-Channel Power MOSFET 100 V, 23 A, 55 mW Features • • • • Low RDS(on) High Current Capability 100% Avalanche Tested These Devices are Pb−Free and are RoHS Compliant V(BR)DSS Value 100 $20 23 16 PD IDM TJ, Tstg IS EAS 83 89 −55 to +175 23 79 W A °C G Unit V V A 100 V http://onsemi.com ID MAX (Note 1) 23 A MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage − Continuous Continuous Drain Current RqJC Power Dissipation RqJC Pulsed Drain Current Steady State Steady State TC = 25°C TC = 100°C TC = 25°C Symbol VDSS VGS ID RDS(on) MAX 55 mW @ 10 V N−Channel D tp = 10 ms Operating and Storage Temperature Range Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (VDD = 50 Vdc, VGS = 10 Vdc, IL(pk) = 23 A, L = 0.3 mH, RG = 25 W) Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 Seconds S A mJ 4 4 TL 260 °C THERMAL RESISTANCE RATINGS Parameter Junction−to−Case (Drain) Steady State Junction−to−Ambient (Note 1) Symbol RqJC RqJA Max 1.8 39 Unit °C/W 3 DPAK CASE 369AA STYLE 2 12 1 3 IPAK CASE 369D STYLE 2 2 YWW 64 15ANG 1 Gate 2 Drain 3 Source YWW 64 15ANG 1 Gate 2 Drain 3 Source Publication Order Number: NTD6415AN/D Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface mounted on FR4 board using 1 sq in pad size, (Cu Area 1.127 sq in [2 oz] including traces). MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain 4 Drain 6415AN Y WW G = Device Code = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2009 November, 2009 − Rev. 0 1 NTD6415AN ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On−Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Plateau Voltage Gate Resistance SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge td(on) tr td(off) tf VSD tRR Ta Tb QRR VGS = 0 V, dIS/dt = 100 A/ms, IS = 23 A TJ = 25°C TJ = 125°C VGS = 10 V, VDD = 80 V, ID = 23 A, RG = 6.1 W 10 37 30 37 0.83 0.68 65 46 19 176 nC ns 1.2 V ns VGS(TH) VGS(TH)/TJ RDS(on) gFS CISS COSS CRSS QG(TOT) QG(TH) QGS QGD VGP RG VGS = 10 V, VDS = 80 V, ID = 23 A VGS = 0 V, f = 1.0 MHz, VDS = 25 V VGS = 10 V, ID = 23 A VGS = 5 V, ID = 10 A VGS = VDS, ID = 250 mA 2.0 7.6 47 13 700 110 52 29 1.2 5 14.6 5.7 2.3 V W nC 55 4.0 V mV/°C mW S pF V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS = 0 V, VDS = 100 V TJ = 25°C TJ = 125°C VGS = 0 V, ID = 250 mA 100 113 1.0 100 "100 nA V mV/°C mA Symbol Test Condition Min Typ Max Unit VDS = 0 V, VGS = "20 V CHARGES, CAPACITANCES AND GATE RESISTANCE DRAIN−SOURCE DIODE CHARACTERISTICS VGS = 0 V, IS = 23 A 2. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. ORDERING INFORMATION Device NTD6415ANT4G NTD6415AN−1G Package DPAK (Pb−Free) IPAK (Pb−Free) Shipping† 2500 / Tape & Reel 75 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 2 NTD6415AN 40 40 TJ = 25°C 10 V 6.5 V 7.5 V ID, DRAIN CURRENT (A) 6.0 V 30 VDS w 10 V ID, DRAIN CURRENT (A) 30 20 5.5 V 20 TJ = 125°C 10 TJ = 25°C TJ = −55°C 10 5.0 V 4.5 V 0 0 1 2 3 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 5 0 2 3 4 5 6 7 VGS, GATE−TO−SOURCE VOLTAGE (V) 8 Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.11 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 5 6 7 8 9 ID = 23 A TJ = 25°C RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.0 8 Figure 2. Transfer Characteristics VGS = 10 V TJ = 175°C TJ = 125°C TJ = 25°C TJ = −55°C 10 10 12 14 16 18 20 22 24 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Region versus Gate Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 3 2.5 2 1.5 1 ID = 23 A VGS = 10 V 10000 VGS = 0 V TJ = 150°C IDSS, LEAKAGE (nA) 1000 100 TJ = 125°C 0.5 −50 −25 0 25 50 75 100 125 150 175 10 10 20 30 40 50 60 70 80 90 100 Figure 5. On−Resistance Variation with Temperature TJ, JUNCTION TEMPERATURE (°C) Figure 6. Drain−to−Source Leakage Current versus Voltage VDS, DRAIN−TO−SOURCE VOLTAGE (V) http://onsemi.com 3 NTD6415AN QT VDS Qds VGS VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) 1600 TJ = 25°C VGS = 0 V C, CAPACITANCE (pF) 1200 10 8 6 4 2 0 ID = 23 A TJ = 25°C 0 5 10 15 20 25 Qg, TOTAL GATE CHARGE (nC) 100 80 60 40 20 0 30 800 Qgs Ciss 400 Coss 20 40 60 80 0 Crss 0 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. Capacitance Variation 1000 Figure 8. Gate−to−Source Voltage and Drain−to−Source Voltage versus Total Charge 25 IS, SOURCE CURRENT (A) 20 15 10 5 0 0.4 TJ = 25°C VGS = 0 V VDS = 80 V ID = 23 A VGS = 10 V t, TIME (ns) 100 tf 10 tr td(off) td(on) 1 1 10 RG, GATE RESISTANCE (W) 100 0.5 0.6 0.7 0.8 VSD, SOURCE−TO−DRAIN VOLTAGE (V) 0.9 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 1000 AVALANCHE ENERGY (mJ) VGS = 10 V SINGLE PULSE TC = 25°C 10 ms 10 100 ms 1 ms 1 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 dc 80 70 60 50 40 30 20 10 0 100 1000 25 50 75 100 125 ID = 23 A ID, DRAIN CURRENT (A) 100 0.1 1 150 175 Figure 11. Maximum Rated Forward Biased Safe Operating Area VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature TJ, STARTING JUNCTION TEMPERATURE http://onsemi.com 4 NTD6415AN 10 1 R(t) (°C/W) 0.1 D = 0.01 0.02 0.01 0.05 0.2 0.5 SINGLE PULSE 0.01 0.001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, PULSE TIME (s) Figure 13. Thermal Response http://onsemi.com 5 NTD6415AN PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE A −T− B V R 4 SEATING PLANE C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.030 0.045 0.386 0.410 0.018 0.023 0.090 BSC 0.180 0.215 0.024 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.89 0.46 0.61 0.77 1.14 9.80 10.40 0.46 0.58 2.29 BSC 4.57 5.45 0.60 1.01 0.51 −−− 0.89 1.27 3.93 −−− S A 1 2 3 Z H U F L D 2 PL J DIM A B C D E F H J L R S U V Z 0.13 (0.005) M T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 NTD6415AN PACKAGE DIMENSIONS DPAK CASE 369D−01 ISSUE B B V R 4 C E Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− S −T− SEATING PLANE A 1 2 3 K F D G 3 PL J H M 0.13 (0.005) T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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