NTLUD3191PZTAG

NTLUD3191PZ Power MOSFET −20 V, −1.8 A, mCoolt Dual P−Channel, ESD, 1.6x1.6x0.55 mm UDFN Package Features • UDFN Package with Exposed Drain Pads for Excellent Thermal • • • • Conduction Low Profile UDFN 1.6 x 1.6 x 0.55 mm for Board Space Saving ESD This is a Halide Free Device This is a Pb−Free Device http://onsemi.com V(BR)DSS −20 V Applications • • • • High Side Load Switch PA Switch Battery Switch Optimized for Power Management Applications for Portable Products, such as Cell Phones, PMP, DSC, GPS, and others G1 Symbol Value Units Drain-to-Source Voltage VDSS −20 V Gate-to-Source Voltage VGS ±8.0 V ID −1.4 A Continuous Drain Current (Note 1) Power Dissipation (Note 1) Continuous Drain Current (Note 2) Steady State TA = 25°C TA = 85°C −1.0 t≤5s TA = 25°C −1.8 Steady State TA = 25°C t≤5s TA = 25°C Steady State TA = 25°C PD W 1.3 ID TA = 85°C A −1.1 −0.8 TA = 25°C PD 0.5 W Pulsed Drain Current tp = 10 ms IDM −8.0 A TJ, TSTG -55 to 150 °C Source Current (Body Diode) (Note 2) IS −1.0 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C ESD 1000 V Gate-to-Source ESD Rating (HBM) per JESD22−A114F Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu. © Semiconductor Components Industries, LLC, 2009 April, 2009 − Rev. 1 −1.5 A 380 mW @ −2.5 V −1.0 A 500 mW @ −1.8 V −0.5 A 700 mW @ −1.5 V −0.2 A D2 S1 P−Channel MOSFET S2 MARKING DIAGRAM 1 UDFN6 CASE 517AT mCOOLt 1 AC MG G AC = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) Power Dissipation (Note 2) Operating Junction and Storage Temperature 250 mW @ −4.5 V G2 6 0.8 ID MAX D1 MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter RDS(on) MAX 1 (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: NTLUD3191PZ/D NTLUD3191PZ THERMAL RESISTANCE RATINGS Parameter Symbol Max Units Junction-to-Ambient – Steady State (Note 3) RθJA 155 °C/W Junction-to-Ambient – t ≤ 5 s (Note 3) RθJA 100 Junction-to-Ambient – Steady State min Pad (Note 4) RθJA 245 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min −20 Typ Max Units OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ ID = −250 mA, ref to 25°C Zero Gate Voltage Drain Current Gate-to-Source Leakage Current IDSS VGS = 0 V, VDS = −20 V V 15 mV/°C TJ = 25°C −1.0 TJ = 85°C −10 IGSS VDS = 0 V, VGS = ±8.0 V VGS(TH) VGS = VDS, ID = 250 mA 10 mA mA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temp. Coefficient Drain−to−Source On Resistance −0.4 VGS(TH)/TJ RDS(on) Forward Transconductance −1.0 2.5 gFS V mV/°C mW VGS = −4.5 V, ID = −1.5 A 175 250 VGS = −2.5 V, ID = −1.0 A 240 380 VGS = −1.8 V, ID = −0.5 A 330 500 VGS = −1.5 V, ID = −0.2 A 410 700 VDS = −5.0 V, ID = −0.2 A 1.4 S 160 pF CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate-to-Source Charge QGS Gate-to-Drain Charge QGD VGS = 0 V, f = 1 MHz, VDS = −10 V 32 23 2.3 VGS = −4.5 V, VDS = −10 V; ID = −1.5 A 3.5 nC 0.2 0.4 0.7 SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6) Turn-On Delay Time td(ON) 13 tr 24 Rise Time Turn-Off Delay Time td(OFF) Fall Time VGS = −4.5 V, VDD = −10 V, ID = −1.5 A, RG = 1 W tf ns 68 62 DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time ta Discharge Time tb Reverse Recovery Charge 3. 4. 5. 6. VGS = 0 V, IS = −1.0 A TJ = 25°C 0.85 TJ = 85°C 0.75 10 VGS = 0 V, dISD/dt = 100 A/ms, IS = −1.0 A QRR http://onsemi.com 2 V ns 8.0 2.0 5.0 Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. Switching characteristics are independent of operating junction temperatures. 1.2 nC NTLUD3191PZ TYPICAL CHARACTERISTICS VGS = −4.5 V 9 TJ = 25°C −ID, DRAIN CURRENT (A) 8 5 −4.0 V −3.5 V 7 −3.0 V 6 5 −2.5 V 4 −2.0 V 3 2 −1.8 V 1 −1.5 V 0 1 2 3 4 1 0.7 0.6 0.5 ID = −1.5 A 0.4 ID = −0.2 A 1.5 2.0 2.5 3.0 3.5 4.0 4.5 −VGS, GATE−TO−SOURCE VOLTAGE (V) 0.5 1 1.5 2 2.5 −1.5 V 3 TJ = 25°C 0.8 0.6 −1.8 V −2.5 V 0.4 0.2 0 VGS = −4.5 V 0 1 2 3 4 5 6 7 8 9 10 −ID, DRAIN CURRENT (A) Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10000 1.7 VGS = −4.5 V ID = −1.5 A VGS = 0 V −IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 0 1.0 Figure 3. On−Resistance vs. Gate Voltage 1.5 TJ = 25°C TJ = −55°C Figure 2. Transfer Characteristics 0.8 1.6 TJ = 125°C Figure 1. On−Region Characteristics TJ = 25°C 0.1 1.0 2 −VGS, GATE−TO−SOURCE VOLTAGE (V) 0.9 0.2 3 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1.0 0.3 VDS = −5 V 4 0 5 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (A) 10 1.4 1.3 1.2 1.1 1.0 0.9 TJ = 150°C 1000 TJ = 125°C 100 TJ = 85°C 0.8 0.7 0.6 −50 −25 0 25 50 75 100 125 150 10 0 5 10 15 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 20 NTLUD3191PZ VGS = 0 V TJ = 25°C f = 1 MHz C, CAPACITANCE (pF) 225 200 Ciss 175 150 125 100 75 Coss 50 25 0 Crss 0 4 8 12 20 16 5 10 4 VDS 2 4 VGS = −10 V ID = −1.5 A TJ = 25°C 1 0 0 0.25 0.5 0.75 −IS, SOURCE CURRENT (A) t, TIME (ns) tr 10 2 0 2.25 2.5 1.0 TJ = 150°C TJ = 25°C 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 100 RG, GATE RESISTANCE (W) −VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 175 0.85 ID = −250 mA 0.80 150 0.75 125 0.70 POWER (W) −VGS, GATE−TO−SOURCE VOLTAGE (V) 1.25 1.5 1.75 10 td(on) 0.65 0.60 0.55 0.50 100 75 50 0.45 25 0.40 0.35 −50 1 2 Qg, TOTAL GATE CHARGE (nC) td(off) 1 QGD Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge tf 10 8 6 QGS Figure 7. Capacitance Variation VGS = −4.5 V VDD = −10 V ID = −1.5 A VGS 3 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 100 12 QT −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 250 −VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS −25 0 25 50 75 100 125 0 150 0.0000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 TJ, TEMPERATURE (°C) SINGLE PULSE TIME (s) Figure 11. Threshold Voltage Figure 12. Single Pulse Maximum Power Dissipation http://onsemi.com 4 NTLUD3191PZ TYPICAL CHARACTERISTICS −ID, DRAIN CURRENT (AMPS) 10 10 ms 1 100 ms 1 ms VGS = −8 V 0.1 SINGLE PULSE TC = 25°C 0.01 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 Figure 13. Maximum Rated Forward Biased Safe Operating Area 175 150 R(t) (°C/W) 125 100 75 0.5 50 0.2 25 0.1 0.05 0 0.000001 0.02 Single Pulse 0.00001 0.0001 0.001 0.01 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 14. FET Thermal Response DEVICE ORDERING INFORMATION Package Shipping† NTLUD3191PZTAG UDFN6 (Pb−Free) 3000 / Tape & Reel NTLUD3191PZTBG UDFN6 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN6 1.6x1.6, 0.5P CASE 517AT−01 ISSUE O 6 1 SCALE 4:1 A B D 2X 0.10 C PIN ONE REFERENCE 2X 0.10 C ÉÉ ÉÉ ÉÉ DETAIL A E OPTIONAL CONSTRUCTION (A3) A 0.05 C A1 0.05 C SIDE VIEW D1 DETAIL A 6X ÉÉÉ ÈÈÈ EXPOSED Cu TOP VIEW 6X C A1 SEATING PLANE OPTIONAL CONSTRUCTION L 6 4 6X MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 1.60 BSC 1.60 BSC 0.50 BSC 1.14 1.34 0.38 0.58 0.54 0.74 0.20 −−− 0.15 0.35 −−− 0.10 1 XX MG G E1 6X A3 DIM A A1 A3 b D E e D1 D2 E1 K L L1 GENERIC MARKING DIAGRAM* 2X 3 1 MOLD CMPD DETAIL B D2 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 DETAIL B DATE 02 SEP 2008 XX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) b e 0.10 C A B BOTTOM VIEW 0.05 C NOTE 3 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERMASK DEFINED MOUNTING FOOTPRINT* 1.34 2X 0.58 6X 0.48 0.74 1.90 1 0.50 PITCH 6X 0.32 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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