NTLUD3A260PZTBG

NTLUD3A260PZ MOSFET – Power, Dual, P-Channel, ESD, mCool, UDFN, 1.6X1.6X0.55 mm -20 V, -2.1 A http://onsemi.com Features • UDFN Package with Exposed Drain Pads for Excellent Thermal • • • Conduction Low Profile UDFN 1.6x1.6x0.55 mm for Board Space Saving ESD Protected These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MOSFET V(BR)DSS RDS(on) MAX ID MAX 200 mW @ −4.5 V 290 mW @ −2.5 V −20 V −2.1 A 390 mW @ −1.8 V 650 mW @ −1.5 V Applications • High Side Load Switch • PA Switch • Optimized for Power Management Applications for Portable D1 Products, such as Cell Phones, PMP, DSC, GPS, and others G1 D2 G2 MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current (Note 1) Power Dissipation (Note 1) Continuous Drain Current (Note 2) Symbol Value Units VDSS −20 V VGS ±8.0 V ID −1.7 A Steady State TA = 25°C TA = 85°C −1.2 t≤5s TA = 25°C −2.1 Steady State TA = 25°C t≤5s TA = 25°C Steady State TA = 25°C PD 1 W 0.8 TA = 85°C A −1.3 TA = 25°C PD Pulsed Drain Current tp = 10 ms IDM −8.0 A TJ, TSTG -55 to 150 °C Source Current (Body Diode) (Note 2) IS −0.6 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C 0.5 May, 2019− Rev. 1 1 AD MG G AD = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu. © Semiconductor Components Industries, LLC, 2010 UDFN6 CASE 517AT mCOOLt −0.9 Power Dissipation (Note 2) Operating Junction and Storage Temperature S2 MARKING DIAGRAM 6 1.3 ID S1 P−Channel MOSFET 1 (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: NTLUD3A260PZ/D NTLUD3A260PZ THERMAL RESISTANCE RATINGS Symbol Max Units Junction-to-Ambient – Steady State (Note 3) RθJA 155 °C/W Junction-to-Ambient – t ≤ 5 s (Note 3) RθJA 100 Junction-to-Ambient – Steady State min Pad (Note 4) RθJA 245 Parameter ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min −20 Typ Max Units OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA Drain-to-Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ ID = −250 mA, ref to 25°C Zero Gate Voltage Drain Current Gate-to-Source Leakage Current IDSS VGS = 0 V, VDS = −20 V V −10 mV/°C TJ = 25°C −1.0 TJ = 125°C −10 IGSS VDS = 0 V, VGS = ±8.0 V VGS(TH) VGS = VDS, ID = −250 mA ±10 mA mA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temp. Coefficient Drain-to-Source On Resistance Forward Transconductance −0.4 VGS(TH)/TJ −1.0 2.8 RDS(on) gFS V mV/°C VGS = −4.5 V, ID = −2.0 A 160 200 mW VGS = −2.5 V, ID = −1.2 A 226 290 VGS = −1.8 V, ID = −0.24 A 300 390 VGS = −1.5 V, ID = −0.18 A 390 650 VDS = −10 V, ID = −1.5 A 3.7 S 300 pF CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate-to-Source Charge QGS Gate-to-Drain Charge QGD VGS = 0 V, f = 1 MHz, VDS = −10 V 34 29 nC 4.2 VGS = −4.5 V, VDS = −10 V; ID = −1.7 A 0.3 0.7 1.1 SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6) Turn-On Delay Time td(ON) 17.4 tr 32.3 Rise Time Turn-Off Delay Time td(OFF) Fall Time VGS = −4.5 V, VDD = −10 V, ID = −1.5 A, RG = 1 W tf ns 149 74 DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time ta Discharge Time tb Reverse Recovery Charge 3. 4. 5. 6. VGS = 0 V, IS = −0.6 A TJ = 25°C 0.8 TJ = 125°C 0.68 10.6 VGS = 0 V, dis/dt = 100 A/ms, IS = −1.0 A QRR http://onsemi.com 2 V ns 8.7 1.9 5.1 Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. Switching characteristics are independent of operating junction temperatures. 1.2 nC NTLUD3A260PZ TYPICAL CHARACTERISTICS 5 −4.0 V TJ = 25°C VGS = −4.5 V 9 −ID, DRAIN CURRENT (A) 8 −3.0 V 7 6 −2.5 V 5 4 3 −2.0 V 2 −1.8 V 1 −1.5 V 0 1 2 3 4 2 TJ = 25°C 1 TJ = 125°C TJ = −55°C 0 0.5 1.0 1.5 2.0 2.5 −VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 25°C 0.70 ID = −2.0 A 0.60 0.50 0.40 0.30 0.20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 3.0 0.500 TJ = 25°C −1.8 V 0.400 −2.5 V 0.300 0.200 VGS = −4.5 V 0.100 1 2 3 4 5 6 7 8 9 10 −VGS, GATE VOLTAGE (V) −ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10,000 1.6 1.5 1.4 VGS = −4.5 V ID = −2.0 A −IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE (W) 3 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.80 0.10 1.0 4 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VDS ≤ −10 V −3.5 V −ID, DRAIN CURRENT (A) 10 1.3 1.2 1.1 1.0 0.9 TJ = 125°C 1000 TJ = 85°C 0.8 0.7 −50 −25 0 25 50 75 100 125 150 100 2 4 6 8 10 12 14 16 18 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 20 NTLUD3A260PZ VGS = 0 V TJ = 25°C f = 1 MHz C, CAPACITANCE (pF) 400 Ciss 300 200 100 0 Coss Crss 0 2 4 6 8 10 12 14 18 16 20 5 10 4 VDS QGS 6 4 VDS = −10 V ID = −1.7 A TJ = 25°C 1 0 0 1 2 2 0 4 3 QG, TOTAL GATE CHARGE (nC) Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge VGS = −4.5 V VDD = −10 V ID = −1.5 A −IS, SOURCE CURRENT (A) 100 1000 t, TIME (ns) 8 QGD 2 Figure 7. Capacitance Variation td(off) 100 tf tr 10 td(on) 1 10 TJ = 125°C 10 TJ = 25°C TJ = −55°C 1 0.2 100 0.4 0.6 0.8 1.0 1.2 RG, GATE RESISTANCE (W) −VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 200 0.85 ID = −250 mA 0.75 175 150 POWER (W) 0.65 −VGS(th) (V) VGS 3 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1 12 QT −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 500 −VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 0.55 0.45 0.35 100 75 50 0.25 0.15 −50 125 25 −25 0 25 50 75 100 125 0 150 1.E−05 1.E−03 1.E−01 1.E+01 1.E+03 TJ, JUNCTION TEMPERATURE (°C) SINGLE PULSE TIME (s) Figure 11. Threshold Voltage Figure 12. Single Pulse Maximum Power Dissipation http://onsemi.com 4 NTLUD3A260PZ TYPICAL CHARACTERISTICS −ID, DRAIN CURRENT (AMPS) 10 10 ms 1 100 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0.1 R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 1 ms 0 ≤ VGS ≤ −8 V 0.1 SINGLE PULSE TC = 25°C dc 1 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 Figure 13. Maximum Rated Forward Biased Safe Operating Area 160 RqJA = 155°C/W 120 80 Duty Cycle = 0.5 40 0.2 0.05 0.02 0.01 0.1 0 Single Pulse 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03 t, TIME (s) Figure 14. FET Thermal Response DEVICE ORDERING INFORMATION Package Shipping† NTLUD3A260PZTAG UDFN6 (Pb−Free) 3000 / Tape & Reel NTLUD3A260PZTBG UDFN6 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN6 1.6x1.6, 0.5P CASE 517AT−01 ISSUE O 6 1 SCALE 4:1 A B D 2X 0.10 C PIN ONE REFERENCE 2X 0.10 C ÉÉ ÉÉ ÉÉ DETAIL A E OPTIONAL CONSTRUCTION (A3) A 0.05 C A1 0.05 C SIDE VIEW D1 DETAIL A 6X ÉÉÉ ÈÈÈ EXPOSED Cu TOP VIEW 6X C A1 SEATING PLANE OPTIONAL CONSTRUCTION L 6 4 6X MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 1.60 BSC 1.60 BSC 0.50 BSC 1.14 1.34 0.38 0.58 0.54 0.74 0.20 −−− 0.15 0.35 −−− 0.10 1 XX MG G E1 6X A3 DIM A A1 A3 b D E e D1 D2 E1 K L L1 GENERIC MARKING DIAGRAM* 2X 3 1 MOLD CMPD DETAIL B D2 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 DETAIL B DATE 02 SEP 2008 XX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) b e 0.10 C A B BOTTOM VIEW 0.05 C NOTE 3 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERMASK DEFINED MOUNTING FOOTPRINT* 1.34 2X 0.58 6X 0.48 0.74 1.90 1 0.50 PITCH 6X 0.32 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON32372E 6 PIN UDFN, 1.6X1.6, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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