NTMD2C02R2SG

NTMD2C02R2 Preferred Device Power MOSFET 2 Amps, 20 Volts Complementary SOIC−8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain−to−source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc−dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. http://onsemi.com 2 AMPERES 20 VOLTS RDS(on) = 43 mW (N−Channel) RDS(on) = 120 mW (P−Channel) N−Channel D P−Channel D Features • Ultra Low RDS(on) Provides Higher Efficiency and Extends • • • • • • • Battery Life Logic Level Gate Drive − Can Be Driven by Logic ICs Miniature SOIC−8 Surface Mount Package − Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SOIC−8 Package Provided Pb−Free Packages are Available G G S MARKING DIAGRAM & PIN ASSIGNMENT 8 ND ND PD PD 8 1 SOIC−8 CASE 751 STYLE 14 D2C02x AYWW G G MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1) Rating Symbol Drain−to−Source Voltage N−Channel P−Channel VDSS Gate−to−Source Voltage Drain Current − Continuous − Pulsed N−Channel P−Channel N−Channel P−Channel Operating and Storage Temperature Range Total Power Dissipation @ TA= 25°C (Note 2) Thermal Resistance − Junction to Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds. Value Vdc VGS ±12 Vdc ID 5.2 3.4 48 17 A TJ and Tstg −55 to 150 °C PD 2.0 W RJA 62.5 °C/W TL 260 °C IDM March, 2006 − Rev. 1 D2C02 x A Y WW G = Specific Device Code = Blank or S = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Negative signs for P−Channel device omitted for clarity. 2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10 sec. max. © Semiconductor Components Industries, LLC, 2006 1 NS NG PS PG Unit 20 20 S 1 ORDERING INFORMATION Device Package NTMD2C02R2 SOIC−8 Shipping † 2500/Tape & Reel NTMD2C02R2G SOIC−8 2500/Tape & Reel (Pb−Free) NTMD2C02R2SG SOIC−8 2500/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D Preferred devices are recommended choices for future use and best overall value. Publication Order Number: NTMD2C02R2/D NTMD2C02R2 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Note 3) Characteristic Symbol Polarity Min Typ Max Unit V(BR)DSS (N) (P) 20 20 − − − − Vdc (N) (P) − − − − 1.0 1.0 − − − 100 (N) (P) 0.6 0.6 0.9 0.9 1.2 1.2 (N) (P) − 0.07 0.028 − 0.043 0.1 (N) (P) − 0.1 0.033 − 0.048 0.13 (N) (P) 3.0 3.0 6.0 4.75 − − Ciss (N) (P) − − 785 540 1100 750 Coss (N) (P) − − 210 215 450 325 Crss (N) (P) − − 75 100 180 175 td(on) (N) (P) − − 11 15 18 − tr (N) (P) − − 35 40 65 − td(off) (N) (P) − − 45 35 75 − tf (N) (P) − − 60 35 110 − td(on) (N) (P) − − 12 10 20 20 tr (N) (P) − − 50 35 90 65 td(off) (N) (P) − − 45 33 75 60 tf (N) (P) − − 80 29 130 55 QT (N) (P) − − 12 10 20 18 Q1 (N) (P) − − 1.5 1.5 − − Q2 (N) (P) − − 4.0 5.0 − − Q3 (N) (P) − − 3.0 3.0 − − OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 20 Vdc) (VGS = 0 Vdc, VDS = 12 Vdc) IDSS Gate−Body Leakage Current (VGS = ± 12 Vdc, VDS = 0) IGSS Adc nAdc ON CHARACTERISTICS (Note 4) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) Drain−to−Source On−Resistance (VGS = 4.5 Vdc, ID = 4.0 Adc) (VGS = 4.5 Vdc, ID = 2.4 Adc) RDS(on) Drain−to−Source On−Resistance (VGS = 2.7 Vdc, ID = 2.0 Adc) (VGS = 2.7 Vdc, ID = 1.2 Adc) RDS(on) Forward Transconductance (VDS = 2.5 Vdc, ID = 2.0 Adc) (VDS = 2.5 Vdc, ID = 1.0 Adc) gFS Vdc   Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 10 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time (VDD = 16 Vdc, ID = 4.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 1.2 Adc, VGS = 2.7 Vdc, RG = 6.0 ) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time (VDS = 16 Vdc, ID = 6.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) (VDS = 10 Vdc, ID = 2.4 Adc, VGS = 4.5 Vdc, RG = 6.0 ) Total Gate Charge Gate−Source Charge Gate−Drain Charge (VDS = 10 Vdc, ID = 4.0 Adc, VGS = 4.5 Vdc) (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc) 3. Negative signs for P−Channel device omitted for clarity. 4. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 ns nC NTMD2C02R2 ELECTRICAL CHARACTERISTICS − continued (TA = 25°C unless otherwise noted) (Note 6) Characteristic Symbol Polarity Min Typ Max Unit VSD (N) (P) − − 0.83 0.88 1.1 1.0 Vdc trr (N) (P) − − 30 37 − − ns ta (N) (P) − − 15 16 − − tb (N) (P) − − 15 21 − − QRR (N) (P) − − 0.02 0.025 − − SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C) Forward Voltage (Note 7) (IS = 4.0 Adc, VGS = 0 Vdc) (IS = 2.4 Adc, VGS = 0 Vdc) Reverse Recovery Time (IF = IS, dIS/dt = 100 A/s) Reverse Recovery Stored Charge C 6. Negative signs for P−Channel device omitted for clarity. 7. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%. TYPICAL ELECTRICAL CHARACTERISTICS N−Channel 10 V 2.5 V 10 4.5 V 3.2 V 8 4 2.0 V −ID, DRAIN CURRENT (AMPS) I D, DRAIN CURRENT (AMPS) 12 P−Channel TJ = 25°C 1.8 V 6 4 VGS = 1.5 V 2 0 0 0.25 0.5 0.75 1 1.25 1.5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS = −1.7 V 1 VGS = −1.5 V 0 2 4 6 8 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 2. On−Region Characteristics 5 12 VDS ≥ 10 V −ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) VGS = −1.9 V 2 Figure 1. On−Region Characteristics 10 8 6 4 100°C 25°C TJ = −55°C 2 0 TJ = 25°C VGS = −10 V VGS = −4.5 V VGS = −2.5 V 3 0 1.75 VGS = −2.1 V 0.5 1 1.5 2 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VDS ≥ −10 V 4 3 2 1 0 2.5 TJ = 25°C TJ = 100°C 1 TJ = 55°C 1.5 2 2.5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 3. Transfer Characteristics Figure 4. Transfer Characteristics http://onsemi.com 3 3 NTMD2C02R2 RDS(on), DRAIN−TO−SOURCE RESISTANCE () N−Channel 0.07 ID = 6.0 A TJ = 25°C 0.06 0.05 0.04 0.03 0.02 0.01 0 0 2 4 6 8 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 10 Figure 5. On−Resistance versus Gate−To−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE () R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) TYPICAL ELECTRICAL CHARACTERISTICS 0.05 TJ = 25°C 0.04 VGS = 2.5 V 0.03 4.5 V 0.02 0.01 1 3 5 7 9 ID, DRAIN CURRENT (AMPS) 11 13 P−Channel 0.2 0.15 0.1 0.05 0 4 6 8 Figure 6. On−Resistance versus Gate−To−Source Voltage 0.12 TJ = 25°C 0.1 VGS = −2.7 V 0.08 VGS = −4.5 V 0.06 0.04 1 1.5 2 2.5 3 3.5 4 4.5 −ID, DRAIN CURRENT (AMPS) Figure 8. On−Resistance versus Drain Current and Gate Voltage 1.6 1.6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 7. On−Resistance versus Drain Current and Gate Voltage ID = 6.0 A VGS = 4.5 V 1.4 1.2 1 0.8 0.6 −50 TJ = 25°C −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 1.4 ID = −2.4 A VGS = −4.5 V 1.2 1 0.8 0.6 −50 Figure 9. On−Resistance Variation with Temperature −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 10. On−Resistance Variation with Temperature http://onsemi.com 4 150 NTMD2C02R2 TYPICAL ELECTRICAL CHARACTERISTICS N−Channel 1000 VGS = 0 V VGS = 0 V TJ = 125°C 100 100 −IDSS, LEAKAGE (nA) I DSS , LEAKAGE (nA) 1000 P−Channel 100°C 10 1 25°C 0.1 0.01 4 8 12 16 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ = 100°C 10 TJ = 25°C 1 0.1 0.01 20 TJ = 125°C 0 Figure 11. Drain−To−Source Leakage Current versus Voltage 4 8 12 16 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 20 Figure 12. Drain−To−Source Leakage Current versus Voltage POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figures 17 and 18) show how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figures is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) http://onsemi.com 5 NTMD2C02R2 N−Channel 2000 VGS = 0 V Ciss 1500 Crss 1000 Ciss 500 10 5 1200 Coss Crss 0 VDS = 0 V TJ = 25°C 0 VGS VDS 5 10 15 Ciss 900 600 Ciss 300 Coss 0 20 Crss 10 5 V DS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) 16 VGS 2 ID = 6 A VDS = 16 V VGS = 4.5 V TJ = 25°C 8 1 4 0 0 4 0 8 12 16 Qg, TOTAL GATE CHARGE (nC) 20 16 14 1 8 VDS 0 2 4 6 8 10 12 4 14 2 0 Figure 16. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 1000 tf tr VDD = −10 V ID = −1.2 A VGS = −2.7 V 100 tr td(off) td (off) td(on) 10 6 ID = −2.4 A TJ = 25°C Qg, TOTAL GATE CHARGE (nC) t, TIME (ns) t, TIME (ns) 10 Q2 2 0 12 VGS Q1 VDS = 16 V ID = 4.0 A VGS = 4.5 V 1 18 3 1000 10 20 QT Figure 15. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 100 15 4 12 Q2 10 5 20 3 Q1 5 Figure 14. Capacitance Variation QT VDS 0 −VGS −VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 13. Capacitance Variation 4 TJ = 25°C Crss GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 5 VGS = 0 V −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VDS = 0 V P−Channel 1500 C, CAPACITANCE (pF) C, CAPACITANCE (pF) 2500 10 100 tf td (on) 1.0 RG, GATE RESISTANCE (OHMS) Figure 17. Resistive Switching Time Variation versus Gate Resistance 10 RG, GATE RESISTANCE (OHMS) Figure 18. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 6 100 NTMD2C02R2 DRAIN−TO−SOURCE DIODE CHARACTERISTICS high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 24. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by N−Channel P−Channel 2 −IS, SOURCE CURRENT (AMPS) I S, SOURCE CURRENT (AMPS) 5 VGS = 0 V TJ = 25°C 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1.0 1.2 0.8 0.4 0 1.2 VGS = 0 V TJ = 25°C 1.6 0.4 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 0.5 0.6 0.7 0.8 0.9 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 19. Diode Forward Voltage versus Current Figure 20. Diode Forward Voltage versus Current http://onsemi.com 7 1 NTMD2C02R2 di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta t, TIME Figure 21. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the N−Channel P−Channel 100 10 VGS = 20 V SINGLE PULSE TC = 25°C 10 s 100 s 1 ms I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 100 10 ms 1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.01 Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10s max. 0.1 1 VGS = 8 V SINGLE PULSE TC = 25°C 10 Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10s max. 1 ms 10 ms 1 dc 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 10 0.1 100 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 22. Maximum Rated Forward Biased Safe Operating Area Figure 23. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 8 100 NTMD2C02R2 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 Normalized to ja at 10s. Chip 0.0175  0.0710  0.2706  0.5776  0.7086  0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F 0.01 0.01 SINGLE PULSE 0.001 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 t, TIME (s) 1.0E+00 1.0E+01 Figure 24. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 25. Diode Reverse Recovery Waveform http://onsemi.com 9 1.0E+02 Ambient 1.0E+03 NTMD2C02R2 INFORMATION FOR USING THE SOIC−8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self−align when subjected to a solder reflow process. 0.060 1.52 0.275 7.0 0.155 4.0 0.024 0.6 0.050 1.270 inches mm SOIC−8 POWER DISSIPATION The power dissipation of the SOIC−8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SOIC−8 package, PD can be calculated as follows: PD = into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. PD = 150°C − 25°C = 2.0 Watts 62.5°C/W The 62.5°C/W for the SOIC−8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Cladt, the power dissipation can be doubled using the same footprint. TJ(max) − TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When • • • • using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. The soldering temperature and time shall not exceed 260°C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. *Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 10 NTMD2C02R2 TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 26 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177−189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. STEP 4 HEATING ZONES 3 & 6 “SOAK” 160°C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 “SPIKE” 205° TO 219°C PEAK AT 170°C SOLDER JOINT 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 26. Typical Solder Heating Profile MiniMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC). Thermal Clad is a registered trademark of the Bergquist Company. http://onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative