NTMD6N02R2
MOSFET – Power, Dual,
N-Channel Enhancement
Mode, SO-8
6.0 A, 20 V
http://onsemi.com
Features
•
•
•
•
•
•
•
•
Ultra Low RDS(on)
Higher Efficiency Extending Battery Life
Logic Level Gate Drive
Miniature Dual SOIC−8 Surface Mount Package
Diode Exhibits High Speed, Soft Recovery
Avalanche Energy Specified
SOIC−8 Mounting Information Provided
Pb−Free Package is Available
VDSS
RDS(ON) TYP
ID MAX
20 V
35 mW @ VGS = 4.5 V
6.0 A
N−Channel
D
G
Applications
• DC−DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery−Powered Products,
for example, Computers, Printers, Cellular and Cordless Telephones
and PCMCIA Cards
S
SOIC−8
CASE 751
STYLE 11
8
1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Value
Unit
VDSS
20
V
Drain−to−Gate Voltage (RGS = 1.0 MW)
VDGR
20
V
Gate−to−Source Voltage − Continuous
VGS
"12
V
RqJA
PD
ID
ID
IDM
62.5
2.0
6.5
5.5
50
°C/W
W
A
A
A
Thermal Resistance,
Junction−to−Ambient (Note 2)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4)
RqJA
PD
ID
ID
IDM
102
1.22
5.07
4.07
40
°C/W
W
A
A
A
Thermal Resistance
Junction−to−Ambient (Note 3)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4)
RqJA
PD
ID
ID
IDM
172
0.73
3.92
3.14
30
°C/W
W
A
A
A
Source 2
Gate 2
1
8
2
7
3
4
6
5
Drain 1
Drain 1
Drain 2
Drain 2
(Top View)
E6N02 = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NTMD6N02R2
NTMD6N02R2G
1. Mounted onto a 2 in square FR−4 Board
(1 in sq. 2 oz. Cu 0.06 in thick single sided), t < 10 seconds.
2. Mounted onto a 2 in square FR−4 Board
(1 in sq. 2 oz. Cu 0.06 in thick single sided), t = steady state.
3. Minimum FR−4 or G−10 PCB, t = steady state.
4. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
May, 2019 − Rev. 3
Source 1
Gate 1
Thermal Resistance,
Junction−to−Ambient (Note 1)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4)
© Semiconductor Components Industries, LLC, 2005
MARKING DIAGRAM
& PIN ASSIGNMENT
E6N02
ALYWG
G
Symbol
Drain−to−Source Voltage
Package
Shipping†
SOIC−8
2500/Tape & Reel
SOIC−8
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
Publication Order Number:
NTMD6N02R2/D
NTMD6N02R2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (continued)
Rating
Symbol
Value
Unit
Operating and Storage Temperature Range
TJ, Tstg
−55 to +150
°C
EAS
360
mJ
TL
260
°C
Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 6.0 Apk, L = 20 mH, RG = 25 W)
Maximum Lead Temperature for Soldering Purposes for 10 seconds
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (Note 5)
Symbol
Characteristic
Min
Typ
Max
20
−
−
19.2
−
−
−
−
−
−
1.0
10
Unit
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25°C)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc)
IGSS
−
−
100
nAdc
Gate−Body Leakage Current (VGS = −12 Vdc, VDS = 0 Vdc)
IGSS
−
−
−100
nAdc
0.6
−
0.9
−3.0
1.2
−
−
−
−
−
0.028
0.028
0.033
0.035
0.035
0.043
0.048
0.049
gFS
−
10
−
Mhos
Ciss
−
785
1100
pF
Coss
−
260
450
Crss
−
75
180
td(on)
−
12
20
tr
−
50
90
td(off)
−
45
75
tf
−
80
130
td(on)
−
11
18
tr
−
35
65
td(off)
−
45
75
tf
−
60
110
Qtot
−
12
20
Qgs
−
1.5
−
Qgd
−
4.0
−
mAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = −250 mAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−State Resistance
(VGS = 4.5 Vdc, ID = 6.0 Adc)
(VGS = 4.5 Vdc, ID = 4.0 Adc)
(VGS = 2.7 Vdc, ID = 2.0 Adc)
(VGS = 2.5 Vdc, ID = 3.0 Adc)
RDS(on)
Forward Transconductance (VDS = 12 Vdc, ID = 3.0 Adc)
Vdc
mV/°C
W
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 6 and 7)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 16 Vdc, ID = 6.0 Adc,
VGS = 4.5 Vdc,
RG = 6.0 W)
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 16 Vdc, ID = 4.0 Adc,
VGS = 4.5 Vdc,
RG = 6.0 W)
Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
(VDS = 16 Vdc,
VGS = 4.5 Vdc,
ID = 6.0 Adc)
5. Handling precautions to protect against electrostatic discharge is mandatory
6. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%.
7. Switching characteristics are independent of operating junction temperature.
http://onsemi.com
2
ns
ns
nC
NTMD6N02R2
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (continued) (Note 8)
Characteristic
Symbol
Min
Typ
Max
Unit
VSD
−
−
−
0.83
0.88
0.75
1.1
1.2
−
Vdc
trr
−
30
−
ns
ta
−
15
−
tb
−
15
−
QRR
−
0.02
−
BODY−DRAIN DIODE RATINGS (Note 9)
(IS = 4.0 Adc, VGS = 0 Vdc)
(IS = 6.0 Adc, VGS = 0 Vdc)
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Diode Forward On−Voltage
Reverse Recovery Time
(IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
mC
8. Handling precautions to protect against electrostatic discharge is mandatory.
9. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%.
2.5 V
4.5 V
3.2 V
8
12
2.0 V
ID, DRAIN CURRENT (AMPS)
10
TJ = 25°C
1.8 V
6
4
VGS = 1.5 V
2
0
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
10 V
0
0.25
0.5
0.75
1
1.25
1.5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
0.07
ID = 6.0 A
TJ = 25°C
0.06
0.05
0.04
0.03
0.02
0.01
0
0
2
4
6
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
VDS ≥ 10 V
10
8
6
4
10
25°C
100°C
TJ = −55°C
2
0
1.75
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
I D, DRAIN CURRENT (AMPS)
12
0.5
1
1.5
2
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
2.5
Figure 2. Transfer Characteristics
0.05
TJ = 25°C
0.04
VGS = 2.5 V
0.03
4.5 V
0.02
0.01
1
Figure 3. On−Resistance versus
Gate−To−Source Voltage
3
9
5
7
ID, DRAIN CURRENT (AMPS)
11
13
Figure 4. On-Resistance versus Drain Current
and Gate Voltage
http://onsemi.com
3
1.6
1000
ID = 6.0 A
VGS = 4.5 V
1.4
I DSS , LEAKAGE (nA)
1.2
1
VGS = 0 V
TJ = 125°C
100
100°C
10
1
25°C
0.1
0.8
0.6
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
0.01
150
4
VDS = 0 V
2000
VGS = 0 V
TJ = 25°C
Ciss
1500
Crss
1000
Ciss
500
Coss
Crss
0
10
5
0
5
10
15
VGS VDS
20
5
20
QT
4
16
VDS
VGS
3
12
Q1
2
ID = 6 A
VDS = 16 V
VGS = 4.5 V
TJ = 25°C
Q2
8
4
1
0
0
4
8
12
16
Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 7. Capacitance Variation
1000
VDS = 16 V
ID = 6.0 A
VGS = 4.5 V
t, TIME (ns)
C, CAPACITANCE (pF)
2500
100
tf
tr
td(off)
10
td(on)
1
20
Figure 6. Drain−To−Source Leakage Current
versus Voltage
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
8
12
16
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
http://onsemi.com
4
100
0
V DS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
NTMD6N02R2
NTMD6N02R2
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
100
VGS = 0 V
TJ = 25°C
4
I D , DRAIN CURRENT (AMPS)
I S, SOURCE CURRENT (AMPS)
5
3
2
1
0
0
0.2
0.4
0.6
0.8
100 ms
10
1 ms
10 ms
1
0.1
1.2
1.0
VGS = 20 V
SINGLE PULSE
TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
0.1
dc
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 12. Diode Reverse Recovery Waveform
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
P(pk)
0.01
t1
0.001
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
1.0E+00
t, TIME (s)
Figure 13. Thermal Response
http://onsemi.com
5
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) RqJC(t)
1.0E+01
1.0E+02
1.0E+03
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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