NTP35N15
Power MOSFET
37 Amps, 150 Volts
N−Channel TO−220
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Features
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
•
•
•
37 AMPERES
150 VOLTS
50 mW @ VGS = 10 V
Fast Recovery Diode
Avalanche Energy Specified
IDSS and RDS(on) Specified at Elevated Temperature
This is a Pb−Free Device*
N−Channel
D
Applications
• PWM Motor Controls
• Power Supplies
• Converters
G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
150
Vdc
Drain−to−Source Voltage (RGS = 1.0 MW)
VDGR
150
Vdc
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
VGS
VGSM
"20
"40
ID
ID
37
23
111
PD
178
1.43
W
W/°C
Operating and Storage Temperature Range
TJ, Tstg
−55 to
+150
°C
Single Drain−to−Source Avalanche Energy −
Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
IL(pk) = 21.6 A, L = 3.0 mH, RG = 25 W)
EAS
700
mJ
RqJC
RqJA
0.7
62.5
TL
260
Rating
Drain Current
− Continuous @ TA 25°C
− Continuous @ TA 100°C
− Pulsed (Note 1)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
IDM
MARKING DIAGRAM &
PIN ASSIGNMENT
D
Vdc
Adc
35N15G
AYWW
1
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
2
3
TO−220
CASE 221A
STYLE 5
A
Y
WW
G
1
G D S
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NTP35N15G
Package
Shipping
TO−220
(Pb−Free)
50 Units / Rail
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2010
May, 2010 − Rev. 4
1
Publication Order Number:
NTP35N15/D
NTP35N15
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
150
−
−
240
−
−
−
−
−
−
5.0
50
−
−
± 100
2.0
−
2.9
−8.56
4.0
−
−
−
0.042
−
0.050
0.120
−
1.55
1.78
gFS
−
26
−
mhos
Ciss
−
2275
3200
pF
Coss
−
450
650
Crss
−
90
175
td(on)
−
20
35
tr
−
125
225
td(off)
−
90
175
tf
−
120
210
Qtot
−
70
100
Qgs
−
14
−
Qgd
−
32
−
VSD
−
−
1.00
0.88
1.5
−
Vdc
trr
−
170
−
ns
ta
−
112
−
tb
−
58
−
QRR
−
1.14
−
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Collector Current
(VGS = 0 Vdc, VDS = 150 Vdc, TJ = 25°C)
(VGS = 0 Vdc, VDS = 150 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−State Resistance
(VGS = 10 Vdc, ID = 18.5 Adc)
(VGS = 10 Vdc, ID = 18.5 Adc, TJ = 125°C)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 18.5 Adc)
VDS(on)
Forward Transconductance (VDS = 10 Vdc, ID = 18.5 Adc)
Vdc
mV/°C
W
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 2 & 3)
Turn−On Delay Time
(VDD = 120 Vdc, ID = 37 Adc,
VGS = 10 Vdc,
RG = 9.1 W)
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(VDS = 120 Vdc, ID = 37 Adc,
VGS = 10 Vdc)
ns
nC
BODY−DRAIN DIODE RATINGS (Note 2)
Forward On−Voltage
(IS = 37 Adc, VGS = 0 Vdc)
(IS = 37 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 37 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperature.
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2
mC
NTP35N15
60
70
TJ = 25°C
VGS = 10 V
VGS = 5.5 V
VGS = 9 V
50
VGS = 8 V
40
VGS = 7 V
VGS = 5 V
30
VGS = 6 V
20
10
0
VGS = 4.5 V
8
9
1
2
3
4
5
6
7
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
50
40
TJ = 25°C
30
20
TJ = 100°C
10
VGS = 4 V
0
VDS ≥ 10 V
60
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
70
TJ = −55°C
0
10
2
0.055
VDS = 10 V
0.08
TJ = 100°C
0.06
0.04
TJ = 25°C
0.02
0
TJ = −55°C
0
10
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.1
20
30
40
50
ID, DRAIN CURRENT (AMPS)
60
70
TJ = 25°C
0.05
VGS = 10 V
0.45
VGS = 15 V
0.40
0.35
0.03
0
Figure 3. On−Resistance versus Drain Current
and Temperature
2.5
2.25
2.0
7
Figure 2. Transfer Characteristics
10
50
20
30
40
ID, DRAIN CURRENT (AMPS)
60
70
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10,000
ID = 18.5 A
VGS = 10 V
VGS = 0 V
TJ = 150°C
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
3
4
5
6
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1.75
1.5
1.25
1.0
0.75
1000
100
TJ = 100°C
0.5
0.25
0
−50
−25
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
10
150
30 40 50 60 70 80 90 100 110 120 130 140 150
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTP35N15
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
C, CAPACITANCE (pF)
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6000
VDS = 0 V
5000
Ciss
VGS = 0 V
TJ = 25°C
4000
3000
Crss
Ciss
2000
1000
Coss
Crss
0
10
5
5
0
VGS
10
15
20
25
VDS
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
12
120
QT
VDS
80
Q1
Q2
VGS
60
40
4
2
0
20
ID = 37 A
TJ = 25°C
0
10
VDD = 75 V
ID = 37 A
VGS = 10 V
100
8
6
1000
20
30
40
50
QG, TOTAL GATE CHARGE (nC)
60
0
70
t, TIME (ns)
10
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
NTP35N15
td(off)
100
tr
tf
10
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
td(on)
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
40
VGS = 0 V
TJ = 25°C
I S , SOURCE CURRENT (AMPS)
35
30
25
20
15
10
5
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
1.0
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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5
NTP35N15
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
1000
10 ms
100 ms
10
1 ms
10 ms
1
0.1
0.1
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
1.0
100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
700
ID = 21.6 A
600
500
400
300
200
100
0
25
1000
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
150
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.00001
0.0001
0.001
0.01
t, TIME (ms)
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
0.1
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
1.0
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220
CASE 221A
ISSUE AK
DATE 13 JAN 2022
SCALE 1:1
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
BASE
EMITTER
COLLECTOR
EMITTER
STYLE 3:
PIN 1.
2.
3.
4.
CATHODE
ANODE
GATE
ANODE
STYLE 4:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
STYLE 5:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 6:
PIN 1.
2.
3.
4.
ANODE
CATHODE
ANODE
CATHODE
STYLE 7:
PIN 1.
2.
3.
4.
CATHODE
ANODE
CATHODE
ANODE
STYLE 8:
PIN 1.
2.
3.
4.
CATHODE
ANODE
EXTERNAL TRIP/DELAY
ANODE
STYLE 9:
PIN 1.
2.
3.
4.
GATE
COLLECTOR
EMITTER
COLLECTOR
STYLE 10:
PIN 1.
2.
3.
4.
GATE
SOURCE
DRAIN
SOURCE
STYLE 11:
PIN 1.
2.
3.
4.
DRAIN
SOURCE
GATE
SOURCE
STYLE 12:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
NOT CONNECTED
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42148B
TO−220
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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