NTTFS5826NLTAG

NTTFS5826NL MOSFET – Power, Single, N-Channel, m8FL 60 V, 24 mW Features • • • • Small Footprint (3.3 x 3.3 mm) for Compact Designs Low QG(TOT) to Minimize Switching Losses Low Capacitance to Minimize Driver Losses These are Pb−Free Devices http://onsemi.com V(BR)DSS ID MAX 24 mW @ 10 V 60 V Applications • • • • RDS(on) MAX 20 A 32 mW @ 4.5 V Motor Drivers DC−DC Converters Synchronous Rectification Power Management N−Channel D MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RYJ−mb (Notes 1, 2, and 3) Power Dissipation RYJ−mb (Notes 1, 2, and 3) Continuous Drain Current RqJA (Notes 1 & 3) Tmb = 25°C Value Unit VDSS 60 V VGS "20 V ID 20 A Tmb = 100°C Tmb = 25°C Steady State PD Tmb = 100°C TA = 25°C TA = 25°C Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL(pk) = 14.4 A, L = 1.0 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) W 19 ID A 8 PD W 3.1 1.6 IDM 133 A TJ, Tstg −55 to 175 °C IS 20 A EAS 20 mJ Junction−to−Ambient − Steady State (Note 3) WDFN8 (m8FL) CASE 511AB 5826 A Y WW G 5826 AYWWG G D D D D = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device TL 260 °C THERMAL RESISTANCE MAXIMUM RATINGS Junction−to−Mounting Board (top) − Steady State (Notes 2, 3) 1 S S S G 1 6 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Parameter S MARKING DIAGRAM 10 TA = 100°C TA = 25°C, tp = 10 ms G 14 TA = 100°C Power Dissipation RqJA (Notes 1 & 3) Pulsed Drain Current Symbol Symbol Value Unit RYJ−mb 7.9 °C/W RqJA 48 Package Shipping† NTTFS5826NLTAG WDFN8 1500/Tape & Reel (Pb−Free) NTTFS5826NLTWG WDFN8 5000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. © Semiconductor Components Industries, LLC, 2011 June, 2019 − Rev. 2 1 Publication Order Number: NTTFS5826NL/D NTTFS5826NL 2. Psi (Y) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. http://onsemi.com 2 NTTFS5826NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current 58.6 IDSS Gate−to−Source Leakage Current V VGS = 0 V, VDS = 60 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA ±100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance 1.5 3.0 5.6 gFS VGS = 10 V ID = 7.5 A 19 24 VGS = 4.5 V ID = 7.5 A 25 32 VDS = 15 V, ID = 5.0 A V mV/°C mW 8 S 850 pF CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 50 Total Gate Charge QG(TOT) 8.4 Threshold Gate Charge QG(TH) 1.0 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge VGS = 0 V, f = 1.0 MHz, VDS = 25 V VGS = 4.5 V, VDS = 48 V, ID = 5.0 A 85 2.5 3.9 QG(TOT) VGS = 10 V, VDS = 48V, ID = 5.0A 16 RG TA = 25°C 1.5 Gate Resistance nC 25 nC W SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) 9.0 18 15 28 14 25 tf 5.4 12 td(on) 7.0 12 10 20 17 30 3.5 6.0 TJ = 25°C 0.8 2.3 TJ = 125°C 0.7 tr td(off) tr td(off) VGS = 4.5 V, VDS = 48 V, ID = 5.0 A, RG = 2.5 W VGS = 10 V, VDS = 48 V, ID = 5.0 A, RG = 2.5 W tf ns ns DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD VGS = 0 V, IS = 7.5 A tRR 15 Charge Time ta 12 Discharge Time tb Reverse Recovery Charge VGS = 0 V, dIS/dt = 100 A/ms, IS = 5.0 A QRR http://onsemi.com 3 ns 4 13 4. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. V nC NTTFS5826NL TYPICAL CHARACTERISTICS VGS = 10 V 40 TJ = 25°C VGS = 4.5 V VGS = 3.8 V VDS ≥ 10 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 40 30 VGS = 3.6 V 20 VGS = 3.2 V 10 30 20 TJ = 25°C 10 TJ = 125°C VGS = 2.8 V 0 0 1 2 3 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0 5 1 2 3 4 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.055 0.045 0.035 0.025 0.015 2 4 6 8 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.040 TJ = 25°C 0.030 VGS = 4.5 V 0.010 5 10 15 20 25 30 35 40 ID, DRAIN CURRENT (A) Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.10 10000 ID = 7.5 A VGS = 4.5 V VGS = 0 V 1.70 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) VGS = 10 V 0.020 Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.90 5 Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics ID = 7.5 A TJ = 25°C TJ = −55°C 1.50 1.30 1.10 0.90 TJ = 150°C 1000 TJ = 125°C 0.70 0.50 −50 −25 0 25 50 75 100 125 150 175 100 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 60 NTTFS5826NL TYPICAL CHARACTERISTICS C, CAPACITANCE (pF) Ciss 800 600 400 200 Coss Crss 0 0 10 20 30 40 50 VGS, GATE−TO−SOURCE VOLTAGE (V) 10 VDS = 0 V TJ = 25°C 1000 60 4 0 IS, SOURCE CURRENT (A) td(on) 1 10 RG, GATE RESISTANCE (W) 100 100 ms 1 ms 10 ms 10 ms dc RDS(on) Limit Thermal Limit Package Limit 0.1 4 8 12 16 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS = 0 V TJ = 25°C 30 20 10 0 0.5 0.6 0.7 0.8 0.9 1.0 VSD, SOURCE−TO−DRAIN VOLTAGE (V) 1.1 Figure 10. Diode Forward Voltage vs. Current EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) ID, DRAIN CURRENT (A) VGS = 10 V Single Pulse TC = 25°C 10 0.1 0 40 td(off) 1 VDS = 48 V ID = 5 A TJ = 25°C 2 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 100 Qgd Figure 8. Gate−to−Source vs. Total Charge tf 1000 Qgs Figure 7. Capacitance Variation tr t, TIME (ns) 6 Qg, TOTAL GATE CHARGE (nC) VDD = 48 V ID = 5 A VGS = 4.5 V 1 8 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 100 10 QT 100 20 ID = 20 A 15 10 5 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTTFS5826NL TYPICAL CHARACTERISTICS 100 D = 0.5 D = 0.2 D = 0.1 D = 0.05 RqJA (t) 10 D = 0.02 1 D = 0.01 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (sec) Figure 13. Thermal Response http://onsemi.com 6 1 10 100 1000 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN8 3.3x3.3, 0.65P CASE 511AB ISSUE D 1 SCALE 2:1 DATE 23 APR 2012 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D A D1 B 2X 0.20 C 8 7 6 5 4X E1 E q c 1 2 3 4 A1 TOP VIEW 0.10 C A e SIDE VIEW 0.10 8X b C A B 0.05 C 4X DETAIL A 8X e/2 1 0.42 4 INCHES NOM 0.030 −−− 0.012 0.008 0.130 BSC 0.116 0.120 0.078 0.083 0.130 BSC 0.116 0.120 0.058 0.063 0.009 0.012 0.026 BSC 0.012 0.016 0.026 0.032 0.012 0.017 0.002 0.005 0.055 0.059 0_ −−− MIN 0.028 0.000 0.009 0.006 MAX 0.031 0.002 0.016 0.010 0.124 0.088 0.124 0.068 0.016 0.020 0.037 0.022 0.008 0.063 12 _ 0.65 PITCH PACKAGE OUTLINE 4X 0.66 M E3 8 5 D2 BOTTOM VIEW 1 3.60 L1 GENERIC MARKING DIAGRAM* XXXXX A Y WW G MILLIMETERS MIN NOM MAX 0.70 0.75 0.80 0.00 −−− 0.05 0.23 0.30 0.40 0.15 0.20 0.25 3.30 BSC 2.95 3.05 3.15 1.98 2.11 2.24 3.30 BSC 2.95 3.05 3.15 1.47 1.60 1.73 0.23 0.30 0.40 0.65 BSC 0.30 0.41 0.51 0.65 0.80 0.95 0.30 0.43 0.56 0.06 0.13 0.20 1.40 1.50 1.60 0_ −−− 12 _ SOLDERING FOOTPRINT* L G SEATING PLANE DETAIL A K E2 C 6X 0.10 C DIM A A1 b c D D1 D2 E E1 E2 E3 e G K L L1 M q XXXXX AYWWG G 0.75 2.30 0.57 0.47 2.37 3.46 DIMENSION: MILLIMETERS = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98AON30561E WDFN8 3.3X3.3, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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