RFP30P06

RFG30P06, RFP30P06, RF1S30P06SM Data Sheet January 2002 30A, 60V, 0.065 Ohm, P-Channel Power MOSFETs Features • 30A, 60V These are P-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They are designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA09834. Ordering Information PART NUMBER PACKAGE TO-247 RFG30P06 RFP30P06 TO-220AB RFP30P06 RF1S30P06SM TO-263AB F1S30P06 • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • 175oC Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND RFG30P06 • rDS(ON) = 0.065Ω D G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, i.e. RF1S30P06SM9A. S Packaging JEDEC STYLE TO-247 JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (BOTTOM SIDE METAL) DRAIN (FLANGE) SOURCE DRAIN GATE JEDEC TO-263AB GATE DRAIN (FLANGE) SOURCE ©2002 Fairchild Semiconductor Corporation RFG30P06, RFP30P06, RF1S30P06SM Rev. B RFG30P06, RFP30P06, RF1S30P06SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Deratlng Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg RFG30P06, RFP30P06 RF1S30P06SM -60 -60 ±20 30 Refer to Peak Current Curve Refer to UIS Curve 135 0.9 -55 to 175 UNITS V V V A W W/oC oC oC oC 300 260 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V -60 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA -2 - -4 V IDSS VDS = -60V, VGS = 0V - - -1 µA VDS = 0.8 x Rated BVDSS, TC = 150oC - - -25 µA Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IGSS rDS(ON) Turn-On Time t(ON) Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VGS = ±20V - - ±100 nA ID = -30A, VGS = -10V (Figure 9) - - 0.065 Ω VDD = -30V, ID = 15A, RL = 2.00Ω, VGS = -10V RG = 6.25Ω (Figure 13) - - 80 ns - 15 - ns tr - 23 - ns td(OFF) - 28 - ns tf - 18 - ns t(OFF) - - 100 ns - 140 170 nC - 70 85 nC - 5.5 6.6 nC - 3200 - pF - 800 - pF - 175 - pF Total Gate Charge Qg(TOT) VGS = 0 to -20V Gate Charge at -10V Qg(-10) VGS = 0 to -10V Threshold Gate Charge Qg(TH) VGS = 0 to -2V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance, Junction to Case RθJC Thermal Resistance, Junction to Ambient RθJA VDD = -48V, ID = 30A, RL = 1.6Ω, IG(REF) = 1.6mA VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) TO-220, TO-263 - - 1.11 oC/W - - 62 oC/W 30 oC/W TO-247 Source to Drain Diode Specifications MIN TYP MAX MAX Source to Drain Diode Voltage (Note 2) PARAMETER SYMBOL VSD ISD = -30A TEST CONDITIONS - - -1.5 V Diode Reverse Recovery Time tRR ISD = -30A, dISD/dt = -100A/µs - - 150 ns NOTES: 2. Pulse test: pulse width ≤ 300µs maximum, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). ©2002 Fairchild Semiconductor Corporation RFG30P06, RFP30P06, RF1S30P06SM Rev. B RFG30P06, RFP30P06, RF1S30P06SM Typical Performance Curves Unless Otherwise Specified POWER DISSIPATION MULTIPLIER 1.2 -40 ID , DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 -30 -20 -10 0.2 0 0 25 50 75 100 125 150 0 175 25 50 TC , CASE TEMPERATURE (oC) 75 100 125 150 175 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 0.5 0.2 PDM 0.1 0.1 0.05 t1 t2 0.02 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE -500 -200 100µs 1ms -10 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED -1 100ms DC -10 -1 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA ©2002 Fairchild Semiconductor Corporation -100 IDM , PEAK CURRENT (A) -100 ID , DRAIN CURRENT (A) FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: VGS = -20V VGS = -10V  175 – T C I = I 25  --------------------- 150   -100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -10 10-5 TC = 25oC 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 5. PEAK CURRENT CAPABILITY RFG30P06, RFP30P06, RF1S30P06SM Rev. B RFG30P06, RFP30P06, RF1S30P06SM Typical Performance Curves Unless Otherwise Specified (Continued) -100 -75 -10 VGS = -10V ID, DRAIN CURRENT (A) IAS , AVALANCHE CURRENT (A) VGS = -20V STARTING TJ = 25oC STARTING TJ = 150oC If R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) -60 VGS = -8V VGS = -7V -45 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC -30 VGS = -6V -15 VGS = -5V If R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] -1 0.1 VGS = -4.5V 0 1 10 tAV , TIME IN AVALANCHE (ms) 0 100 -2 -4 -6 -8 -10 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322, FIGURE 7. SATURATION CHARACTERISTICS 2 -75 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = -15V -60 NORMALIZED DRAIN TO SOURCE ON RESISTANCE IDS(ON), DRAIN TO SOURCE CURRENT (A) FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 25oC -55oC -45 175oC -30 -15 0 -2 0 -8 -6 -4 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = -10V, ID = 30A 1.5 1 0.5 0 -80 -10 -40 80 120 160 200 2 2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 40 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 8. TRANSFER CHARACTERISTICS 1.5 1 0.5 0 -80 0 TJ , JUNCTION TEMPERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V) -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE ©2002 Fairchild Semiconductor Corporation ID = 250µA 1.5 1 0.5 0 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE RFG30P06, RFP30P06, RF1S30P06SM Rev. B RFG30P06, RFP30P06, RF1S30P06SM Unless Otherwise Specified C, CAPACITANCE (pF) CISS 3000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGS 2000 COSS -60 VDS, DRAIN TO SOURCE VOLTAGE (V) 4000 (Continued) 1000 CRSS -10 VDD = BVDSS -7.5 RL = 2.0Ω IG(REF) = -1.6mA VGS = -10V -10 -15 -20 -5 -30 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS -15 -2.5 DRAIN SOURCE VOLTAGE 0 -5 VDD = BVDSS -45 0 0 GATE SOURCE VOLTAGE -25 20 VDS , DRAIN TO SOURCE VOLTAGE (V) IG(REF) IG(ACT) VGS, GATE TO SOURCE VOLTAGE (V) Typical Performance Curves 0 t, TIME (µs) 80 IG(REF) IG(ACT) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN REQUIRED PEAK IAS - RG + 0V VGS VDD DUT VDD tP IAS IAS VDS tP 0.01Ω BVDSS FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) tr VDS 0 RL tf 10% 10% VGS VDS VDD + VGS DUT RGS VGS 0 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 16. SWITCHING TIME TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation FIGURE 17. RESISTIVE SWITCHING WAVEFORMS RFG30P06, RFP30P06, RF1S30P06SM Rev. B RFG30P06, RFP30P06, RF1S30P06SM Test Circuits and Waveforms (Continued) VDS RL VDS Qg(TH) 0 VGS = -2V VGS - VGS = -10V -VGS VDD Qg(-10) + DUT VGS = -20V VDD Ig(REF) Qg(TOT) 0 Ig(REF) FIGURE 18. GATE CHARGE TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation FIGURE 19. GATE CHARGE WAVEFORMS RFG30P06, RFP30P06, RF1S30P06SM Rev. B RFG30P06, RFP30P06, RF1S30P06SM PSPICE Electrical Model .SUBCKT RFP30P06 2 1 3; REV 8/21/94 CA 12 8 3.23e-9 CB 15 14 3.23e-9 CIN 6 8 3.08e-9 ESG - DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 6 DPLCAPMOD 5 51 EBREAK ESCL + 17 18 - 50 GATE 11 RDRAIN DPLCAP EVTO 20 + 18 8 LGATE RGATE VTO + DBODY 16 21 6 9 MOS2 MOS1 DBREAK RIN CIN 8 RSOURCE LSOURCE 7 3 SOURCE MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 S2A S1A 12 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 39.85e-3 RGATE 9 20 2.34 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 2.56e-3 RVTO 18 19 RVTOMOD 1 RSCL1 + 51 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.92e-9 LSOURCE 3 7 4.60e-9 DRAIN 2 LDRAIN 5 RSCL2 EBREAK 5 11 17 18 -77.3 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 + 8 6 10 13 8 S1B RBREAK 15 14 13 17 18 S2B 13 CA RVTO CB + EGS - 14 + 6 8 EDS - 6 8 IT 19 VBAT + S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.81 ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/114,5))} .MODEL DBDMOD D (IS=4.7e-13 RS=1.31e-2 TRS1=1.39e-4 TRS2=-4.77e-6 CJO=2.85e-9 TT=8.81e-8) .MODEL DBKMOD D (RS=2.23e-1 TRS1=1.97e-3 TRS2=-2.37e-5) .MODEL DPLCAPMOD D (CJO=0.78e-9 IS=1e-30 N=10) .MODEL MOSMOD PMOS (VTO=-3.75 KP=10.83 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=9.08e-4 TC2=-1.72e-6) .MODEL RDSMOD RES (TC1=5.01e-3 TC2=1.02e-5) .MODEL RSCLMOD RES (TC1=2.09e-3 TC2=5.88e-7) .MODEL RVTOMOD RES (TC1=-2.99e-3 TC2=1.40e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.4 VOFF=1.4) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.4 VOFF=3.4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.2 VOFF=-3.8) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.8 VOFF=1.2) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; authors, William J. Hepp and C. Frank Wheatley. ©2002 Fairchild Semiconductor Corporation RFG30P06, RFP30P06, RF1S30P06SM Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST  FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET  VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4