RFP70N03

RFP70N03, RF1S70N03, RF1S70N03SM Data Sheet January 2002 70A, 30V, 0.010 Ohm, N-Channel Power MOSFETs Features • 70A, 30V These N-Channel power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49025. Ordering Information PART NUMBER PACKAGE • rDS(ON) = 0.010Ω • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve (Single Pulse) • 175oC Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND D RFP70N03 TO-220AB RFP70N03 RF1S70N03 TO-262AA F1S70N03 RF1S70N03SM TO-263AB F1S70N03 G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, e.g., RF1S70N03SM9A S Packaging JEDEC TO-220AB DRAIN (FLANGE) JEDEC TO-263AB SOURCE DRAIN GATE GATE DRAIN (FLANGE) SOURCE JEDEC TO-262AA DRAIN (FLANGE) ©2002 Fairchild Semiconductor Corporation SOURCE DRAIN GATE RFP70N03, RF1S70N03, RF1S70N03SM Rev. C RFP70N03, RF1S70N03, RF1S70N03SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg UNITS V V V 30 30 ±20 70 200 Figure 5 150 1.0 -55 to 175 A A W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 30 - - V Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 9) 2 - 4 V VDS = 30V, VGS = 0V - - 1 µA VDS = 30V, VGS = 0V, TC = 150oC - - 50 µA VGS = ±20V - - 100 nA ID = 70A, VGS = 10V (Figure 8) - - 0.010 Ω VDD = 15V, ID ≅ 70A, RL = 0.214Ω, VGS = 10V, RGS = 2.5Ω - - 80 ns - 20 - ns tr - 20 - ns td(OFF) - 40 - ns tf - 25 - ns tOFF - - 125 ns - 215 260 nC - 120 145 nC - 6.5 8.0 nC - 3300 - pF - 1750 - pF - 750 - pF Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance IGSS rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDD = 24V, ID ≅ 70A, RL = 0.343Ω Ig(REF) = 1.0mA (Figure 12) VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) Thermal Resistance Junction to Case RθJC (Figure 3) - - 1.0 oC/W Thermal Resistance Junction to Ambient RθJA TO-220, TO-263 - - 62 oC/W MIN TYP MAX UNITS ISD = 70A - - 1.5 V ISD = 70A, dISD/dt = 100A/µs - - 125 ns Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time ©2002 Fairchild Semiconductor Corporation SYMBOL VSD trr TEST CONDITIONS RFP70N03, RF1S70N03, RF1S70N03SM Rev. C RFP70N03, RF1S70N03, RF1S70N03SM Typical Performance Curves 80 POWER DISSIPATION MULTIPLIER 1.2 70 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 60 50 40 30 20 10 0 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 175 25 ZθJC, NORMALIZED THERMAL IMPEDANCE FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 100 0.5 0.2 10-1 PDM 0.1 0.05 t1 t2 0.02 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 10-2 -5 10 10-4 10-3 10-2 10-1 t1, RECTANGULAR PULSE DURATION (s) 10-0 101 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 300 100µs ID, DRAIN CURRENT (A) 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 10ms 100ms DC TC = 25oC TJ = MAX RATED SINGLE PULSE 1 1 VDSS(MAX) = 30V 10 VDS, DRAIN TO SOURCE VOLTAGE (V) IAS, AVALANCHE CURRENT (A) 300 IDM 100 If R = 0 tAV = (L) (IAS)/(1.3 x RATED BVDSS - VDD) 10 50 STARTING TJ = 25oC STARTING TJ = 150oC If R ≠ 0 tAV = (L/R) ln [(IAS x R)/(1.3 x RATED BVDSS - VDD) +1] 0.01 0.10 1 10 tAV , TIME IN AVALANCHE (ms) NOTE: Refer to Application Notes AN9321 and AN9322. FIGURE 4. FORWARD BIAS SAFE OPERATING AREA ©2002 Fairchild Semiconductor Corporation FIGURE 5. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY RFP70N03, RF1S70N03, RF1S70N03SM Rev. C RFP70N03, RF1S70N03, RF1S70N03SM Typical Performance Curves 200 VGS = 10V (Continued) 200 VGS = 8V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V VGS = 7V 160 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 120 DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 160 VGS = 6V 80 VGS = 5V -55oC 25oC 120 175oC 80 40 40 VGS = 4V 0 0 0 1.5 3.0 4.5 6.0 7.5 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 70A VGS = VDS , ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.0 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 1.6 1.2 0.8 0.4 0 -80 200 -40 TJ, JUNCTION TEMPERATURE (oC) 40 80 120 160 200 FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 7000 2.0 ID = 250µA VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 6000 1.6 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 0 TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.2 0.8 5000 CISS 4000 3000 COSS 2000 0.4 CRSS 1000 0 -80 10 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE ©2002 Fairchild Semiconductor Corporation 0 0 5 10 15 20 25 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE RFP70N03, RF1S70N03, RF1S70N03SM Rev. C RFP70N03, RF1S70N03, RF1S70N03SM Typical Performance Curves (Continued) VDS, DRAIN SOURCE VOLTAGE (V) VDD = BVDSS VDD = BVDSS 7.5 22.5 5.0 15.0 0.75BVDSS 0.75BVDSS 0.50BVDSS 0.50BVDSS 0.25BVDSS 0.25BVDSS RL = 0.43Ω Ig(REF) = 3.0mA VGS = 10V 7.5 0 I g ( REF ) 20 --------------------I g ( ACT ) 2.5 VGS, GATE SOURCE VOLTAGE (V) 10.0 30.0 0 I g ( REF ) 80 --------------------I g ( ACT ) t, TIME (µs) NOTE: Refer to Application Notes AN7254 and AN7260. FIGURE 12. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) VDS td(OFF) tr VDS tf 90% 90% RL VGS + DUT RGS VGS - VDD 90% VGS 0 FIGURE 15. SWITCHING TIME TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation 10% 10% 0 10% 50% 50% PULSE WIDTH FIGURE 16. SWITCHING WAVEFORMS RFP70N03, RF1S70N03, RF1S70N03SM Rev. C RFP70N03, RF1S70N03, RF1S70N03SM Test Circuits and Waveforms (Continued) VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD DUT Ig(REF) VGS = 10V VGS - VGS = 2V 0 Qg(TH) Ig(REF) 0 FIGURE 17. GATE CHARGE TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation FIGURE 18. GATE CHARGE WAVEFORM RFP70N03, RF1S70N03, RF1S70N03SM Rev. C RFP70N03, RF1S70N03, RF1S70N03SM PSPICE Electrical Model .SUBCKT RFP70N03 2 1 3 ; *NOM TEMP = 25oC rev 9/16/92 CA 12 8 6.09e-9 CB 15 14 6.05e-9 CIN 6 8 3.40e-9 10 DPLCAP - 9 1 LGATE 20 RGATE 18 8 - VTO 16 + - EVTO GATE RDRAIN DBREAK ESG 6 + 8 + EBREAK 11 7 17 18 35.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 6 MOS1 S1A RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 30.7e-6 RGATE 9 20 0.890 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.92e-3 RVTO 18 19 RVTOMOD 1 13 8 S1B RSOURCE S2A 14 13 17 18 CIN 8 12 11 EBREAK IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.10e-9 LSOURCE 3 7 1.82e-9 DBODY MOS2 21 RIN MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 DRAIN 2 LDRAIN 5 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD 15 17 + 7 LSOURCE RBREAK S2B 3 SOURCE 18 RVTO 13 CA + EGS 6 - 8 CB 14 + 5 EDS 8 IT 19 - VBAT + - S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.605 .MODEL DBDMOD D (IS=7.91e-12 RS=3.87e-3 TRS1=2.71e-3 TRS2=2.50e-7 CJO=4.84e-9 TT=4.51e-8) .MODEL DBKMOD D (RS=3.9e-2 TRS1=1.05e-4 TRS2=3.11e-5) .MODEL DPLCAPMOD D (CJO=4.8e-9 IS=1e-30 N=10) .MODEL MOSMOD NMOS (VTO=3.46 KP=47 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=8.46e-4 TC2=-8.48e-7) .MODEL RDSMOD RES (TC1=2.23e-3 TC2=6.56e-6) .MODEL RVTOMOD RES (TC1=-3.29e-3 TC2=3.49e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8.35 VOFF=-6.35) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.35 VOFF=-8.35) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=3.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.0 VOFF=-2.0) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. ©2002 Fairchild Semiconductor Corporation RFP70N03, RF1S70N03, RF1S70N03SM Rev. C TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST  FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET  VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4