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onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
STK541UC62K-E
Intelligent Power Module (IPM)
600 V, 10 A
Overview
This “Inverter IPM” is highly integrated device containing all High Voltage
(HV) control from HV-DC to 3-phase outputs in a single SIP module
(Single-In line Package). Output stage uses IGBT/FRD technology and
implements Under Voltage Protection (UVP) and Over Current Protection
(OCP) with a Fault Detection output flag. Internal Boost diodes are provided
for high side gate boost drive.
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Function
Single control power supply due to Internal bootstrap circuit for high side
pre-driver circuit
All control input and status output are at low voltage levels directly
compatible with microcontrollers
Built-in cross conduction prevention
Externally accessible embedded thermistor for substrate temperature
measurement
Certification
UL1557 (File Number : E339285)
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Symbol
Conditions
Supply voltage
VCC
P to N, surge < 500 V
Collector-emitter voltage
VCE
Output current
Io
Output peak current
Iop
Pre-driver voltage
VD1, 2, 3, 4
Input signal voltage
FLTEN terminal voltage
Maximum power dissipation
VIN
VFLTEN
Unit
450
V
P to U, V, W or U, V, W to N
600
V
P, N, U, V, W terminal current
±10
A
P, N, U, V, W terminal current at Tc = 100C
±5
A
P, N, U, V, W terminal current for a Pulse width of 1 ms.
±20
A
VB1 to U, VB2 to V, VB3 to W, VDD to VSS
20
V
*2
HIN1, 2, 3, LIN1, 2, 3
FLTEN terminal
Pd
IGBT per channel
Junction temperature
Tj
IGBT, FRD
Storage temperature
Operating substrate
temperature
Tightening torque
Tstg
Tc
Ratings
*1
IPM case temperature
Case mounting screws
*3
0.3 to 7
V
0.3 to VDD
V
22
W
150
C
40 to +125
C
40 to +100
C
0.9
Isolation voltage
Vis
50 Hz sine wave AC 1 minute
*4
2000
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1 : Surge voltage developed by the switching operation due to the wiring inductance between “P” and “N” terminal.
*2 : Terminal voltage: VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = VDD to VSS
*3 : Flatness of the heat-sink should be 0.15 mm and below.
*4 : Test conditions : AC 2500 V, 1 s.
Nm
VRMS
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
October 2016 - Rev. 1
1
Publication Order Number :
STK541UC62K-E/D
STK541UC62K-E
Electrical Characteristics at Tc 25C, VD1, VD2, VD3, VD4 = 15 V
Parameter
Symbol
Conditions
Test
circuit
min
typ
max
Unit
0.1
mA
0.1
mA
1.4
2.3
1.7
2.6
1.3
1.6
1.3
2.2
1.6
2.5
1.2
Power output section
Collector-emitter cut-off current
ICE
VCE = 600 V
Bootstrap diode reverse current
IR(BD)
VR(BD)
Collector to emitter
saturation voltage
Diode forward voltage
VCE(sat)
VF
Fig.1
Ic = 10 A
Upper side
Tj = 25C
Lower side *1
Ic = 5 A
Upper side
Tj = 100C
Lower side *1
IF = 10 A
Upper side
Tj = 25C
Lower side *1
IF = 5 A
Upper side
Tj = 100C
Lower side *1
Junction to case
θj-c(T)
IGBT
thermal resistance
θj-c(D)
FRD
Fig.2
Fig.3
1.5
V
V
5.5
0.08
0.4
1.6
4.0
2.5
V
0.8
V
6.5
C/W
Control (Pre-driver) section
Pre-driver current consumption
VD1, 2, 3 = 15 V
ID
Fig.4
VD4 = 15 V
mA
High level Input voltage
Vin H
Low level Input voltage
Vin L
Input threshold voltage hysteresis *1
Vinth(hys)
0.5
0.8
V
Logic 0 input leakage current
IIN+
VIN = +3.3 V
76
118
160
A
Logic 1 input leakage current
IIN-
VIN = 0 V
97
150
203
A
FLTEN terminal input electric current
IoSD
FAULT : ON/VFLTEN = 0.1 V
2
mA
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3 to VSS
FAULT clearance delay time
FLTCLR
Fault output latch time
6
9
12
ms
FLTEN Threshold
VEN+
VEN-
Enable
2.5
V
Disable
0.8
10.5
11.1
11.7
V
10.3
10.9
11.5
V
0.14
0.2
A
VCC and VS undervoltage upper
threshold
VSUV+
VCC and VS undervoltage lower
threshold
VSUV-
VCC and VS undervoltage hysteresis
VCCUV+
VCCUVVCCUVH
VSUVH-
Over current protection level
ISD
PW = 100 μs
Output level for current monitor
ISO
Io = 10 A
Fig.5
10
17
A
0.30
0.33
0.36
V
min
typ
max
Unit
0.2
0.4
1.1
0.5
1.2
200
J
s
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1 : The lower side’s VCE(sat) and VF include a loss by the shunt resistance
Electrical Characteristics at Tc 25C, VD1, VD2, VD3, VD4 = 15 V, VCC = 300 V,
Parameter
Symbol
Conditions
Test
circuit
L = 3.9 mH
Switching Character
tON
Io = 10 A
tOFF
Inductive load
Turn-on switching loss
Eon
Ic = 5 A, P = 300 V,
Turn-off switching loss
Eoff
VDD = 15 V, L = 3.9 mH
Total switching loss
Etot
Tc = 25C
Turn-on switching loss
Eon
Ic = 5 A, P = 300 V,
Turn-off switching loss
Eoff
VDD = 15 V, L = 3.9 mH
Total switching loss
Etot
Tc = 100C
Diode reverse recovery energy
Erec
IF = 5 A, P = 400 V, VDD = 15 V,
Diode reverse recovery time
Trr
L = 0.5 mH, Tc = 100C
Reverse bias safe operating area
RBSOA
Io = 20 A, VCE = 450 V
Short circuit safe operating area
SCSOA
VCE = 400 V, Tc = 100C
Switching time
Fig.6
Fig.6
Fig.6
130
330
240
160
400
17
62
s
J
J
J
J
J
J
ns
Full square
4
Reference voltage is “VSS” terminal voltage unless otherwise specified.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Notes :
1. The pre-drive power supply low voltage protection has approximately 0.2 V of hysteresis and operates as follows.
Upper side : The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the input signal will
turn ‘high’.
Lower side : The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage.
2. The pre-drive low voltage protection is the feature to protect devices when the pre-driver supply voltage falls due to an operating malfunction.
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2
STK541UC62K-E
Equivalent Block Diagram
VB1(7)
U(8)
VB2(4)
V(5)
VB3(1)
W(2)
P(10)
U.V.
U.V.
U.V.
Shunt Resistor
N(12)
Thermistor
VTH (13)
Level
Level
Level
Shifter
Shifter
Shifter
HIN1(15)
HIN2(16)
HIN3(17)
LIN1(18)
Logic
Logic
Logic
LIN2(19)
LIN3(20)
FLTEN(21)
ISO(22)
VDD(14)
VSS(23)
Latch
Over-Current
VDD-Under Voltage
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3
Latch Time About 9ms
( Automatic Reset )
STK541UC62K-E
Module Pin-Out Description
Pin
Name
Description
1
VB3
High Side Floating Supply Voltage 3
2
W, VS3
Output 3 - High Side Floating Supply Offset Voltage
3
Witout Pin
4
VB2
High Side Floating Supply voltage 2
5
V,VS2
Output 2 - High Side Floating Supply Offset Voltage
6
Witout Pin
7
VB1
High Side Floating Supply voltage 1
8
U,VS1
Output 1 - High Side Floating Supply Offset Voltage
9
Witout Pin
10
P
Positive Bus Input Voltage
11
Witout Pin
12
N
Negative Bus Input Voltage
13
VTH
Temperature Feedback
14
VDD
+15 V Main Supply
15
HIN1
Logic Input High Side Gate Driver - Phase U
16
HIN2
Logic Input High Side Gate Driver - Phase V
17
HIN3
Logic Input High Side Gate Driver - Phase W
18
LIN1
Logic Input Low Side Gate Driver - Phase U
19
LIN2
Logic Input Low Side Gate Driver - Phase V
20
LIN3
Logic Input Low Side Gate Driver - Phase W
21
FLTEN
Fault output and Enable
22
ISO
Current monitor output
23
VSS
Negative Main Supply
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4
STK541UC62K-E
Test Circuit
The tested phase U+ shows the upper side of the U phase and U shows the lower side of the U phase.
■ ICE / IR(BD)
ICE
U+
V+
W+
U-
V-
W-
M
10
10
10
8
5
2
N
8
5
2
12
12
12
1
M
A
VD3=15V
2
4
VD2=15V
5
VCE
7
U(BD)
V(BD)
W(BD)
M
7
4
1
N
23
23
23
VD1=15V
8
14
VD4=15V
23
N
Fig.1
1
■ VCE(sat) (test by pulse)
M
VD3=15V
2
U+
V+
W+
U-
V-
W-
M
10
10
10
8
5
2
N
8
5
2
12
12
12
m
15
16
17
18
19
20
4
VD2=15V
5
V
Ic
7
VD1=15V
VCE(SAT)
8
14
VD4=15V
m
23
N
Fig.2
■ VF (test by pulse)
M
U+
V+
W+
U-
V-
W-
M
10
10
10
8
5
2
N
8
5
2
12
12
12
V
N
Fig.3
■ ID
VD1
VD2
VD3
VD4
M
7
4
1
14
N
8
5
2
23
ID
A
M
VD*
N
Fig.4
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5
VF
IF
STK541UC62K-E
■ ISD
1
8
VD3=15V
2
4
VD2=15V
Input signal
(0 to 5 V)
5
Io
7
VD1=15V
Io
8
14
SD
VD4=15V
Input signal
100μS
18
23
12
Fig.5
■ Switching time (The circuit is a representative example of the lower side U phase.)
1
10
VD1=15V
Input signal
(0 to 5 V)
2
4
VD2=15V
5
90%
8
7
Vcc
CS
VD3=15V
Io
8
14
10%
VD4=15V
tOFF
Input signal
Io
18
23
12
Fig.6
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6
STK541UC62K-E
Input / Output Timing Diagram
VBS undervoltage protection reset signal
OFF
HIN1,2,3
ON
LIN1,2,3
*2
VDD
VDD undervoltage protection reset voltage
*3
VBS undervoltage protection reset voltage
VB1,2,3
*4
-------------------------------------------------------ISD operation current level-------------------------------------------------------
-terminal
(BUS line)
Current
FLTEN terminal
Voltage
(at pulled-up)
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Automatically reset after protection
(typ.9ms)
Fig.7
Notes
*1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay needs to be
added externally.
*2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. When VDD rises the operation will
resume immediately.
*3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The
outputs return to normal operation immediately after the upper side gate voltage rises.
*4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 6 to
12ms after the over current condition is removed.
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7
STK541UC62K-E
Logic level table
P
INPUT
Ho
HIN1,2,3
(15,16,17)
IC
Driver
U,V,W
(8,5,2)
LIN1,2,3
(18,19,20)
OUTPUT
Upper Lower
IGBT IGBT
HIN
LIN
OCP
FAULTEN
U,V,W
FAULTEN
H
L
OFF
Pulled-UP
OFF
ON
N
OFF
L
H
OFF
Pulled-UP
ON
OFF
P
OFF
OFF
L
L
OFF
Pulled-UP
OFF
OFF
High
Impedance
H
H
OFF
Pulled-UP
OFF
OFF
High
Impedance
OFF
X
X
ON
Pulled-UP
OFF
OFF
High
Impedance
ON
X
X
OFF
L
OFF
OFF
High
Impedance
ON
Lo
N
Fig. 8
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8
STK541UC62K-E
Sample Application Circuit
CB
CB
VSS
VTH
VDD
ISO
FLTEN
LIN3
LIN2
LIN1
HIN3
HIN2
HIN1
U
VB1
7 8
N
4 5
P
1 2
V
VB2
W
VB3
STK541UC62K-E
10
12 15 16 17 18 19 20 21 22 14 23 13
CB
CS
RP
VP
CD
Control Logic
Vcc
VDD=15V
CI
Fig. 9
Recommended Operating Conditions
Item
Supply voltage
Pre-driver supply voltage
Symbol
Conditions
VCC
P to N
VD1, 2, 3
VB1 to U, VB2 to V, VB3 to W
VDD to VSS
VD4
ON-state input voltage
VIN(ON)
OFF-state input voltage
VIN(OFF)
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3
*1
min
typ
max
Unit
V
0
280
450
12.5
15
17.5
13.5
16.5
0
15
3.0
5.0
0.3
V
V
PWM frequency
fPWM
1
Dead time
DT
Turn-off to turn-on
2
20
1
μs
0.6
0.9
Nm
Allowable input pulse width
PWIN
ON and OFF
Tightening torque
‘M3’ type screw
kHz
μs
*1 Pre-drive power supply (VD4 = 15 ±1.5 V) must have the capacity of Io = 20 mA (DC), 0.5 A (Peak).
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Usage Precaution
1. This IPM includes bootstrap diode and resistors. Therefore, by adding a capacitor “CB”, a high side drive voltage is generated;
each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47 μF, however this
value needs to be verified prior to production. If selecting the capacitance more than 47 μF (±20%), connect a resistor (about 20
Ω) in series between each 3-phase upper side power supply terminals (VB1,2,3) and each bootstrap capacitor.
When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply.
2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of
surge voltages. Recommended value of “CS” is in the range of 0.1 to 10 μF.
3. “ISO” (pin22) is terminal for current monitor. When the pull-down resistor is used, please select it more than 5.6 kΩ
4. “FLTEN” (pin21) is open DRAIN output terminal (Active Low). Pull up resistor is recommended more than 5.6 kΩ.
5. Inside the IPM, a thermistor used as the temperature monitor for internal subatrate is connected between VSS terminal and VTH
terminal, therefore, an external pull up resistor connected between the TH terminal and an external power supply should be used.
The temperature monitor example application is as follows, please refer the Fig.10 and below.
6. The over-current protection feature is not intended to protect in exceptional fault condition. An external fuse is recommended for
safety.
7. When “N” and “VSS” terminal are short-circuited on the outside, level that over-current protection (ISD) might be changed from
designed value as IPM. Please check it in your set (“N” terminal and “VSS” terminal are connected in IPM).
8. When input pulse width is less than 1.0 μs, an output may not react to the pulse. (Both ON signal and OFF signal)
This data shows the example of the application circuit, does not guarantee a design as the mass production set.
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9
STK541UC62K-E
The characteristic of thermistor
Parameter
Symbol
Condition
Min
Typ.
Max
Unit
Resistance
R25
Tc = 25C
99
100
101
kΩ
Resistance
R100
Tc = 100C
5.12
5.38
5.66
kΩ
4165
4250
4335
K
40
+125
C
B-Constant (25 to 50 C)
B
Temperature Range
Case Temperature(Tc) - Thermal resistance(RTH)
10000
Thermistor Resistanse, RTH-Kohm
min
typ
1000
max
100
10
1
-40
-30
-20
-10
0
10
20 30 40 50 60 70
Case temperature, Tc-degC
80
90
100 110 120 130
Fig.10 Variation of thermistor resistance with temperature
Case Temperature(Tc) - TH terminal voltage(VTH)
6.0
Thermistor Pin Read-Out Voltage, VTH-V
min
typ
5.0
max
4.0
3.0
2.0
1.0
0.0
-40
-30
-20
-10
0
10
20 30 40 50 60 70
Case temperature, Tc-degC
80
90
Fig.11 Variation of thermistor terminal voltage with temperature
(47 k pull-up resistor, 5 V)
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10
100 110 120 130
STK541UC62K-E
The characteristic of PWM switching frequency
Maximum RMS Output Current / Phase
(A)
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
14
16
18
PWM Switching Frequency (kHz)
Fig. 12 Maximum sinusoidal phase current as function of switching frequency
at Tc = 100℃, VCC = 400 V
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11
20
STK541UC62K-E
CB capacitor value calculation for bootstrap circuit
Calculate conditions
Parameter
Symbol
Value
Unit
Upper side power supply
VBS
15
V
Total gate charge of output power IGBT at 15 V
QG
89
nC
Upper limit power supply low voltage protection
UVLO
12
V
Upper side power dissipation
IDMAX
400
μA
ON time required for CB voltage to fall from 15 V to UVLO
TONMAX
s
Capacitance calculation formula
Thus, the following formula are true
VBS x CB - QG - IDMAX * TONMAX = UVLO * CB
therefore,
CB = (QG + IDMAX * TONMAX) / (VBS - UVLO)
The relationship between TONMAX and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated
above. The recommended value of CB is in the range of 1 to 47 μF, however, this value needs to be verified prior to production.
CB vs Tonmax
Bootstrap Capacitance CB [uF]
100
10
1
0.1
0.01
0.1
1
10
Tonmax [ms]
Fig. 15 Tonmax - CB characteristic
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12
100
1000
STK541UC62K-E
PACKAGE DIMENSIONS
unit : mm
The tolerances of length are +/ 0.5 mm unless otherwise specified.
56.0
missing pin ; 3, 6, 9, 11
note3
2.0
9.0
23
1
0.6+0.2
-0.05
0.5+0.2
-0.05
2.0
22.0
4.3
note1
(10.9)
STK541UC62K
21.8
4DB00
0.5
R1.
7
3.4
note2
5.0
22 x 2.0 = 44.0
3.2
5.0
46.2
2.0
note1 : Mark for No.1 pin identification.
note2 : The form of a character in this
drawing differs from that of IPM.
note3 : This indicates the date code.
The form of a character in this
drawing differs from that of IPM.
50.0
62.0
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13
STK541UC62K-E
ORDERING INFORMATION
Device
STK541UC62K-E
Package
Shipping (Qty / Packing)
SIP23 56x21.8
(Pb-Free)
8 / Tube
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries
in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other
intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON
Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is
responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or
standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its
patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support
systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall
indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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