STK544UC62K-E

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Other names and brands may be claimed as the property of others. STK544UC62K-E Intelligent Power Module (IPM) 600 V, 10 A Overview This Inverter IPM includes the output stage of a 3-phase inverter, pre-drive circuits, bootstrap circuits, and protection circuits in one package. www.onsemi.com Function  SIP (single in-line package) of the transfer full mold structure.  The emitter line of the each lower phase outputs to an external terminal with the option of control using 3-phase current detection with external resistors.  Direct input of CMOS level control signals without an insulating circuit is possible.  Protective circuits including over current and pre-drive low voltage protection are built in.  A single power supply drive is enabled through the use of bootstrap circuits for upper IGBT gate drives.  Built-in dead-time for shoot-thru protection.  Internal substrate temperature is measured with an internal pulled up thermistor. Certification  UL1557 (File Number : E339285) Specifications Absolute Maximum Ratings at Tc = 25C Parameter Supply voltage Collector-emitter voltage Symbol VCC VCE Output current Io Output peak current Iop Conditions V+ to VRU(VRV,VRW), surge < 500 V V+ to U(V,W) or U(V,W) to VRU(VRV,VRW) V+, VRU,VRV,VRW, U,V,W terminal current *1 V+, VRU,VRV,VRW, U,V,W terminal current at Tc = 100C V+, VRU,VRV,VRW, U,V,W terminal current for a pulse width of 1 ms VB1 to U, VB2 to V, VB3 to W, VDD to VSS *2 HIN1, 2, 3, LIN1, 2, 3 terminals ITRIP terminal IGBT per 1 channel IGBT,FRD Ratings 450 600 ±10 ±6 Unit V V A A ±20 A Pre-driver voltage VD1,2,3,4 20 V Input signal voltage VIN V 0.3 to 7 VSS+5 ITRIP terminal voltage VITRIP V Maximum power dissipation Pd 22 W Junction temperature Tj 150 C Storage temperature Tstg 40 to +125 C Operating case temperature Tc IPM case temperature 40 to +100 C Tightening torque Case mounting screws *3 0.9 Nm Withstand voltage Vis 50 Hz sine wave AC 1 minute *4 2000 VRMS Reference voltage is “VSS” terminal voltage unless otherwise specified. *1 : Surge voltage developed by the switching operation due to the wiring inductance between V+ and VRU(VRV,VRW) terminals. *2 : VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = VDD to VSS terminal voltage. *3 : Flatness of the heat-sink should be less than 50 m to +100 m. *4 : Test conditions : AC 2500 V, 1 second. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORDERING INFORMATION See detailed ordering and shipping information on page 15 of this data sheet. © Semiconductor Components Industries, LLC, 2016 December 2016 - Rev. 3 1 Publication Order Number : STK544UC62K-E/D STK544UC62K-E Electrical Characteristics at Tc  25C, VD1, VD2, VD3, VD4 = 15 V Parameter Symbol Test circuit Conditions Ratings Unit min typ max - - 0.1 mA - - 0.1 mA Power output section Collector-emitter cut-off current ICE VCE = 600 V Bootstrap diode reverse current IR(BD) VR(BD) = 600 V Collector to emitter saturation voltage VCE(SAT) Diode forward voltage VF Bootstrap diode forward voltage VF(BD) - 1.4 2.3 - 1.3 - - 1.3 2.2 - 1.2 - - - 2.0 - - - 2 - - - 10 - - 4.5 5.5 - 5.5 6.5 - 0.1 - 6 9 12 Fig.2 Io = 10 A, Tj = 25C Fig.3 Io = 5 A, Tj = 100C IF = 0.1 A RBS θj-c(T) IGBT θj-c(D) FRD Rth(c-s) 1W/mK thermal conductivity FLTCLR Form time fault condition clears t ON Io = 10 A Bootstrap circuit resistance Thermal resistance case to sink Io = 10 A, Tj = 25C Io = 5 A, Tj = 100C Resistor value for common boot charge line Resister values for separate boot charge lines RBC Junction to case thermal resistance Fig.1 V V V Ω *1 C/W Protection section FAULT clearance delay time Switching time Fig.5 t OFF Inductive load Reference voltage is “VSS” terminal voltage unless otherwise specified. *1 : At 100 μm thickness of the thermal grease. - 0.48 - - 0.54 - ms μs Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Electrical Characteristics Driver Function at Tc  25C Parameter Symbol Ratings Test circuit min typ max - 10.5 11.1 11.7 V - 10.3 10.9 11.5 V - 0.14 0.2 - V - 2.0 4.0 mA - 0.08 0.4 mA - 0.8 V - V Unit Supply section VDDUV+ VDD and VBS supply undervoltage protection reset VBSUV+ VDDUV- VDD and VBS supply undervoltage protection set VBSUVVDDUVH VDD and VBS supply undervoltage hysteresis VBSUVH Quiescent VDD supply current IQDD Quiescent VBS supply current IQBS Fig.4 Input section Logic low input voltage VINL - - Logic high input voltage VINH - 2.5 Logic 0 input leakage current IIN+ - 76 118 160 μA Logic 1 input leakage current IIN- - 97 150 203 μA ITRIP threshold voltage (OUT = LO or OUT = HI) VITRIP - 3.67 4.17 4.67 V Dead time (Internal dead time injected by driver) DT - 220 300 380 ns ITRIP to shutdown propagation delay tITRIP - 1.0 1.2 1.4 μs - - 0.9 - μs Dynamic section ITRIP blanking time tITRPBL Reference voltage is “VSS” terminal voltage unless otherwise specified. www.onsemi.com 2 STK544UC62K-E Switching Characteristics at Tc  25C, VD1, VD2, VD3, VD4 = 15 V Parameter Symbol Conditions Ratings min typ max Unit Turn-on switching loss Eon IC = 5 A, V+ = 400 V - 195 - μJ Turn-off switching loss Eoff VDD = 15 V, L = 3.9 mH, - 122 - μJ Total switching loss Etot Tc = 25C - 317 - μJ Turn-on switching loss Eon IC = 5 A, V+ = 400 V, - 224 - μJ Turn-off switching loss Eoff VDD = 15 V, L = 3.9 mH, - 186 - μJ Total switching loss Etot Tc = 100C - 410 - μJ Diode reverse recovery time trr - 70 - ns Reverse bias safe operating area RBSOA IF = 5A, V+ = 400 V, VDD = 15 V, L = 3.9 mH, Tc = 100C Io = 20 A, VCE = 450 V FULL SQUARE - VCE = 400 V Short circuit safe operating area SCSOA 4 μs VDD = VB1 = VB2 = VB3 = 15 V, VSS = VS1 = VS2 = VS3 = 0 V, outputs loaded with 1 nF, all voltage are referenced to VSS ; unless otherwise noted. Internal NTC-Thermistor Characteristics Parameter Conditions R25 Resistance Tc = 25C R125 Resistance Tc = 125C B B-Constant (25 to 50C) R2 = R1e [B(1/T2-1/T1)] Temperature range - Typ. Dissipation constant Tc=25C Typ. Unit 100 ±3% kΩ 2.522 ±3% kΩ 4250 ±1% K 40 to +125 C 1 mW/C Notes 1. The pre-drive power supply low voltage protection has approximately 200 mV of hysteresis and operates as follows. Upper side : The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the input signal will turn ‘high’. Lower side : The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage. 2. When assembling the IPM on the heat sink the tightening torque range is 0.6 Nm to 0.9 Nm. 3. The pre-drive low voltage protection protects the device when the pre-drive supply voltage falls due to an operating malfunction. 4. When use the over-current protection with external shunt resistor, please set the current protection level to be equal to or less than the rating of output peak current (Iop). www.onsemi.com 3 STK544UC62K-E Equivalent Block Diagram VB3 (1) RBS W,VS3 (2) VB2 (4) RBS V,VS2 (5) VB1 (7) RBS U,VS1 (8) V+ (10) BD BD BD U.V. U.V. U.V. RBC VRU (12) VRV (13) VRW (14) Level Shifter Level Shifter Level Shifter HIN1 (15) HIN2 (16) HIN3 (17) Logic Logic Logic LIN1 (18) LIN2 (19) LIN3 (20) Thermistor T/ITRIP (21) Shut down VDD (22) S Under voltage DETECT Vref VSS (23) Q Timer R Latch time about 9ms Module Pin-Out Description Pin Name Description Pin Name Description 1 VB3 High Side Floating Supply Voltage 3 12 VRU Low Side Emitter Connection – Phase 1 2 W, VS3 Output 3, High Side Floating Supply Offset Voltage 3 13 VRV Low Side Emitter Connection – Phase 2 3 - Without pin 14 VRW Low Side Emitter Connection – Phase 3 4 VB2 High Side Floating Supply Voltage 2 15 HIN1 Logic Input High Side Gate Driver – Phase 1 5 V, VS2 Output 2, High Side Floating Supply Offset Voltage 2 16 HIN2 Logic Input High Side Gate Driver – Phase 2 6 - Without pin 17 HIN3 Logic Input High Side Gate Driver – Phase 3 7 VB1 High Side Floating Supply Voltage 1 18 LIN1 Logic Input Low Side Gate Driver – Phase 1 8 U, VS1 Output 1, High Side Floating Supply Offset Voltage 1 19 LIN2 Logic Input Low Side Gate Driver – Phase 2 9 - Without pin 20 LIN3 Logic Input Low Side Gate Driver – Phase 3 10 V+ Positive Bus Input Voltage 21 T/Itrip Temperature Monitor and Shut-down Pin 11 - Without pin 22 VDD +15 V Main Supply - - - 23 VSS Negative Main Supply www.onsemi.com 4 STK544UC62K-E Test Circuit The tested phase U+ shows the upper side of the U phase and U- shows the lower side of the U phase. ■ ICE / IR(BD) U+ V+ W+ U- V- W- M 10 10 10 8 5 2 N 8 5 2 12 13 14 7 VD1=15V A M ICE 8 4 VD2=15V 5 VCE U(BD) V(BD) W(BD) M 7 4 1 N 23 23 23 1 VD3=15V 2 22 VD4=15V 23 N Fig. 1 ■ VCE(SAT) (test by pulse) U+ V+ W+ U- V- 7 W- M 10 10 10 8 5 2 N 8 5 2 12 13 14 m 15 16 17 18 19 20 VD1=15V M 8 4 VD2=15V 5 Io V 1 VD3=15V VCE(SAT) 2 22 VD4=15V m 23 N 21 Fig. 2 ■ VF (test by pulse) U+ V+ W+ U- V- W- M 10 10 10 8 5 2 N 8 5 2 12 13 14 M V N Fig. 3 ■ ID ID VD1 VD2 VD3 VD4 M 7 4 1 22 N 8 5 2 23 A M VD* N Fig. 4 www.onsemi.com 5 VF Io STK544UC62K-E ■ Switching time (The circuit is a representative example of the lower side U phase.) 10 7 VD1=15V Input signal ( 0 to 5V ) 8 4 VD2=15V 5 8 1 90% VD3=15V Io 10% tON CS 2 22 VD4=15V Input signal VCC Io 18 12 23 tOFF Fig. 5 ■ RB-SOA (The circuit is a representative example of the lower side U phase.) 10 7 VD1=15V Input signal ( 0 to 5V ) 8 4 VD2=15V 5 8 CS 1 Io VD3=15V 2 22 VD4=15V Input signal Io 18 12 23 Fig. 6 www.onsemi.com 6 VCC STK544UC62K-E Input / Output Timing Diagram VBS undervoltage protection reset signal OFF HIN1,2,3 ON LIN1,2,3 *2 VDD VDD undervoltage protection reset voltage *3 VBS undervoltage protection reset voltage VB1,2,3 VIT≥4.67V *4 ITRIP terminal Voltage VIT