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STK554U362A-E
Intelligent Power Module (IPM)
600 V, 10 A
Overview
This “Inverter IPM” is highly integrated device containing all High
Voltage (HV) control from HV-DC to 3-phase outputs in a single small SIP
module. Output stage uses IGBT/FRD technology and implements Under
Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault
Detection output flag. Internal Boost diodes are provided for high side gate
boost drive.
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PACKAGE PICTURE
Function
Single control power supply due to Internal bootstrap circuit for high side
pre-driver circuit
All control inputs and status outputs are at low voltage levels directly
compatible with microcontrollers.
A single power supply drive is enabled through the use of bootstrap circuits
for upper power supplies
Built-in dead-time for shoot-thru protection
Having open emitter output for low side IGBTs ; individual shunt resistor
per phase for OCP
Externally accessible embedded thermistor for substrate temperature
measurement
SIP29 56x21.8
MARKING DIAGRAM
Shutdown function ‘ITRIP’ to disable all operations of the 6 phase output
stage by external input
Certification
UL1557 (File number : E339285)
Typical Applications
Industrial Pumps
Industrial Fans
Industrial Automation
Home Appliances
STK554U362A = Specific Device Code
A = Year
B = Month
C = Production Site
DD = Factory Lot Code
Device marking is on package underside
2D Code Format: DMX code (22X22)
Content of the code Digit
Model Lot code
1–5
Module parts number 7-19
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
December 2016 - Rev. 3
1
Publication Order Number :
STK554U362A-E/D
STK554U362A-E
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Supply voltage
Collector-emitter voltage
Symbol
VCC
VCE
Remarks
V+ to U-, V-, W-, surge < 500 V *1
V+ to U, V, W or U, V, W, to U-, V-, WV+,U-,V-,W-,U,V,W terminal current
Ratings
Unit
V
V
A
A
A
V
HIN1, 2, 3, LIN1, 2, 3
450
600
±10
±7
±20
20
0.3 to VDD
FLTEN terminal
0.3 to VDD
V
Maximum power dissipation
Pd
IGBT per 1 channel
30
Junction temperature
Tj
IGBT, FRD, Pre-Driver IC
150
Storage temperature
Tstg
40 to +125
Operating case
Tc
IPM case
40 to +100
temperature
Tightening torque
A screw part *3
0.9
Withstand voltage
Vis
50 Hz sine wave AC 1 minute *4
2000
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1 : Surge voltage developed by the switching operation due to the wiring inductance between V+ and U-(V-, W-) terminal.
*2 : VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = VDD to VSS terminal voltage.
*3 : Flatness of the heat-sink should be less than 50 m to +100 m.
*4 : Test conditions : AC 2500 V, 1 second.
W
Output current
Io
Output peak current
Pre-driver voltage
Input signal voltage
FLTEN terminal voltage
V+,U-,V-,W-,U,V,W terminal current, Tc = 100C
V+,U-,V-,W-,U,V,W terminal current, P.W. = 1 ms
VB1 to U, VB2 to V, VB3 to W, VDD to VSS *2
Iop
VD1, 2, 3, 4
VIN
VFLTEN
V
C
C
C
Nm
VRMS
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Electrical Characteristics at Tc = 25C, VD1, VD2, VD3, VD4 = 15 V
Parameter
Symbol
Power output section
Collector-emitter cut-off current
Bootstrap diode reverse current
ICE
IR(DB)
Collector to emitter saturation voltage
VCE(sat)
Diode forward voltage
VF
Junction to case thermal resistance
θj-c(T)
θj-c(D)
Conditions
VCE = 600 V
VR(DB) = 600 V
Ic = 10 A, Tj = 25C
Ic = 5 A, Tj = 100C
IF = 10 A, Tj = 25C
IF = 5 A, Tj = 100C
IGBT
FWD
Test
circuit
Fig.1
Fig.2
Fig.3
Min
Typ
Max
Unit
1.6
1.35
1.6
1.3
100
100
2.2
μA
μA
4
5
2.5
0.08
1.6
0.4
4
100
0.8
143
2
2.1
V
V
C/W
Control (Pre-driver) section
Pre-driver power dissipation
ID
High level Input voltage
Low level Input voltage
Logic 1 input leakage current
Logic 0 input leakage current
FLTEN terminal sink current
FLTEN clearance delay time
Vin H
Vin L
IIN+
IINIoSD
FLTCLR
VEN+
VENVITRIP
tITRIP
tITRIPBL
VCCUV+
VBSUV+
VCCUVVBSUVVCCUVH
VBSUVH
FLTEN Threshold
VD1, 2, 3 = 15 V
VD4 = 15 V
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3 to VSS
VIN = +3.3 V
VIN = 0 V
FAULT : ON / VFLTEN = 0.1 V
From time fault condition clear
VEN rising
VEN falling
ITRIP(16) to VSS(29)
ITRIP threshold voltage
ITRIP to shutdown propagation delay
ITRIP blanking time
VCC and VBS supply undervoltage
protection reset
VCC and VBS supply undervoltage
protection set
VCC and VBS supply undervoltage
hysteresis
Resistance between
Thermistor for substrate temperature
Rt
TH(27) and VSS(29)
Monitor
Reference voltage is “VSS” terminal voltage unless otherwise specified.
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2
Fig.4
mA
1.3
2
1.65
0.8
0.44
340
250
0.49
550
350
0.54
800
V
V
μA
μA
mA
ms
V
V
V
ns
ns
10.5
11.1
11.7
V
10.3
10.9
11.5
V
0.14
0.2
V
42.3
47
51.7
kΩ
2
2.5
STK554U362A-E
Parameter
Symbol
Conditions
Test
circuit
Min
Typ
Max
0.4
0.65
Unit
Switching Character
Switching time
t ON
t OFF
Turn-on switching loss
Eon
Turn-off switching loss
Eoff
Total switching loss
Etot
Turn-on switching loss
Eon
Turn-off switching loss
Eoff
Total switching loss
Etot
Io = 10 A
Inductive load
Fig.5
+
Io = 5 A,V = 300 V,
VDD = 15 V, L = 650 H
Tc = 25C
+
Io = 5 A, V = 300 V,
VDD = 15 V, L = 650 H
Tc = 100C
+
μs
130
μJ
122
μJ
252
μJ
156
μJ
154
μJ
310
μJ
Diode reverse recovery energy
Erec
6.9
μJ
trr
I0 = 5 A, V = 400 V, VDD = 15 V,
L = 650 H, Tc = 100C
Diode reverse recovery time
57
ns
Reverse bias safe operating area
RBSOA
Io = 20 A, VCE = 450 V
SCSOA
VCE = 400 V, Tc = 100C
4
μs
50
50
V/ns
Short circuit safe operating area
Allowable offset voltage slew rate
dv/dt
Between U(V,W) to U-(V-,W-)
Reference voltage is “VSS” terminal voltage unless otherwise specified.
Full square
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Notes
1. The pre-drive power supply low voltage protection has approximately 200 mV of hysteresis and operates as follows.
Upper side : The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will
continue till the input signal will turn ‘low’.
Lower side : The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal
voltage.
2. When assembling the IPM on the heat sink the tightening torque range is 0.6 Nm to 0.9 Nm.
3. The pre-drive low voltage protection protects the device when the pre-drive supply voltage falls due to an operating malfunction.
4. When use the over-current protection with external shunt resistor, please set the current protection level to be equal to or less than the
rating of output peak current (Iop).
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3
STK554U362A-E
Module Pin-Out Description
Pin
Name
Description
1
VB3
High Side Floating Supply Voltage 3
2
W, VS3
Output 3 - High Side Floating Supply Offset Voltage
3
-
Without pin
4
-
Without pin
5
VB2
High Side Floating Supply voltage 2
6
V,VS2
Output 2 - High Side Floating Supply Offset Voltage
7
-
Without pin
8
-
Without pin
9
VB1
High Side Floating Supply voltage 1
10
U,VS1
Output 1 - High Side Floating Supply Offset Voltage
11
-
Without pin
12
-
Without pin
13
V+
Positive Bus Input Voltage
14
-
Without pin
15
-
Without pin
16
ITRIP
Current protection pin
17
U-
Low Side Emitter Connection - Phase U
18
FLTEN
Enable input / Fault output
19
V-
Low Side Emitter Connection - Phase V
20
HIN1
Logic Input High Side Gate Driver - Phase U
21
W-
Low Side Emitter Connection - Phase W
22
HIN2
Logic Input High Side Gate Driver - Phase V
23
HIN3
Logic Input High Side Gate Driver - Phase W
24
LIN1
Logic Input Low Side Gate Driver - Phase U
25
LIN2
Logic Input Low Side Gate Driver - Phase V
26
LIN3
Logic Input Low Side Gate Driver - Phase W
27
TH
Thermistor output
28
VDD
+15 V Main Supply
29
VSS
Negative Main Supply
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4
STK554U362A-E
Equivalent Block Diagram
VB3( 1)
W,VS3( 2)
VB2( 5)
V,VS2( 6)
VB1( 9)
U,VS1(10)
V+ (13)
DB
DB
DB
U.V.
U.V.
U.V.
U- (17)
V- (19)
W- (21)
Level
Level
Level
Shifter
Shifter
Shifter
HIN1(20)
HIN2(22)
HIN3(23)
Logic
Logic
Logic
LIN1(24)
LIN2(25)
LIN3(26)
Thermistor
TH(27)
ITRIP(16)
Shutdown
VDD(28)
VSS(29)
Enable/Disable
Under voltage
+
Detect
-
S
Timer
Q
R
Vref
Latch time about 1.65ms
FLTEN(18)
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5
STK554U362A-E
Test Circuit
The tested phase : U+ shows the upper side of the U phase and U- shows the lower side of the U phase.
ICE / IR(BD)
M
N
U+
13
10
M
N
U(DB)
9
29
V+
13
6
W+
13
2
V(DB)
5
29
U10
17
V6
19
ICE
W2
21
9
M
A
VD1=15V
10
5
W(DB)
1
29
VD2=15V
6
VCE
1
VD3=15V
2
28
VD4=15V
29
N
Fig.1
VCE(sat) (Test by pulse)
M
N
m
U+
13
10
20
V+
13
6
22
W+
13
2
23
U10
17
24
V6
19
25
9
W2
21
26
M
VD1=15V
10
5
VD2=15V
6
V
Ic
1
VD3=15V
VCE(sat)
2
28
VD4=15V
5V
m
29
16
N
Fig.2
VF (Test by pulse)
M
N
U+
13
10
V+
13
6
W+
13
2
U10
17
V6
19
M
W2
21
V
N
Fig.3
ID
M
N
VD1
9
10
VD2
5
6
VD3
1
2
VD4
28
29
ID
A
M
VD*
N
Fig.4
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6
VF
IF
STK554U362A-E
Switching time (The circuit is a representative example of the lower side U phase.)
9
Input signal
(0 to 5 V)
13
VD1=15V
10
5
VD2=15V
6
90%
Io
10
1
Vcc
CS
VD3=15V
2
28
10%
tON
VD4=15V
tOFF
Input signal
Io
24
29
16
Fig.5
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7
17
STK554U362A-E
Input / Output Timing Chart
VBS undervoltage protection reset signal
ON
HIN1,2,3
OFF
LIN1,2,3
*2
VDD
VDD undervoltage protection reset voltage
*3
VBS undervoltage protection reset voltage
VB1,2,3
VIT≥0.54V
*4
ITRIP terminal
Voltage
VIT