82P33913-1NLG

Synchronization System for IEEE 1588 82P33913 / 82P33913-1 Datasheet Description Features The IEEE 1588-2008 Precision Time Protocol (PTP) is a packet-based synchronization mechanism used in packet-switched networks. PTP synchronizes the clocks of different devices with the most accurate clock on the network – usually a precise, grandmaster clock such as one using a Primary Reference Time Clock (PRTC) time signal. ▪ System implements ITU-T telecom profiles ▪ Composed of Renesas’ IEEE 1588 software and Renesas’ Synchronization Management Unit (SMU) hardware ▪ Operates as IEEE 1588 / PTP slave ▪ Recovers accurate and stable synchronization signals from packet based IEEE 1588 / PTP master ▪ Provides integrated physical layer frequency support ▪ Operates as an IEEE 1588 / PTP master The 82P33913-x is a software and hardware system that can operate as a PTP slave or PTP master. As a PTP slave, the 82P33913-x recovers accurate and stable electrical synchronization signals from a packet-based reference generated by a PTP master. As a PTP master, the 82P33913-x can lock to a stable electrical clock source and generate packet based PTP references for downstream PTP slaves. Software ▪ C99 source code distribution, supporting POSIX-based Operating Systems (OSs) such as Linux ▪ IEEE 1588 compliant Precision Time Protocol (PTP) stack ▪ Abstraction interface supports user-supplied IEEE 1588 compliant Precision Time Protocol (PTP) stack ▪ Reference trackers filter packet synchronization noise from IEEE 1588 unaware networks The 82P33913-x is available with the two software options listed in Table 1. Table 1. Software Options by Part Number Part Number Included Software 82P33913 Renesas Clock Recovery Servo Software 82P33913-1 Renesas Clock Recovery Servo Software IEEE 1588 Protocol Stack Hardware ▪ Synchronization Management Unit (SMU) provides tools to manage physical layer and packet based synchronous clocks for IEEE 1588 Telecom Profile applications ▪ Supports independent IEEE 1588 and Synchronous Ethernet (SyncE) timing paths ▪ Combo mode provides SyncE physical layer frequency support for IEEE 1588 Telecom Boundary Clocks (T-BC) and Telecom Time Slave Clocks (T-TSC) per G.8273.2 ▪ Digital PLLs can be configured as Digitally Controlled Oscillators (DCOs) for IEEE 1588 clock synthesis ▪ Generates G.8262 and G.8262.1 compliant SyncE clocks ▪ Fractional-N input dividers support a wide range of reference frequencies ▪ Locks to 1 pulse per second (PPS) references from GPS based sources ▪ Loads configuration from an external EPROM after reset Typical Applications ▪ ▪ ▪ ▪ ▪ ▪ Access routers, edge routers, core routers Carrier Ethernet switches Multiservice access platforms PON OLT LTE eNodeB ITU-T G.8265.1 and G.8275.1 Telecom Profile clock synthesizer ▪ ▪ ▪ ▪ ▪ ITU-T G.8273.2 Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) ITU-T G.8264 Synchronous Equipment Timing Source (SETS) ITU-T G.8263 Packet-based Equipment Clock (PEC) ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC) and G.8262.1 Enhanced Synchronous Ethernet Equipment Clock (eEEC) ▪ ITU-T G.813 Synchronous Equipment Clock (SEC) ▪ Telcordia GR-253-CORE Stratum 3 Clock (S3) and SONET Minimum Clock (SMC) ©2021 Renesas Electronics Corporation 1 November 18, 2021 82P33913 / 82P33913-1 Datasheet System Component Documentation The detailed characteristics of the 82P33913-x software and hardware components are described in other documents as shown in Table 2 and Table 3. Table 2. Software Documentation Software System Component Reference 82P33913-x IEEE 1588 Software Please contact Renesas Table 3. SMU Hardware Documentation Part Number Reference 82P33913 82P33913-1 82P33813 Datasheet Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website (see Ordering Information for POD links). The package information is the most current data available and is subject to change without revision of this document. Ordering Information Orderable Part Number Package Shipping Packaging Temperature 82P33913NLG 10 × 10 × 0.9 mm 72-VFQFPN Tray -40o to +85oC 82P33913NLG8 10 × 10 × 0.9 mm 72-VFQFPN Tape & Reel, Pin 1 Orientation: EIA-481-C -40 o to +85oC 82P33913NLG/W 10 × 10 × 0.9 mm 72-VFQFPN Tape & Reel, Pin 1 Orientation: EIA-481-D -40o to +85oC 82P33913-1NLG 10 × 10 × 0.9 mm 72-VFQFPN Tray -40o to +85oC 82P33913-1NLG8 10 × 10 × 0.9 mm 72-VFQFPN Tape & Reel, Pin 1 Orientation: EIA-481-C -40o to +85oC 82P33913-1NLG/W 10 × 10 × 0.9 mm 72-VFQFPN Tape & Reel, Pin 1 Orientation: EIA-481-D -40 o to +85oC ©2021 Renesas Electronics Corporation 2 November 18, 2021 82P33913 / 82P33913-1 Datasheet Table 4. Pin 1 Orientation in Tape and Reel Packaging Part Number Suffix Pin 1 Orientation Illustration Correct Pin 1 ORIENTATION NLG8 BAG8 CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 1 (EIA-481-C) USER DIRECTION OF FEED Correct Pin 1 ORIENTATION NLG/W CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 2 (EIA-481-D) USER DIRECTION OF FEED Revision History Revision Date Description of Change November 18, 2021 ▪ Added “G.8262.1” information to ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC) bullet in Typical Applications and Features/Hardware sections on front page. ▪ Added Package Outline Drawings section. December 5, 2017 Initial release of stand-alone 82P33913 / 82P33913-1 Datasheet. ©2021 Renesas Electronics Corporation 3 November 18, 2021 72-VFQFPN, Package Outline Drawing 10.0 x 10.0 x 0.90 mm Body, Epad 7.50 x 7.50 mm 0.50mm Pitch NLG72P2, PSC-4208-02, Rev 01, Page 1 © Integrated Device Technology, Inc. 72-VFQFPN, Package Outline Drawing 10.0 x 10.0 x 0.90 mm Body, Epad 7.50 x 7.50 mm 0.50mm Pitch NLG72P2, PSC-4208-02, Rev 01, Page 2 Package Revision History Date Created © Integrated Device Technology, Inc. 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