840272AGILF

Synchronous Ethernet Frequency Translator ICS840272I DATA SHEET General Description Features The ICS840272I is a PLL-based Frequency Translator intended for use in Synchronous Ethernet applications. This high performance device is optimized to generate 25MHz and 8kHz LVCMOS clock outputs. The ICS840272I accepts the following differential or single-ended input signals: 161.1328125MHz (10GbE Mode), 156.25MHz (1GbE Mode), or 125MHz (Recovered clock from 10/100/1000BaseT Ethernet PHY). The extended temperature range supports telecommunication and networking end equipment requirements. • Two single-ended outputs (LVCMOS or LVTTL levels), output impedance: 17 • • • Single-ended lock detect output (LVCMOS or LVTTL levels) Pin Assignment VDD LOCK_DT REF_SEL SEL0 SEL1 OE VDDA GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDO QA QB GND CLK0 nCLK0 CLK1 nCLK1 Two selectable differential clock inputs Differential input pair (CLKx, nCLKx) accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels • Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels • Selectable input frequencies: 161.1328MHz, 156.25MHz or 125MHz • • • • Output frequency: 25MHz, 8kHz Full 3.3V supply voltage -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) packaging ICS840272I 16-Lead TSSOP 4.40mm x 5.0mm x 0.925mm package body G Package Top View Block Diagram LOCK_DT CLK0 0 Pulldown nCLK0 Pullup/Pulldown 0 P CLK1 Pulldown Pullup/Pulldown N PLL QA 25MHz 1 1 nCLK1 QB 8kHz REF_SEL Pulldown M Input Control SEL[1:0] Pulldown:Pullup 00 = PLL Bypass, 25MHz Input 01 = 161.1328125MHz (default) 10 = 156.25MHz 11 = 125MHz OE Pulldown ICS840272I REVISION A 06/19/14 1 ©2014 Integrated Device Technology, Inc. ICS840272I DATA SHEET Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1 VDD Power Core supply pin. 2 LOCK_DT Output Lock detect. Logic HIGH when PLL is locked. 3 REF_SEL Input Pulldown 4 SEL0 Input Pullup Selects the input reference frequency and the PLL bypass mode. See Table 3A. LVCMOS/LVTTL interface levels. 5 SEL1 Input Pulldown Selects the input reference frequency and the PLL bypass mode. See Table 3A. LVCMOS/LVTTL interface levels. 6 OE Input Pulldown 8kHz output enable pin. When LOW, QB is disabled. When HIGH, QB is enabled. LVCMOS/LVTTL interface levels. See Table 3B. 7 VDDA Power Analog supply pin. 8 GND Power Power supply ground. 9 nCLK1 Input Pullup/ Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. 10 CLK1 Input Pulldown Non-inverting differential clock input. 11 nCLK0 Input Pullup/ Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. 12 CLK0 Input Pulldown Non-inverting differential clock input. 13 GND Power Power supply ground. 14 QB Output Single-ended clock output. LVCMOS/LVTTL interface levels. 15 QA Output Single-ended clock output. LVCMOS/LVTTL interface levels. 16 VDDO Power Output supply pin. Selects the input reference clock. When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1, nCLK1. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ROUT Output Impedance 17  SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR Test Conditions VDDO = 3.465V 2 Minimum Typical Maximum Units REVISION A 06/19/14 ICS840272I DATA SHEET Function Tables Table 3A. SEL[1:0] Function Table Inputs Function Output (MHz) SEL1 SEL0 CLKx, nCLKx (MHz) Mode QA 0 0 25 PLL Bypass 25 0 (default) 1 (default) 161.1328125 PLL Enabled 25 1 0 156.25 PLL Enabled 25 1 1 125 PLL Enabled 25 Table 3B. OE Function Table Control Input Function OE QB Output 0 (default) Disabled (High impedance) 1 Enabled REVISION A 06/19/14 3 SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR ICS840272I DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 81.2C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.11 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 57 mA IDDA Analog Supply Current 11 mA IDDO Output Supply Current 5 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C Symbol Parameter VIH VIL IIH IIL Test Conditions Minimum Input High Voltage VDD = 3.465V 2 VDD + 0.3 V Input Low Voltage VDD = 3.465V -0.3 0.8 V Input High Current Input Low Current Typical OE, SEL1, REF_SEL VDD = VIN = 3.465V 150 µA SEL0 VDD = VIN = 3.465V 5 µA OE, SEL1, REF_SEL VDD = 3.465V, VIN = 0V -5 µA SEL0 VDD = 3.465V, VIN = 0V -150 µA 2.6 V VOH Output High Voltage IOH = -12mA VOL Output Low Voltage IOL = 12mA SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 4 0.5 V REVISION A 06/19/14 ICS840272I DATA SHEET Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units 150 µA CLK[0:1], nCLK[0:1] VDD = VIN = 3.465V CLK[0:1] VDD = 3.465V, VIN = 0V -5 µA nCLK[0:1] VDD = 3.465V, VIN = 0V -150 µA 0.15 1.3 V GND + 0.5 VDD – 0.85 V Maximum Units NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. AC Electrical Characteristics Table 5. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C Symbol Parameter Test Conditions fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 QA 25MHz, Integration Range: 12kHz – 10MHz tjit(cc) Cycle-to-Cycle Jitter QA 25MHz QA 20% to 80% tR / tF Output Rise/Fall Time QB 20% to 80% odc Output Duty Cycle Minimum Typical QA 25 MHz QB 8 kHz 1.1 ps 37 ps 450 1100 ps 450 1100 ps QA 47 53 % QB 47 53 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise plot. REVISION A 06/19/14 5 SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR ICS840272I DATA SHEET Typical Phase Noise at 25MHz Noise Power (dBc/Hz) Additive Phase Jitter @ 25MHz 12kHz to 10MHz = 1.1ps (typical) Offset Frequency (Hz) SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 6 REVISION A 06/19/14 ICS840272I DATA SHEET Parameter Measurement Information 1.65V±5% 1.65V±5% VDD SCOPE VDD, VDDO nCLK[0:1] VDDA Qx V V Cross Points PP CMR CLK[0:1] GND GND -1.65V±5% LVCMOS Output Load AC Test Circuit Differential Input Level V DDO 2 QA, QB 80% 80% t PW t PERIOD 20% 20% QA, QB odc = t PW tR tF x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time V V DDORx DDORx 2 tcycle n ➤ QA, QB V DDORx 2 ➤ 2 tcycle n+1 ➤ ➤ tjit(cc) = tcycle n – tcycle n+1 1000 Cycles RMS Phase Jitter REVISION A 06/19/14 Cycle-to-Cycle Jitter 7 SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR ICS840272I DATA SHEET Applications Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS840272I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVCMOS Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVCMOS output can be left floating. There should be no trace attached. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 8 REVISION A 06/19/14 ICS840272I DATA SHEET Wiring the Differential Input to Accept Single-Ended Levels values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Suggested edge rate faster than 1V/ns. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels REVISION A 06/19/14 9 SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR ICS840272I DATA SHEET Differential Clock Input Interface with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figure 3A to Figure 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult 3.3V 1.8V 1.8V R3 3.3KΩ Zo = 50Ω 3.3V 3.3V 3.3V R4 6.65KΩ Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK Differential Input LVHSTL R1 50Ω IDT LVHSTL Driver R2 50Ω Differential Input LVPECL R1 50Ω R2 50Ω R3 50Ω Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver 3.3V 3.3V 127Ω Figure 3D. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V Zo = 50Ω 120Ω 3.3V R2 3.3KΩ CLK CLK R1 100Ω nCLK 82.5Ω Receiver LVDS 82.5Ω R3 3.3KΩ Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V nCLK Zo = 50Ω Differential Input LVPECL Figure 3E. CLK/nCLK Input Driven by a 3.3V LVDS Driver 3.3V 2.5V 2.5V 3.3V R5 3.3KΩ R3 120Ω 3.3V R4 113Ω Zo = 60Ω *R3 CLK CLK Zo = 60Ω nCLK nCLK *R4 HCSL SSTL Differential Input R1 120Ω Figure 3C. CLK/nCLK Input Driven by a 3.3V HCSL Driver SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR R2 120Ω Differential Input Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver 10 REVISION A 06/19/14 ICS840272I DATA SHEET Schematic Example the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 10 ohm VCCA resistor and the 0.1uf capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Pull up and pull down resistors to set configuration pins can all be placed on the pcb side opposite the device side to free up device side area if necessary. Figure 4 (next page) shows an example ICS840272I application which focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set for the application. The ICS840272I requires a variation on each of the standard LVDS and LVPECL termination networks for the input clocks. These variations introduce an input offset that ensures the LOCK_DT output stays at a stable logic low value when the input clock is either stopped or tri-stated. Notice in particular the nonstandard value of R4 in the LVPECL termination and the addition of R11 and R12 in the LVDS termination. Use these same terminations for AC coupling. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS840272I provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. For additional layout recommendations and guidelines, contact clocks@idt.com. In order to achieve the best possible filtering, it is recommended that REVISION A 06/19/14 11 SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR ICS840272I DATA SHEET Figure 4. ICS840272I Schematic Example SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 12 REVISION A 06/19/14 ICS840272I DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the ICS840272I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS840272I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD + IDDA+ IDDO) = 3.465V *(57mA + 11mA + 5mA) = 252.9mW • Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 17)] = 25.86mA • Total Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 17 * (25.86mA)2 = 11.4mW per output Total Power (ROUT) = 11.4mW * 2 = 22.8mW Total Power Dissipation • Total Power = Power (core)MAX + Total Power (ROUT) = 252.9mW + 22.8mW = 275.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 81.2°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.276W *81.2°C/W = 107.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 16-Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards REVISION A 06/19/14 0 1 2.5 81.2°C/W 73.9°C/W 70.2°C/W 13 SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR ICS840272I DATA SHEET Reliability Information Table 7. JA vs. Air Flow Table for a 16-Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 81.2°C/W 73.9°C/W 70.2°C/W Transistor Count The transistor count for ICS840272I: 3326 Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Table 8. Package Dimensions for 16-Lead TSSOP All Dimensions in Millimeters Symbol Minimum N Maximum 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 Basic 4.30 e 4.50 0.65 Basic L 0.45  0° 0.75 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 14 REVISION A 06/19/14 ICS840272I DATA SHEET Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 840272AGILF 40272AIL “Lead-Free” 16-Lead TSSOP Tube -40C to 85C 840272AGILFT 40272AIL “Lead-Free” 16-Lead TSSOP Tape & Reel -40C to 85C REVISION A 06/19/14 15 SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR ICS840272I DATA SHEET Revision History Sheet Rev A Table Page Description of Change 10 11-12 Updated Differential Clock Input Interface drawings. Updated schematic and schematic text. SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR Date 16 6/19/2014 REVISION A 06/19/14 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2014 Integrated Device Technology, Inc.. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.