843002I
FemtoClockTM Crystal-To-3.3V, 2.5V
LVPECL Frequency Synthesizer
Data Sheet
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
GENERAL DESCRIPTION
FEATURES
T h e 8 4 3 0 0 2 I i s a 2 o u t p u t LV P E C L s y n t h e s i z e r
optimized to generate Fibre Channel reference
clock frequencies and is a member of thefamily of high
performance clock solutions from IDT. Using a 26.5625MHz,
18pF parallel resonant crystal, the following frequencies
can be generated based on the 2 frequency select pins (F_
SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, and
53.125MHz. The 843002I uses IDT’s FemtoClock TM low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The 843002I is packaged in a small 20-pin TSSOP
package.
• Two 3.3V or 2.5V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @212.5MHz (2.55MHz - 20MHz):
0.50ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package
• For functional replacement part use 8T49N242
FREQUENCY SELECT FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Input Frequency
F_SEL1
F_SEL0
M Divider
Value
N Divider
Value
M/N
Divider Value
Output
Frequency
(MHz)
26.5625
0
0
24
3
8
212.5
26.5625
0
1
24
4
6
159.375
26.5625
1
0
24
6
4
106.25
26.5625
1
1
24
12
2
53.125
23.4375
0
0
24
3
8
187.5
BLOCK DIAGRAM
843002I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 7
nc
Unused
2, 20
VCCO
Power
Output supply pins.
3, 4
Q0, nQ0
Ouput
Differential output pair. LVPECL interface levels.
No connect.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing
the true outputs Qx to go low and the inverted outputs nQx to go high. When logic
Pulldown
LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface
levels.
Determines whether synthesizer is in PLL or bypass mode.
Pulldown
LVCMOS/LVTTL interface levels.
5
MR
Input
6
nPLL_SEL
Input
8
VCCA
Power
9, 11
F_SEL0,
F_SEL1
Input
10, 16
VCC
Power
Core supply pin.
12, 13
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
14
REF_CLK
Input
Pulldown LVCMOS/LVTTL reference clock input.
15
nXTAL_SEL
Input
Selects between crystal or REF_CLK inputs as the the PLL Reference source. Selects
Pulldown XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface
levels.
17
VEE
Power
Negative supply pins.
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
18, 19
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
NOTE: refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Pulldown
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
©2016 Integrated Device Technology, Inc
Test Conditions
2
Minimum
Typical
Maximum
Revision A
Units
May 26, 2016
843002I Data Sheet
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -40°C TO 85°C
Symbol
Parameter
VCC
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
2.97
3.3
3.63
V
Analog Supply Voltage
2.97
3.3
3.63
V
VCCO
Output Supply Voltage
2.97
3.3
3.63
V
IEE
Power Supply Current
130
mA
ICCA
Analog Supply Current
13
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
Test Conditions
2.375
2.5
2.625
V
VCCA
Analog Supply Voltage
2.375
2.5
2.625
V
VCCO
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
115
mA
ICCA
Analog Supply Current
12
mA
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
©2016 Integrated Device Technology, Inc
Test Conditions
Minimum
Maximum
Units
VCC = 3.3V
2
VCC + 0.3
V
VCC = 2.5V
1.7
VCC + 0.3
V
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
-0.3
0.7
V
150
µA
VCC = VIN = 3.63V or 2.625V
VCC = 3.63V or 2.625V,
VIN = 0V
3
Typical
-150
µA
Revision A
May 26, 2016
843002I Data Sheet
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Minimum
Typical
Maximum
Units
VCCO - 1.4
VCCO - 0.9
V
VCCO - 2.0
VCCO - 1.7
V
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
28.33
MHz
Equivalent Series Resistance (ESR)
23.33
26.5625
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
226.67
MHz
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2
tjit(Ø)
tR / tF
odc
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
Typical
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] =11
46.67
56.67
MHz
30
ps
212.5MHz, (2.55MHz - 20MHz)
0.50
ps
159.375MHz, (1.875MHz - 20MHz)
0.54
ps
106.25MHz, (637kHz - 5MHz)
0.68
ps
53.125MHz, (637kHz - 5MHz)
0.70
ps
20% to 80%
350
650
ps
F_SEL[1:0] ≠ 00
49
51
%
F_SEL[1:0] = 00
43
57
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured using crystal input.
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
fOUT
tsk(o)
Parameter
Output Frequency
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
Units
226.67
MHz
MHz
140
170
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] =11
46.67
56.67
MHz
30
ps
Output Skew; NOTE 1, 2
RMS Phase Jitter (Random);
NOTE 3
Maximum
F_SEL[1:0] = 01
212.5MHz, (2.55MHz - 20MHz)
tjit(Ø)
Typical
0.50
ps
159.375MHz, (1.875MHz - 20MHz)
0.55
ps
106.25MHz, (637kHz - 5MHz)
0.75
ps
53.125MHz, (637kHz - 5MHz)
0.76
ps
20% to 80%
350
650
ps
F_SEL[1:0] ≠ 00
49
51
%
F_SEL[1:0] = 00
43
57
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured using crystal input.
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
TYPICAL PHASE NOISE AT 212.5MHZ @ 3.3V
0
-10
-20
-30
-40
-50
212.5MHz
➤
RMS Phase Jitter (Random)
2.55MHz to 20MHz = 0.50ps (typical)
-60
-70
-80
Fibre Channel Jitter Filter
-120
-130
-140
-150
➤
NOISE POWER
Raw Phase Noise Data
-100
-110
➤
dBc
Hz
-90
-160
-170
Phase Noise Result by adding
Fibre Channel Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
PROPAGATION DELAY
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 843002I provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V CC, V CCA, and
V CCO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VCCA.
3.3V
VCC
0.01µF 10Ω
VCCA
0.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
REF_CLK INPUT
For applications not requiring the use of the reference clock, it can
be left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the REF_CLK to ground.
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
CRYSTAL INPUT INTERFACE
The 843002I has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were de-
termined using a 26.5625MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
FIGURE 2. CRYSTAL INPUT INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS signals, it
is recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be done
in one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and
R2 can be 100Ω. This can also be accomplished by removing R1
and making R2 50Ω. By overdriving the crystal oscillator, the device
will be functional, but note the device performance is guaranteed
by using a quartz crystal.
VDD
VDD
R1
Ro
Rs
.1uf
Zo = 50
Zo = Ro + Rs
XTAL_IN
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
TERMINATION FOR 3.3V LVPECL OUTPUTS
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
FIGURE 4A. LVPECL OUTPUT TERMINATION
©2016 Integrated Device Technology, Inc
R2
84
FIGURE 4B. LVPECL OUTPUT TERMINATION
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843002I Data Sheet
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination is
shown in Figure 5C.
2.5V
2.5V
VCCO=2.5V
Zo = 50 Ohm
R1
250
2.5V
VCCO=2.5V
R3
250
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R2
62.5
2,5V LVPECL
Driv er
R4
62.5
R1
50
R2
50
R3
18
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
LAYOUT GUIDELINE
crystal is used. The C1=27pF and C2=33pF are recommended for
frequency accuracy. For different board layout, the C1 and C2 may
be slightly adjusted for optimizing frequency accuracy.
Figure 6A shows a schematic example of the 843002I. An example of
LVEPCL termination is shown in this schematic. Additional LVPECL
termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18pF parallel resonant 26.5625MHz
3.3V
VCC
VCCA
R2
10
C3
10uF
C4
0.01u
Zo = 50 Ohm
VCCO
RD1
Not Install
10
9
8
7
6
5
4
3
2
1
-
R4
82.5
ICS843002i
R6
82.5
VCC=3.3V
F_SEL1
XTAL_OUT
XTAL_IN
REF_CLK
nXTAL_SEL
VCC
VEE
nQ1
Q1
VCCO
RU2
Not Install
To Logic
Input
pins
Zo = 50 Ohm
U1
To Logic
Input
pins
VCCO=3.3V
Zo = 50 Ohm
+
11
12
13
14
15
16
17
18
19
20
RU1
1K
Set Logic
Input to
'0'
VCC
C7
0.1u
VCC
F_SEL0
VCCA
nc
nPLL_SEL
MR
nQ0
Q0
VCCO
nc
Set Logic
Input to
'1'
VCC
R5
133
+
VCC
C6
0.1u
Logic Control Input Examples
R3
133
RD2
1K
Zo = 50 Ohm
VCCO
C8
0.1u
R7
50
C2
33pF
X1
26.5625MHz
18pF
R8
50
VCC
ICS843002I
C1
27pF
R9
50
C9
0.1u
Optional Termination
FIGURE 6A. 843002I SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 6B shows an example of 843002I P.C. board layout. The
crystal X1 footprint shown in this example allows installation of either
surface mount HC49S or through-hole HC49 package. The footprints
of other components in this example are listed in the Table 6. There
should be at least one decoupling capacitor per power pin. The
decoupling capacitors should be located as close as possible to the
power pins. The layout assumes that the board has clean analog
power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5, C6, C7, C8
0603
R2
0603
NOTE: Table 6, lists component sizes
shown in this layout example.
FIGURE 6B. 843002I PC BOARD LAYOUT EXAMPLE
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 843002I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843002I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 130mA = 471.9mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.63V, with all outputs switching) = 471.9mW + 60mW = 531.9mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature for HiPerClockSTM devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.532W * 66.6°C/W = 120.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 7.
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCCO– 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX– VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
©2016 Integrated Device Technology, Inc
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843002I Data Sheet
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 843002I is: 2578
PACKAGE OUTLINE AND DIMENSIONS
TABLE 9. PACKAGE DIMENSIONS
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
Millimeters
SYMBOL
MIN
N
MAX
20
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
E
E1
6.60
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
©2016 Integrated Device Technology, Inc
15
Revision A
May 26, 2016
843002I Data Sheet
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
843002AGILF
ICS843002AIL
20 lead “Lead Free” TSSOP
Tube
-40°C to +85°C
843002AGILFT
ICS843002AIL
20 lead “Lead Free” TSSOP
Tape and Reel
-40°C to +85°C
©2016 Integrated Device Technology, Inc
16
Revision A
May 26, 2016
843002I Data Sheet
REVISION HISTORY SHEET
Rev
Table
Page
A
T10
9
16
1
8
13
16
A
T10
T10
A
A
1
1
16
Description of Change
Date
Changed the format of the datasheet to the new IDT header/footer.
Added LVCMOS to Crystal Interface section.
Ordering Information Table - corrected Lead-Free marking.
Correctly positioned “pulldown” labels of block diagram.
Removed last sentence in paragraph of Power Supply Filtering Techniques.
Updated first paragraph under Junction Temperature.
Ordering information - removed the F marking for the LF part number.
Removed ICS from part numbers were needed.
General Description - removed Hiperclocks Chip and Hiperclocks name.
Features Section - removed reference to lead free part.
Ordering Information - removed quantity in tape and reel and removed LF note below the
table.
Updated data sheet header and footer.
Product Discontinuation Notice - Last time buy expires May 6, 2017.
PDN CQ-16-01
©2016 Integrated Device Technology, Inc
17
Revision A
6/24/09
9/11/09
1/15/16
5/26/16
May 26, 2016
843002I Data Sheet
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