843021AG-01T

FemtoClock® Crystal-to-3.3V LVPECL Clock Generator 843021 DATA SHEET General Description Features The 843021 is a Gigabit Ethernet Clock Generator. The ICS84302 uses a 25MHz crystal to synthesize 125MHz. The 843021has excellent phase jitter performance, over the 1.875MHz – 20MHz integration range. The 843021is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • • One differential 3.3V LVPECL output • • • • Output frequency range: 112MHz – 140MHz Crystal oscillator interface designed for 22.4MHz – 28MHz, 18pF parallel resonant crystal VCO range: 560MHz – 700MHz Output duty cycle range: 49% – 51% RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.650ps (typical) Offset Noise Power 100Hz ..............-94.2 dBc/Hz 1kHz ..............-122.8 dBc/Hz 10kHz ..............-132.2 dBc/Hz 100kHz ..............-131.3 dBc/Hz • • • • Full 3.3V supply mode 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package Industrial temperature information available upon request Table 1. Frequency Table - Typical Applications Inputs Crystal Frequency (MHz) Output Frequency Range (MHz) 25 125 26.6 133 Block Diagram Pin Assignment 25MHz XTAL_IN OSC XTAL_OUT Phase Detector VCO ÷5 Q0 nQ0 1 2 3 4 8 7 6 5 VCC Q0 nQ0 nc 843021 8 Lead TSSOP 4.40mm x 3.0mm x 0.925 package body G Package Top View ÷25 (fixed) 843021 REVISION D 9/25/15 VCCA VEE XTAL_OUT XTAL_IN 1 ©2015 Integrated Device Technology, Inc. 843021 DATA SHEET Table 2. Pin Descriptions Number Name 1 VCCA Unused Type Description 2 VEE Power Negative supply pin. 3, 4 XTAL_OUT XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Analog supply pin. 5 nc Unused No connect. 6, 7 nQ0, Q0 Output Differential output pair. LVPECL interface levels. 8 VCC Power Core supply pin. Table 3. Pin Characteristics Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum Units 4 pF Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 10%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Core Supply Voltage 2.97 3.3 3.63 V VCCA Analog Supply Voltage 2.97 3.3 3.63 V IEE Power Supply Current 85 mA FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 2 Rev D 9/25/15 843021 DATA SHEET Table 4B. LVPECL DC Characteristics, VCC = 3.3V ±10%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCC – 1.4 VCC – 0.9 V VCC – 2.0 VCC – 1.7 V 0.6 1.0 V NOTE 1: Outputs termination with 50 to VCC – 2V. Table 5. Crystal Characteristics Parameter Test Conditions Minimum Maximum Units 40 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF Mode of Oscillation Typical Fundamental Frequency; NOTE 1 14 NOTE 1:Input frequency is limited to a range of 22.4MHz – 28MHz due to VCO range. AC Electrical Characteristics Table 6. AC Characteristics, VCC = 3.3V ± 10%, VEE = 0V, TA = 0°C to 70° Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units 140 MHz 0.65 ps 250 550 ps 49 51 % 112 125MHz, Integration Range: 1.875MHz – 20MHz 20% to 80% 0.37 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plot. FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 3 Rev D 9/25/15 843021 DATA SHEET Typical Phase Noise at 125MHz -10 ➝ 0 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps (typical) -20 10Gb Ethernet Filter -30 -40 -50 -70 -80 -90 -100 -110 ➝ Noise Power dBc Hz -60 -120 Raw Phase Noise Data -130 -140 ➝ -150 -160 Phase Noise Result by adding a 10Gb Ethernet filter to raw data -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz) FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 4 Rev D 9/25/15 843021 DATA SHEET Parameter Measurement Information 2V VCC, Q Noise Power Phase Noise Plot SCOPE VCCA Phase Noise Mask LVPECL nQ VEE f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.3V±0.33V 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter nQ0 nQ0 Q0 Q0 Output Duty Cycle/Pulse Width/Period FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Output Rise/Fall Time 5 Rev D 9/25/15 843021 DATA SHEET Applications Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 843021 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. Figure 1. Power Supply Filtering Crystal Input Interface The 843021 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 33pF X1 18pF Parallel Crystal XTAL_OUT C2 27pF Figure 2. Crystal Input Interface FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 6 Rev D 9/25/15 843021 DATA SHEET Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. 3.3V 3.3V R1 100 Ro ~ 7 Ohm C1 Zo = 50 Ohm XTAL_IN RS 43 R2 100 Driv er_LVCMOS 0.1uF XTAL_OUT Cry stal Input Interf ace Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V C1 Zo = 50 Ohm XTAL_IN R1 50 Zo = 50 Ohm 0.1uF XTAL_OUT LVPECL Cry stal Input Interf ace R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 7 Rev D 9/25/15 843021 DATA SHEET Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 4A. 3.3V LVPECL Output Termination FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR R2 84 Figure 4B. 3.3V LVPECL Output Termination 8 Rev D 9/25/15 843021 DATA SHEET Schematic Example Figure 5A shows a schematic example of using an 843021. An example of LVPECL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18pF parallel resonant crystal is used for generating 125MHz output frequency. TheC1 = 27pF and C2 = 33pF are recommended for frequency accuracy. For a different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. Figure 5. 843021 Schematic Example Schematic Example Figure 5B shows an example of 843021 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 7 There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. Table 7. Footprint Table Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R2 0603 NOTE: Table 7 lists component sizes shown in this layout example. Figure 5B. 843021 PC Board Layout Example FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 9 Rev D 9/25/15 843021 DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the 843021. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843021 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 85mA = 308.6mW • Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.63V, with all outputs switching) = 308.6mW + 30mW = 338.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 90.5°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.339W * 90.5°C/W = 100.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 8. Thermal Resitance JA for 8 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W 10 Rev D 9/25/15 843021 DATA SHEET 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 11 Rev D 9/25/15 843021 DATA SHEET Reliability Information Table 9. JA vs. Air Flow Table for a 8 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W Transistor Count The transistor count for 843021 is: 1928 Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Table 10. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 12 Rev D 9/25/15 843021 DATA SHEET Ordering Information Table 11. Ordering Information Part/Order Number 843021AGLF 843021AGLFT Marking 021AL 021AL Package “Lead-Free” 8 Lead TSSOP “Lead-Free” 8 Lead TSSOP Shipping Packaging Tube Tape & Reel Temperature 0C to 70C 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 13 Rev D 9/25/15 843021 DATA SHEET Revision History Sheet Rev Table Page 1 B B C C C Date Added Function Table. Features section - updated Crystal, Output Frequency & VCO range bullets. Crystal Characteristics Table - changed Frequency from 25MHz typical to 14MHz min. and 40MHz max. Added Note 1. AC Characteristics Table - changed Output Frequency from 125MHz typical to 112MHz min. and 140MHz max. 10/6/04 T5 3 T6 4 T11 12 Ordering Information Table - corrected count from 154 per tube to 100 10/15/04 T4A 3 Power Supply Table - increased VCC to 3.3V ± 10% from 5% and is reflected throughout the datasheet. 11/3/04 T8 T9 T11 3 9 11 12 Absolute Maximum Ratings - corrected Package Thermal Impedance air flow. Thermal Resistance Table - corrected air flow. Corrected air flow in table. Ordering Information Table - corrected marking. 11/30/04 T11 1 12 Features Section - added Lead-Free bullet. Ordering Information Table - added Lead-Free part number. 3/31/05 1 4 7 7 Features section - changed RMS phase jitter spec. AC Characteristics Table - added maximum RMS Phase Jitter spec of 0.65ps. Added LVCMOS to XTAL Interface section. Added Termination for 3.3V LVPECL Output section. Updated datasheet to new format. 11/21/07 T4B 3 T6 10/12/10 T11 3 6 7 13 LVPECL DC Characteristics Table - corrected VOH/VOL parameters from “Current” to “Voltage” and units from “uA” to “V”. AC Characteristics Table - added thermal note. Updated text in “Power Supply Filtering Techniques”. Updated “Overdriving the Crystal Interface” section. Ordering Information Table - deleted “ICS” prefix for part/order column. Updated header/footer. T11 13 Ordering Information - removed leaded devices. Updated data sheet format. 9/25/15 T6 D D D Description of Change FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 14 Rev D 9/25/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. 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