ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JULY 31, 2015
GENERAL DESCRIPTION
FEATURES
• Dual differential 3.3V LVPECL outputs
The ICS8432-111 is a general purpose, dual output
Differential-to-3.3V LVPECL High Frequency Synthesizer.
The ICS8432-111 has a selectable differential CLK, nCLK
pair or LVCMOS/LVTTL TEST_CLK. The TEST_CLK input
accepts LVCMOS or LVTTL input levels and translates them
to 3.3V LVPECL levels. The CLK, nCLK pair can accept most
standard differential input levels.The VCO operates at a
frequency range of 200MHz to 700MHz. The VCO frequency is
programmed in steps equal to the value of the input differential
or single ended reference frequency. Output frequencies up to
700MHz for FOUT and 350MHz for FOUT/2 can be programmed
using the serial or parallel interfaces to the configuration logic.
The low phase noise characteristics and the multiple frequency
outputs of the ICS8432-111 makes it an ideal clock source for
Fibre Channel 1 and 2, and Infiniband applications.
• Selectable differential CLK, nCLK pair or LVCMOS TEST_
CLK
• CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• TEST_CLK can accept the following input types:
LVCMOS or LVTTL
• Maximum FOUT frequency: 700MHz
Maximum FOUT/2 frequency: 350MHz
• CLK, nCLK or TEST_CLK input frequency: 40MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter
and VCO frequency multiplier and dividers
• RMS period jitter: 5ps (maximum)
• Cycle-to-cycle jitter: 40ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For functional replacement device use 8432DY-101LF
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL
MR
VCO
÷M
0
1
÷1
÷2
÷4
÷8
CLK
23
TEST_CLK
M7
3
22
CLK_SEL
M8
4
21
VCCA
N0
5
20
S_LOAD
N1
6
19
S_DATA
nc
7
18
S_CLOCK
VEE
8
17
MR
ICS8432-111
9 10 11 12 13 14 15 16
VEE
nFOUT
FOUT
VCCO
nFOUT/2
TEST
24
2
FOUT/2
CONFIGURATION
INTERFACE
LOGIC
1
M6
VCC
÷2
M5
TEST
FOUT
nFOUT
FOUT/2
nFOUT/2
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
M0:M8
N0:N1
8432CY-111
nCLK
32 31 30 29 28 27 26 25
PHASE DETECTOR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
nP_LOAD
1
M0
CLK
nCLK
M1
0
M2
TEST_CLK
M3
M4
CLK_SEL
VCO_SEL
VCO_SEL
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1
REV. C SEPTEMBER 11, 2014
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
event occurs. As a result, the M and N bits can be hardwired
to set the M divider and N output divider to a specific default
state that will automatically occur during power-up. The TEST
output is LOW when operating in the parallel input mode. The
relationship between the VCO frequency, the input frequency
and the M divider is defined as follows: fVCO = fIN x M
NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values for
different input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The ICS8432-111 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A differential clock input is used as the input to the
ICS8432-111. This input is fed into the phase detector. A 25MHz
clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. When the input clock is at 25MHz, the valid M values for
which the PLL will achieve lock are defined as 10 ≤ M ≤ 28. The
frequency out is defined as follows: fOUT = fVCO = fIN x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N
output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA
input is passed directly to the M divider and N output divider on
each rising edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output as
follows:
T1 T0
TEST Output
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note, that for some values of M (either
too high or too low), the PLL will not achieve lock. The output
of the VCO is scaled by a divider prior to being sent to each of
the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8432-111 support two
input modes to program the PLL M divider and N output divider.
The two input operational modes are parallel and serial. Figure1
shows the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout/2
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE:
8432CY-111
The NULL timing slot must be observed.
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2
REV. C SEPTEMBER 11, 2014
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
2, 3, 4,
28, 29,
30, 31, 32
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
Input
Type
Input
M counter/divider inputs. Data latched on LOW-to-HIGH transistion
Pulldown of nP_LOAD input. LVCMOS/LVTTL interface levels.
5, 6
N0, N1
Input
Pulldown
7
nc
Unused
8, 16
VEE
Power
9
TEST
Output
10
11,
12
13
VCC
Power
Description
Pullup
Determines output divider value as defined in Table 3C
Function Table. LVCMOS/LVTTL interface levels.
No connect.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
Half frequency differential output for the synthesizer.
3.3V LVPECL interface levels.
Output supply pin.
FOUT/2, nFOUT/2 Output
VCCO
Power
14, 15
FOUT, nFOUT
Output
17
MR
Input
Pulldown
18
S_CLOCK
Input
Pulldown
19
S_DATA
Input
Pulldown
20
S_LOAD
Input
Pulldown
21
VCCA
Power
22
CLK_SEL
Input
Pullup
23
TEST_CLK
Input
Pulldown
24
CLK
Input
Pulldown Non-inverting differential clock input.
25
nCLK
Input
26
nP_LOAD
Input
27
VCO_SEL
Input
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
outputs nFOUTx to go high. When logic LOW, the internal dividers are
the outputs are enabled. Assertion of MR does not effect loaded
M, N, and T values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels.
Analog supply pin.
Selects between differential clock input or test input as the PLL reference source. LVCMOS/LVTTL interface levels. Selects CLK, nCLK
inputs when HIGH. Selects TEST_CLK when LOW.
Test clock input. LVCMOS/LVTTL interface levels.
Pullup
Inverting differential clock input.
Parallel load input. Determines when data present at M8:M0 is loaded
Pulldown into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
RPULLUP
Input Pullup Resistor
51
kW
RPULLDOWN
Input Pulldown Resistor
51
kW
8432CY-111
Test Conditions
Minimum
Typical
4
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3
Maximum
Units
pF
REV. C SEPTEMBER 11, 2014
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
L
↑
Data
Data
L
X
X
L
H
X
X
L
↑
Data
L
H
X
X
↑
L
Data
L
H
X
X
↓
L
Data
M divider and N output divider values are latched.
L
H
X
X
L
X
X
Parallel or serial input do not affect shift registers.
L
H
X
X
H
↑
Data
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
S_DATA passed directly to ripple counter as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑= Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
10
0
0
0
0
0
1
0
1
0
11
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
26
0
0
0
0
1
1
0
1
0
675
27
0
0
0
0
1
1
0
1
1
VCO Frequency
(MHz)
M Count
250
275
700
28
0
0
0
0
1
1
1
0
0
NOTE 1: These M count values and the resulting frequencies correspond to differential input or TEST_CLK input frequency of
25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Output Frequency (MHz)
Inputs
N Divider Value
N1
N0
0
0
1
0
1
1
0
1
1
8432CY-111
FOUT
FOUT/2
Minimum
Maximum
Minimum
Maximum
250
700
2
125
350
62.5
175
4
62.5
175
31.25
87.5
8
31.25
87.5
15.625
43.75
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4
125
350
REV. C SEPTEMBER 11, 2014
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5 V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
140
mA
ICCA
Analog Supply Current
15
mA
Maximum
Units
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VIH
VIL
Parameter
Input
High Voltage
Input
Low Voltage
Test Conditions
Minimum
Typical
VCO_SEL, CLK_SEL, S_LOAD,
S_DATA, S_CLOCK, nP_LOAD,
N0:N1, M0:M8, MR
2
VCC + 0.3
V
TEST_CLK
2
VCC + 0.3
V
-0.3
0.8
V
1.3
V
VCO_SEL, CLK_SEL, S_LOAD,
S_DATA, S_CLOCK, nP_LOAD,
N0:N1, M0:M8, MR
TEST_CLK
IIH
IIL
Input
High Current
Input
Low Current
M0-M4, M6-M8, N0, N1, S_
CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD, MR
VCC = VIN = 3.465V
150
µA
M5, CLK_SEL, VCO_SEL
VCC = VIN = 3.465V
5
µA
M0-M4, M6-M8, N0, N1, S_
CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD, MR
VCC = 3.465V,
VIN = 0V
-5
µA
M5, CLK_SEL, VCO_SEL
VCC = 3.465V,
VIN = 0V
-150
µA
2.6
V
VOH
Output
High Voltage
TEST; NOTE 1
VOL
Output
Low Voltage
TEST; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VCCO/2. See Parameter Information, 3.3V Output Load Test Circuit.
8432CY-111
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5
REV. C SEPTEMBER 11, 2014
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
Minimum
Typical
Maximum
Units
CLK
VCC = VIN = 3.465V
150
µA
nCLK
VCC = VIN = 3.465V
5
µA
CLK
VCC = 3.465V, VIN = 0V
-5
µA
nCLK
VCC = 3.465V, VIN = 0V
-150
µA
0.15
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
1.3
V
VCC - 0.85
V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50 W to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fIN
Input Frequency
Test Conditions
Minimum
Typical
Maximum
Units
TEST_CLK; NOTE 1
10
40
MHz
CLK, nCLK; NOTE 1
10
40
MHz
S_CLOCK
50
MHz
NOTE 1: For the input frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range.
Using the minimum input frequency of 10MHz, valid values of M are 25 ≤ M ≤ 70. Using the maximum frequency
of 40MHz, valid values of M are 7 ≤ M ≤ 17.
8432CY-111
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REV. C SEPTEMBER 11, 2014
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
FOUT
Output Frequency
31.25
700
MHz
FOUT/2
Output Frequency
15.625
350
MHz
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 2
40
ps
tjit(per)
Period Jitter, RMS; NOTE 2
tsk(o)
Output Skew; NOTE 1, 2
tR / tF
Output Rise/Fall Time
tS
Setup Time
fOUT > 100
20% to 80%
200
ps
ps
700
ps
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
tH
Hold Time
odc
Output Duty Cycle
tPW
Output Pulse Width
S_CLOCK to S_LOAD
fOUT/2; fOUT, N > 1
5
ns
47
53
%
tPeriod/2 - 150
tPeriod/2 + 150
ps
1
ms
tLOCK
PLL Lock Time
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
8432CY-111
5
60
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REV. C SEPTEMBER 11, 2014
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
DIFFERENTIAL INPUT LEVEL
3.3V OUTPUT LOAD AC TEST CIRCUIT
nFOUT,
nFOUT/2
FOUT,
FOUT/2
tcycle n
tcycle n+1
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
PERIOD JITTER
OUTPUT RISE/FALL TIME
OUPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
8432CY-111
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8
REV. C SEPTEMBER 11, 2014
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The ICS8432-111 provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. Vcc, VccA, and
VccO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VccA pin.
3.3V
Vcc
.01μF
10Ω
VccA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8432CY-111
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REV. C SEPTEMBER 11, 2014
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
FIGURE 4A. LVPECL OUTPUT TERMINATION
8432CY-111
FIGURE 4B. LVPECL OUTPUT TERMINATION
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REV. C SEPTEMBER 11, 2014
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet
the VPP and VCMR input requirements. Figures 5A to 5E show
interface examples for the CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 5A, the input termination applies for LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 5A. CLK/nCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 5B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
Zo = 50 Ohm
Zo = 50 Ohm
LVDS_Driv er
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 5C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 5E. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-111.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432-111 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 60mW = 545.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming
a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.545W * 42.1°C/W = 93°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 7. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of VCCO- 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO _MAX- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8432-111 is: 3765
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PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
MINIMUM
NOMINAL
N
MAXIMUM
32
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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TABLE 10. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT.
IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET
Rev
B
Table
Page
T4A
5
12
T4D
1
2
6
12 - 13
C
C
C
8432CY-111
T10
16
18
1
Description of Change
Date
Power Supply table - adjusted the IEE limit from 120mA max. to 140mA max.
Adjusted Power Dissipation to comply with IEE.
Features Section - added lead-free bullet.
Corrected Figure 1, Paralle & Serial Load Operations Diagram
LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO 0.9V
Power Considerations - corrected power dissipation to reflect VOH max in Table
4D.
Ordering Information Table - added lead-free part number and note.
3/3/04
4/12/07
Updated datasheet’s header/footer with IDT from ICS.
Ordering Information Table - removed ICS prefix from Part/Order Number column. Added LF marking and corrected non-LF marking.
Added Contact Page.
10/5/10
Product Discontinuation Notice - CQ-14-05
Features Section - Removed reference to leaded device and added replacement
device
9/11/14
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DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
We’ve Got Your Timing Solution.
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© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated
Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
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