ICS8432-51
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8432-51 is a general purpose, dual output
ICS
Crystal-to-3.3V Differential LVPECL High FreHiPerClockS™
quency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS8432-51 has a selectable REF_CLK or crystal input. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is
programmed in steps equal to the value of the input reference
or crystal frequency. The VCO and output frequency can be
programmed using the serial or parallel interface to the configuration logic. The low phase noise characteristics of the
ICS8432-51 make it an ideal clock source for Gigabit Ethernet,
Fibre Channel 1 and 2, and Infiniband applications.
• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_CLK
• Output frequency range: 31.25MHz to 700MHz
• Crystal input frequency range: 12MHz to 25MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter and
output dividers
• RMS period jitter: 3.5ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
• Replaces the ICS8432-01
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
32 31 30 29 28 27 26 25
VCO_SEL
XTAL_SEL
REF_CLK
0
XTAL1
OSC
1
XTAL2
PLL
M5
1
24
XTAL_OUT
M6
2
23
REF_CLK
M7
3
22
XTAL_SEL
M8
4
21
VCCA
N0
5
20
S_LOAD
N1
6
19
S_DATA
nc
7
18
S_CLOCK
VEE
8
17
MR
ICS8432-51
9 10 11 12 13 14 15 16
PHASE DETECTOR
VEE
nFOUT0
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
M0:M8
N0:N1
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
FOUT0
TEST
VCCO
CONFIGURATION
INTERFACE
LOGIC
FOUT0
nFOUT0
FOUT1
nFOUT1
nFOUT1
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
1
÷1
÷2
÷4
÷8
FOUT1
÷M
0
VCC
VCO
TEST
MR
1
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
N output divider to a specific default state that will automatically
occur during power-up. The TEST output is LOW when operating
in the parallel input mode. The relationship between the VCO
frequency, the crystal frequency and the M divider is defined as
follows: fVCO = fxtal x M
The ICS8432-51 features a fully integrated PLL and therefore,
requires no external components for setting the loop bandwidth.
A fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the phase detector.
A 25MHz crystal provides a 25MHz phase detector reference
frequency. The VCO of the PLL operates over a range of 250MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz
reference are defined as 10 ≤ M ≤ 28. The frequency out is defined as follows: FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift reg-ister
are loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly
to the M divider and N output divider on each ris-ing edge of
S_CLOCK. The serial mode can be used to program the M and N
bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows:
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8432-51 support two input modes to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode, the nP_LOAD
input is initially LOW. The data on inputs M0 through M8 and N0
and N1 is passed directly to the M divider and N output divider.
On the LOW-to-HIGH transition of the nP_LOAD input, the data
is latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. As a result,
the M and N bits can be hardwired to set the M divider and
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout
SERIAL LOADING
S_CLOCK
T1
S_DATA
t
S_LOAD
S
t
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
H
t
nP_LOAD
S
PARALLEL LOADING
M, N
M0:M8, N0:N1
nP_LOAD
t
S
t
H
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
M5
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Input
M divider inputs. Data latched on LOW-to-HIGH transition
Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
Pulldown
7
nc
Unused
8, 16
VEE
Power
Negative supply pins.
9
TEST
Output
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
10
VCC
Power
Core supply pin.
11, 12
FOUT1, nFOUT1
Output
Differential output for the synthesizer. 3.3V LVPECL interface levels.
13
VCCO
Power
Output supply pin.
14, 15
FOUT0, nFOUT0
Output
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Input
Description
Pullup
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
No connect.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the
inver ted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Asser tion of MR does not
effect loaded M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
17
MR
Input
Pulldown
18
S_CLOCK
Input
Pulldown
19
S_DATA
Input
Pulldown
20
S_LOAD
Input
Pulldown
21
VCCA
Power
Analog supply pin.
XTAL_SEL
Input
Selects between cr ystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels.
22
23
REF_CLK
Input
24,
25
XTAL_OUT,
XTAL_IN
Input
26
nP_LOAD
Input
27
VCO_SEL
Input
Pullup
Pulldown Referenc clock input. LVCMOS / LVTTL interface levels.
Cr ystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL
AND
SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
↑
Data
Data
L
X
X
L
H
X
X
L
↑
Data
L
H
X
X
↑
L
Data
L
H
X
X
↓
L
Data
M divider and N output divider values are latched.
L
H
X
X
L
X
X
Parallel or serial input do not affect shift registers.
L
H
X
X
H
↑
Data
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
0
0
0
0
0
1
0
1
0
11
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
VCO Frequency
(MHz)
M Divide
250
10
275
650
26
0
0
0
0
1
1
0
1
0
675
27
0
0
0
0
1
1
0
1
1
700
28
0
0
0
0
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency
of 25MHz.
0
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N Divider Value
Output Frequency (MHz)
N1
N0
0
0
1
250
700
0
1
2
12 5
350
1
0
4
62.5
175
1
1
8
31.25
87.5
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
4
Minimum
Maximum
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.5V to VCC + 0.5 V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
32 Lead LQFP
32 Lead VFQFN
47.9°C/W (0 lfpm)
41.07°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VCC
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3. 3
3.465
V
VCCA
Analog Supply Voltage
VCC – 0.15
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
135
mA
ICCA
Analog Supply Current
15
mA
Maximum
Units
2
VCC + 0.3
V
2
VCC + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
VCC = VIN = 3.465V
150
µA
VCC = VIN = 3.465V
5
µA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VIH
VIL
IIH
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
Test Conditions
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
REF_CLK
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
REF_CLK
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, REF_CLK,
S_DATA, S_LOAD, nP_LOAD
M5, XTAL_SEL, VCO_SEL
IIL
Input
Low Current
Minimum
Typical
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, REF_CLK,
S_DATA, S_LOAD, nP_LOAD
VCC = 3.465V,
VIN = 0V
-5
µA
M5, XTAL_SEL, VCO_SEL
VCC = 3.465V,
VIN = 0V
-150
µA
2. 6
V
VOH
Output
High Voltage
TEST; NOTE 1
VOL
Output
Low Voltage
TEST; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VCCO/2.
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
5
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
Minimum
Typical
Maximum
Units
VCCO - 1.4
VCCO - 0.9
V
VCCO - 2.0
VCCO - 1.7
V
1.0
V
Maximum
Units
Peak-to-Peak Output Voltage Swing
0.6
VSWING
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section,
figure "3.3V Output Load Test Circuit".
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
REF_CLK; NOTE 1
12
25
MHz
XTAL_IN, XTAL_OUT;
Input Frequency
12
25
MHz
fIN
NOTE 1
S_CLOCK
50
MHz
NOTE 1: For the input cr ystal and REF_CLK frequency range, the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 21 ≤ M ≤ 58. Using the
maximum frequency of 25MHz, valid values of M are 10 ≤ M ≤ 28.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
25
MHz
Equivalent Series Resistance (ESR)
Frequency
12
70
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
TABLE 7. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Maximum
Units
700
MHz
25
ps
Period Jitter, RMS; NOTE 1
3.5
ps
Output Skew; NOTE 2, 3
15
ps
700
ps
FOUT
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 3
tjit(per)
tsk(o)
tR / tF
Output Rise/Fall Time
tH
Setup Time
Hold Time
Typical
31.25
fVCO > 350MHz
20% to 80%
M, N to nP_LOAD
tS
Minimum
200
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
odc
Output Duty Cycle
N>1
48
52
%
tPW
Output Pulse Width
N=1
tPERIOD/2 - 150
tPERIOD/2 + 150
ps
PLL Lock Time
tLOCK
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
6
1
ms
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
2V
nFOUTx
VCC,
VCCO
Qx
SCOPE
FOUTx
VCCA
nFOUTy
LVPECL
nQx
FOUTy
EE
VVEE
tsk(o)
-1.3V± 0.165V
OUTPUT SKEW
VOH
nFOUTx
VREF
FOUTx
➤
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
tcycle n
➤
3.3V OUTPUT LOAD AC TEST CIRCUIT
➤
ttcycle
cycle n+1
n+1
➤
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
CYCLE-TO-CYCLE JITTER
PERIOD JITTER
nFOUTx
nFOUTx
80%
FOUTx
80%
VSW I N G
t PW
t
odc =
PERIOD
t PW
FOUTx
20%
20%
tR
tF
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
OUTPUT RISE/FALL TIME
7
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the
elements within a SAN. The tables below lists the common
frequencies used as well as the settings for the ICS8432-51 to
generate the appropriate frequency.
Table 8. Common SANs Application Frequencies
Clock Rate
Reference Frequency to SERDES
(MHz)
Crystal Frequency
(MHz)
1.25 GHz
125, 250, 156.25
25, 19.53125
FC1 1.0625 GHz
FC2 2.1250 GHz
106.25, 53.125, 132.8125
16.6015625, 25
2.5 GHz
125, 250
25
Interconnect Technology
Gigabit Ethernet
Fibre Channel
Infiniband
Table 9. Configuration Details for SANs Applications
Interconnect
Technology
Crystal Frequency
(MHz)
ICS8432-51
Output Frequency
to SERDES
(MHz)
25
125
0
0
0
0
1
0
1
0
25
250
0
0
0
0
1
0
1
25
156.25
0
0
0
0
1
1
19.53125
156.25
0
0
0
1
0
25
53.125
0
0
0
0
25
106.25
0
0
0
16.6015625
132.8125
0
0
25
125
0
25
250
0
ICS8432-51
M & N Settings
M8 M7 M6 M5 M4 M3 M2
M1 M0
N1
N0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
1
Gigabit Ethernet
Fiber Channel 1
Fiber Channel 2
Infiniband
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8432-51 provides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VCC, VCCA and VCCO should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin.
Figure 2 illustrates this for a generic VCC pin and also shows that
VCCA requires that an additional 10Ω resistor along with a 10µF
bypass capacitor be connected to the VCCA pin.
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10 μF
FIGURE 2. POWER SUPPLY FILTERING
8
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS8432-51 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
FIGURE 3. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
OUTPUTS:
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_CLK INPUT
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the REF_CLK to ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUTx and nFOUTx are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FOUT
50Ω
VCC - 2V
FIN
Zo = 50Ω
RTT
84Ω
FIGURE 5A. LVPECL OUTPUT TERMINATION
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
84Ω
FIGURE 5B. LVPECL OUTPUT TERMINATION
10
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land patter n must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 6. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
SOLDER
LAND PATTERN
THERMAL VIA
PIN
PIN PAD
(GROUND PAD)
FIGURE 6. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The schematic of the ICS8432-51 layout example used in this
layout guideline is shown in Figure 7A. The ICS8432-51
recommended PCB board layout for this example is shown in
Figure 7B. This layout example is used as a general guideline.
The layout in the actual system will depend on the selected
component types, the density of the components, the density of
the traces, and the stack up of the P.C. board.
C1
C2
M5
M6
M7
M8
N0
N1
nc
VEE
8432-51
VCC
C14
0.1u
X_OUT
REF_CLK
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
9
10
11
12
13
FOU T
14
FOUTN 15
16
1
2
3
4
5
6
7
8
TEST
VC C
FOUT1
nFOUT1
VC CO
FOUT0
nFOUT0
VEE
U1
M4
M3
M2
M1
M0
VC O_SEL
nP_LOAD
X_IN
32
31
30
29
28
27
26
25
X1
C15
0.1u
VCC
24
23
22
21
20
19
18
17
R7
10
REF_IN
XTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
C11
0.01u
C16
10u
VCC
R1
125
R3
125
Zo = 50 Ohm
TL1
+
Zo = 50 Ohm
-
TL2
VCC=3.3V
R2
84
R4
84
FIGURE 7A. SCHEMATIC OF RECOMMENDED LAYOUT
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example:
• The differential 50Ω output traces should have the
same length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
CLOCK TRACES AND TERMINATION
CRYSTAL
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The crystal X1 should be located as close as possible to the pins
24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
GND
C1
C2
VCC
X1
VIA
U1
PIN 1
C16
C11
VCCA
R7
Close to the input
pins of the
receiver
TL1N
C15
TL1
C14
TL1
R1
R2
TL1N
R3
R4
TL1, TL21N are 50 Ohm
traces and equal length
FIGURE 7B. PCB BOARD LAYOUT FOR ICS8432-51
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-51.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432-51 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 60mW = 527.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 10A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.528W * 42.1°C/W = 92.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 10A. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 10B. THERMAL RESISTANCE θJA FOR 32-PIN VFQFN, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
34.8°C/W
14
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CCO
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(V
CCO_MAX
•
–V
OH_MAX
) = 0.9V
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX– VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/R ] * (VCCO_MAX – VOH_MAX) =
L
L
[(2V - 0.9V)/50Ω) * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/R ] * (VCCO_MAX – VOL_MAX) =
L
L
[(2V – 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 11A. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 11B. θJAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN PACKAGE
θJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
TRANSISTOR COUNT
The transistor count for ICS8432-51 is: 3743
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 12A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - K SUFFIX 32 LEAD VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
L
A3
N
N
e (Ty p.)
2 If N & N
1
Anvil
Singula tion
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
e
N &N
Odd
0. 08
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
C
D2
2
Th er mal
Ba se
D2
C
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page.
The package dimensions are in Table 8 below.
TABLE 12B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
Minimum
Maximum
32
N
A
0.80
1.0
A1
0
0.05
0.25 Reference
A3
b
0.18
0.30
e
0.50 BASIC
ND
8
NE
8
5.0
D
D2
1.25
3.25
5.0
E
E2
1.25
3.25
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 13. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS8432BY-51
ICS8432BY-51
32 Lead LQFP
tray
0°C to 70°C
ICS8432BY-51T
ICS8432BY-51
32 Lead LQFP
1000 tape & reel
0°C to 70°C
ICS8432BY-51LF
ICS8432BY51L
32 Lead "Lead-Free" LQFP
tray
0°C to 70°C
ICS8432BY-51LFT
ICS8432BY51L
32 Lead "Lead-Free" LQFP
1000 tape & reel
0°C to 70°C
ICS8432BK-51
ICS8432BK51
32 Lead VFQFN
tray
0°C to 70°C
ICS8432BK-51T
ICS8432BK51
32 Lead VFQFN
2500 tape & reel
0°C to 70°C
ICS8432BK-51LF
ICS8432B51L
32 Lead VFQFN
tray
0°C to 70°C
ICS8432BK-51LFT
ICS8432B51L
32 Lead VFQFN
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8432BY-51 REV. F MAY 13, 2008
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700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
Table
Page
Corrected labels on the Parallel & Serial Load Operations diagram.
Revised MR pin description.
Power Supply table - changed IDD to 155mA max. from 130mA max., changed IDDA to
20mA max. from 15mA max., and changed IDDO to 55mA max. from 45mA max.
12/18/02
T1
T4A
2
3
5
9
1
Added LVDS Driver Termination Section.
General Description & Features - changed VCO min. from 200MHz to 250MHz and
replaced throughout the datasheet in: (Functional Description pg2, T3C Program.
Output Divider Func. Table pg4, and T5 Input Freq Charac. Table pg6).
- Features - changed min. Output Frequency Range from 25MHz to 31.25MHz.
3/12/03
3
Pin Descriptions Table - revised XTAL1, XTAL2 pin description.
A
B
B
T1
C
C
C
D
T2
3
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
4
Prog. VCO Freq. Func. Table - deleted 200 and 225 rows, does not apply.
T4A
5
Power Supply DC Characteristics Table - deleted VDDO & IDDO rows,
does not apply.
T7
6
AC Characteristics Table - change FOUT 25MHz min. to 31.25MHz min.
1
Pin Assignment - corrected XTAL pins. Pin 24 is labeled XTAL2 and pin 25 is labeled
XTAL1.
2
Revised Parallel & Serial Load Operations diagram.
3
Pin Descriptions Table - corrected XTAL pins to correspond with the pin number.
Changed XTAL1 to read input and XTAL2 to read output.
10
Updated Figure 5A schematic to correspond the XTAL pins with the Pin Assignment.
11
1
16
1
5
6
9
10
Cr ystal section, corrected pin 24 to read XTAL2 and pin 25 to read XTAL1.
Features Section - added Lead-Free bullet.
Ordering Information - added Lead-Free par t number.
Added 32 Lead VFQFN Package for Pin Assignment.
Power Supply DC Characteristics Table - changed VCCA min. from 3.135V to VCC - 0.15V.
Cr ystal Characteristics Table - added Drive Level.
Added LVCMOS to XTAL Interface.
Added Recommendations for Unused Input and Output Pins.
Added VFQFN package throughout the datasheet.
Changed naming convention of TEST_CLK to REF_CLK, (pin 24) XTAL2 to XTAL_OUT,
and (pin 25) XTAL1 to XTAL_IN. Changed throughout the datasheet.
T1
T13
T4A
T6
T4C
6
13 - 14
T13
F
Date
T3B
1
E
Description of Change
18
5/9/03
LVPECL DC Characteristics Table - corrected VOH max. from VCCO - 1.0V to VCCO - 0.9V.
Power Considerations - corrected power dissipation to reflect VOH max in Table 4C.
1
Ordering Information Table - corrected ICS8432BK-51 marking to ICS8432BK51. Added
VFQFN marking.
Pin Assignment - corrected typo on pin 25 from XTAL_OUT to XTAL_IN.
11
Added VFQFN EPAD Thermal Release Path section.
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
20
2/13/03
5/28/03
4/8/05
4/13/06
4/10/07
5/13/08
ICS8432BY-51 REV. F MAY 13, 2008
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
Corporate Headquarters
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
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www.IDT.com/go/contactIDT
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+480-763-2056
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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