8432DYI-101LFT

8432I-101 700MHz, Differential-to-3.3V LVPECL Frequency Synthesizer Data Sheet GENERAL DESCRIPTION FEATURES The 8432I-101 is a general pur pose, dual outp u t D i f f e r e n t i a l - t o - 3 . 3 V LV P E C L h i g h f r e q u e n c y synthesizer and a member of the fa m i l y o f H i g h Pe r fo r m a n c e C l o c k S o l u t i o n s f r o m IDT. The 8432I-101 has a selectable TEST_CLK or CLK, nCLK inputs. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The CLK, nCLK pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input differential or single ended reference frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics of the 8432I-101 makes it an ideal clock source for Gigabit Ethernet and SONET applications. • Dual differential 3.3V LVPECL outputs • Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK • TEST_CLK can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK, nCLK or TEST_CLK maximum input frequency: 40MHz • Output frequency range: 25MHz to 700MHz • VCO range: 250MHz to 700MHz • Accepts any single-ended input signal on CLK input with resistor bias on nCLK input • Parallel interface for programming counter and output dividers • RMS period jitter: 5ps (maximum) • Cycle-to-cycle jitter: 25ps (maximum) • 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT nCLK nP_LOAD VCO_SEL M0 M1 M2 M3 M4 32 31 30 29 28 27 26 25 M5 1 24 CLK M6 2 23 TEST_CLK M7 3 22 CLK_SEL M8 4 21 VCCA N0 5 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK VEE 8 17 MR ICS8432I-101 9 10 11 12 13 14 15 16 VEE nFOUT0 FOUT0 VCCO nFOUT1 FOUT1 VCC TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ©2016 Integrated Device Technology, Inc 1 Revision C January 8, 2016 8432I-101 Data Sheet FUNCTIONAL DESCRIPTION set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the input frequency and the M divider is defined as follows: fVCO = fIN x M NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values for different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The 8432I-101 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A differential clock input is used as the input to the 8432I101. This input is fed into the phase detector. A 25MHz clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 8 ≤ M ≤ 28. The frequency out is defined as follows: fOUT = fVCO = fIN x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note, that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the 8432I-101 support two input modes to program the PLL M divider and N output divider. The two input operational modes are parallel and serial. Figure1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Input 1 0 Output of M divider 1 1 CMOS Fout FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. ©2016 Integrated Device Technology, Inc 2 Revision C January 8, 2016 8432I-101 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 M5 Input 2, 3, 4 28, 29 30, 31, 32 M6, M7, M8, M0, M1, M2, M3, M4 Input M divider inputs. Data latched on LOW-to-HIGH transistion Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels. 5, 6 N0, N1 Input Pulldown 7 nc Unused 8, 16 VEE Power Negative supply pins. 9 TEST Output Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS / LVTTL interface levels. 10 VCC Power Core supply pin. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. 3.3V LVPECL interface levels. 13 VCCO Power Output supply pin. 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. 3.3V LVPECL interface levels. Pullup Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. No connect. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. 17 MR Input Pulldown 18 S_CLOCK Input Pulldown 19 S_DATA Input Pulldown 20 S_LOAD Input Pulldown 21 VCCA Power Analog supply pin. Clock select input. Selects between differential clock input or TEST_ CLK input as the PLL reference source. When HIGH, selects CLK, nCLK inputs. When LOW, selects TEST_CLK input. LVCMOS / LVTTL interface levels. 22 CLK_SEL Input Pullup 23 TEST_CLK Input 24 CLK Input Pulldown Non-inverting differential clock input. 25 nCLK Input Pullup Inverting differential clock input. 26 nP_LOAD Input 27 VCO_SEL Input Pulldown Test clock input. LVCMOS / LVTTL interface levels. Parallel load input. Determines when data present at M8:M0 is loaded Pulldown into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LVCMOS Pullup / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterisitics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ©2016 Integrated Device Technology, Inc Test Conditions 3 Minimum Typical Maximum Units Revision C January 8, 2016 8432I-101 Data Sheet TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X L L Data Data X X X L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial inputs do not affect shift registers. L H X X H Reset. Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 8 0 0 0 0 0 1 0 0 0 9 0 0 0 0 0 1 0 0 1 250 10 0 0 0 0 0 1 0 1 0 275 11 0 0 0 0 0 1 0 1 1 • • • • • • • • • • • VCO Frequency (MHz) M Divide 200 225 • • • • • • • • • • • 650 26 0 0 0 0 1 1 0 1 0 675 27 0 0 0 0 1 1 0 1 1 700 28 0 0 0 0 1 1 1 0 0 NOTE 1: These M divide values and the resulting frequencies correspond to differential input or TEST_CLK input frequency of 25MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value N1 N0 0 0 1 0 1 1 0 1 1 Output Frequency (MHz) Minimum Maximum 250 700 2 125 350 4 62.5 175 8 31.25 87.5 ©2016 Integrated Device Technology, Inc 4 Revision C January 8, 2016 8432I-101 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 120 mA ICCA Analog Supply Current 15 mA Symbol Parameter VCC VCCA Test Conditions TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL IIH IIL Input Low Voltage Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units VCO_SEL, CLK_SEL, MR, S_ LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N1 2 VCC + 0.3 V TEST_CLK 2 VCC + 0.3 V -0.3 0.8 V -0.3 1.3 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA VCO_SEL, CLK_SEL, MR, S_ LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N1 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, nP_LOAD M5, CLK_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, nP_LOAD VCC = 3.465V, VIN = 0V -5 µA M5, CLK_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA 2.6 V VOH Output High Voltage TEST VCC = 3.135V, IOH = -36mA VOL Output Low Voltage TEST VCC = 3.135V, IOL = 36mA ©2016 Integrated Device Technology, Inc 5 0.5 V Revision C January 8, 2016 8432I-101 Data Sheet TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage Minimum Typical Maximum Units CLK VCC = VIN = 3.465V 150 µA nCLK VCC = VIN = 3.465V 5 µA CLK VCC = 3.465V, VIN = 0V -5 nCLK VCC = 3.465V, VIN = 0V -150 µA µA 0.15 1.3 V VEE + 0.5 VCC - 0.85 V NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL VSWING Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fIN Input Frequency Minimum Typical Maximum Units TEST_CLK; NOTE 1 10 25 MHz CLK, nCLK; NOTE 1 10 25 MHz 25 MHz S_CLOCK NOTE 1: For the differential input and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 10MHz, valid values of M are 25 ≤ M ≤ 70. Using the maximum frequency of 25MHz, valid values of M are 10 ≤ M ≤ 28. TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions FOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 fVCO > 350MHz 25 ps tjit(per) Period Jitter, RMS fOUT > 100MHz 5 ps 15 ps 700 ps tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time tS tH Setup Time Hold Time Minimum Typical 31.25 20% to 80% 200 Maximum Units 700 MHz M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle N>1 47 53 % tPW Output Pulse Width N=1 tPERIOD/2 - 150 tPERIOD/2 + 150 ps tLOCK PLL Lock Time 1 ms See Parameter Measurement Information section. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. ©2016 Integrated Device Technology, Inc 6 Revision C January 8, 2016 8432I-101 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PERIOD JITTER CYCLE-TO-CYCLE JITTER OUTPUT SKEW OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ©2016 Integrated Device Technology, Inc 7 Revision C January 8, 2016 8432I-101 Data Sheet APPLICATION INFORMATION STORAGE AREA NETWORKS A variety of technologies are used for interconnection of the elements within a SAN. The tables below list the common application frequencies as well as the 8432I-101 configurations used to generate the appropriate frequency. Table 7. Common SANs Application Frequencies Clock Rate Reference Frequency to SERDES (MHz) Crystal Frequency (MHz) 1.25 GHz 125, 250, 156.25 25, 19.53125 FC1 1.0625 GHz FC2 2.1250 GHz 106.25, 53.125, 132.8125 16.6015625, 25 2.5 GHz 125, 250 25 Interconnect Technology Gigabit Ethernet Fibre Channel Infiniband Table 8. Configuration Details for SANs Applications Interconnect Technology CLK, nCLK Input (MHz) 8432I-101 Output Frequency to SERDES (MHz) M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0 25 125 0 0 0 0 1 0 1 0 0 1 0 25 250 0 0 0 0 1 0 1 0 0 0 1 25 156.25 0 0 0 0 1 1 0 0 1 1 0 19.53125 156.25 0 0 0 1 0 0 0 0 0 1 0 25 53.125 0 0 0 0 1 0 0 0 1 1 1 25 106.25 0 0 0 0 1 0 0 0 1 1 0 16.6015625 132.8125 0 0 0 1 0 0 0 0 0 1 0 25 125 0 0 0 0 1 0 1 0 0 1 0 25 250 0 0 0 0 1 0 1 0 0 0 1 8432I-101 M & N Settings Gigabit Ethernet Fiber Channel 1 Fiber Channel 2 Infiniband POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 8432I-101 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. ©2016 Integrated Device Technology, Inc 3.3V VCC .01μF 10Ω VCCA .01μF 10 μF FIGURE 2. POWER SUPPLY FILTERING 8 Revision C January 8, 2016 8432I-101 Data Sheet WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. LVPECL OUTPUT: All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ©2016 Integrated Device Technology, Inc 9 Revision C January 8, 2016 8432I-101 Data Sheet DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY IDT HIPERCLOCKS LVHSTL DRIVER FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE ©2016 Integrated Device Technology, Inc 10 Revision C January 8, 2016 8432I-101 Data Sheet TERMINATION FOR LVPECL OUTPUTS lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 5A. LVPECL OUTPUT TERMINATION ©2016 Integrated Device Technology, Inc FIGURE 5B. LVPECL OUTPUT TERMINATION 11 Revision C January 8, 2016 8432I-101 Data Sheet LAYOUT GUIDELINE The schematic of the 8432I-101 layout example used in this layout guideline is shown in Figure 6A. The 8432I-101 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. nCLK CLK R7 32 31 30 29 28 27 26 25 M5 M6 M7 M8 N0 N1 nc VEE 10 CLK REF_IN nCLK_SEL VDDA S_LOAD S_DATA S_CLOCK MR 24 23 22 21 20 19 18 17 C11 0.01u C16 10u XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR Termination A VCC VCC FOUT FOUTN VCC TEST 9 10 11 12 13 14 15 16 8432-101 M4 M3 M2 M1 M0 VCO_SEL nP_LOAD nCLK 1 2 3 4 5 6 7 8 VCC TEST VDD FOUT1/2 nFOUT1/2 VCCO FOUT nFOUT VEE U1 R1 125 R3 125 IN+ Zo = 50 Ohm IN+ IN- TL1 R2 50 Zo = 50 Ohm C14 0.1u Termination B (not shown in the layout) INC15 0.1u R1 50 TL2 R2 84 R4 84 R3 50 FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT ©2016 Integrated Device Technology, Inc 12 Revision C January 8, 2016 8432I-101 Data Sheet The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. POWER AND GROUNDING Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. • The traces with 50Ω transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. • Keep the clock trace on same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. If VCCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA as possible. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. CLOCK TRACES AND TERMINATION • Make sure no other signal trace is routed between the clock trace pair. The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example. FIGURE 6B. PCB BOARD LAYOUT FOR 8432I-101 ©2016 Integrated Device Technology, Inc 13 Revision C January 8, 2016 8432I-101 Data Sheet POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 8432I-101. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8432I-101 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 416mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 416mW + 60mW = 476mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 9 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.476W * 42.1°C/W = 105°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 9. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ©2016 Integrated Device Technology, Inc 14 Revision C January 8, 2016 8432I-101 Data Sheet 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO- 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ©2016 Integrated Device Technology, Inc 15 Revision C January 8, 2016 8432I-101 Data Sheet RELIABILITY INFORMATION TABLE 10. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 8432I-101 is: 3712 ©2016 Integrated Device Technology, Inc 16 Revision C January 8, 2016 8432I-101 Data Sheet PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 11. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL N 32 A 1.60 A1 0.05 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.15 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 E 9.00 BASIC E1 7.00 BASIC E2 5.60 e 0.80 BASIC L 0.45 θ 0° 0.60 0.75 7° ccc Reference Document: JEDEC Publication 95, MS-026 ©2016 Integrated Device Technology, Inc MAXIMUM 17 0.10 Revision C January 8, 2016 8432I-101 Data Sheet TABLE 12. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8432DYI-101LF ICS432DI101L 32 Lead “Lead-Free” LQFP 250 -40°C to 85°C 8432DYI-101LFT ICS432DI101L 32 Lead “Lead-Free” LQFP tape & reel -40°C to 85°C ©2016 Integrated Device Technology, Inc 18 Revision C January 8, 2016 8432I-101 Data Sheet REVISION HISTORY SHEET Rev A Table Page T12 T5 1 17 6 9 B C C C Description of Change Date Features Section - added Lead-Free bullet. Ordering Information Table - add Lead-Free parts. Input Frequency Characteristics Table - changed fIN (TEST_CLK and CLK, nCLK) from 14MHz min. to 10MHz min. Added Recommendations for Unused Input and Output Pins. LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO - 0.9V. Power Considerations - corrected power dissipation to reflect VOH max in Table 4D. 10/26/06 10/23/15 T4D 6 14 - 15 T12 18 Ordering Information - removed leaded devices. Updated data sheet information. T12 18 Ordering Information - removed ICS from part/order number. Removed 1000 from tape and reel and removed LF note from below the table. Updated headers and footers. ©2016 Integrated Device Technology, Inc 19 5/23/05 4/10/07 1/8/16 Revision C January 8, 2016 8432I-101 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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