87972DYI-147LFT

87972I-147 Low Skew, 1-to-12 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer Datasheet General Description Features The 87972I-147 is a low skew, LVCMOS/LVTTL Clock Generator and a member of the family of High Performance Clock Solutions from IDT. The 87972I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. • • Fully integrated PLL • Selectable crystal oscillator interface or LVCMOS/LVTTL reference clock inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • • • • • • • • Output frequency range: 10MHz to 150MHz The 87972I-147 is a highly flexible device. Using the crystal oscillator input, it can be used to generate clocks for a system. All of these clocks can be the same frequency or the device can be configured to generate up to three different frequencies among the three output banks. Using one of the single ended inputs, the 87972I-147 can be used as a zero delay buffer/multiplier/ divider in clock distribution applications. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 10MHz to 150MHz. Input frequency range is 6MHz to 150MHz. The 87972I-147 also has a QSYNC output which can be used or system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Fourteen LVCMOS/LVTTL outputs; (12)clocks, (1)feedback, (1)sync VCO range: 240MHz to 500MHz Output skew: 200ps (maximum) Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum) Full 3.3V supply voltage -40°C to 85°C ambient operating temperature Compatible with PowerPC™and Pentium™Microprocessors Available in lead-free (RoHS 6)packages. Example Applications: 1.System Clock generator: Use a 16.66 MHz Crystal to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. FSEL_B1 FSEL_B0 40 41 2.Line Card Multiplier: Multiply 19.44MHz from a back plane to 77.76MHz for the line Card ASICs and Serdes. FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 42 43 44 45 46 47 48 49 50 GNDO VCO_SEL 51 52 FSEL_FB0 GNDO QB0 VDDO QB1 GNDO QB2 VDDO QB3 EXT_FB GNDO QFB VDD Pin Assignment 39 38 37 36 35 34 33 32 31 30 29 28 27 25 24 23 FSEL_FB1 QSYNC GNDO QC0 VDDO QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO INV_CLK VDDA 2 3 4 5 6 7 8 9 10 11 12 13 FRZ_DATA FSEL_FB2 PLL_SEL REF_SEL CLK_SEL CLK0 CLK1 XTAL1 XTAL2 1 GNDI 22 21 20 19 18 17 16 15 14 nMR/OE FRZ_CLK 3.Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay. 26 87972I-147 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y Package Top View ©2015 Integrated Device Technology, Inc 1 December 7, 2015 87972I-147 Datasheet Block Diagram XTAL1 XTAL2 VCO_SEL Pullup PLL_SEL Pullup REF_SEL Pullup 1 D Q 0 CLK0 Pullup 0 CLK1 Pullup 1 0 PHASE DETECTOR CLK_SEL Pullup VCO 1 LPF EXT_FB Pullup D Q FSEL_FB2 QA0 SYNC FRZ QA1 SYNC FRZ QA2 SYNC FRZ QA3 SYNC FRZ QB0 SYNC FRZ QB1 SYNC FRZ QB2 SYNC FRZ QB3 Pullup nMR/OE Pullup ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 D Q ÷2, ÷4, ÷6, ÷8 FSEL_A[0:1] Pullup Pullup FSEL_C[0:1] Pullup FSEL_FB[0:2] Pullup QC0 D Q POWER-ON RESET FSEL_B[0:1] SYNC FRZ 2 0 ÷4, ÷6, ÷8, ÷10 ÷2 2 2 SYNC FRZ QC1 SYNC FRZ QC2 SYNC FRZ QC3 QFB D Q 1 SYNC PULSE 3 D Q DATA GENERATOR SYNC FRZ QSYNC FRZ_CLK Pullup FRZ_DATA Pullup OUTPUT DISABLE CIRCUITRY 12 INV_CLK Pullup ©2015 Integrated Device Technology, Inc 2 December 7, 2015 87972I-147 Datasheet Simplified Block Diagram nMR/OE XTAL1 1 XTAL2 FSEL_A[0:1] 2 CLK0 Pullup CLK1 Pullup CLK_SEL Pullup REF_SEL Pullup 0 0 FSEL_ A1 A0 0 0 0 1 1 0 1 1 PLL 1 VCO RANGE 240MHz - 500MHz EXT_FB Pullup 0 ÷2 0 1 ÷1 QAx ÷4 ÷6 ÷8 ÷12 SYNC FRZ QA0 SYNC FRZ QA1 SYNC FRZ QA2 SYNC FRZ QA3 SYNC FRZ QB0 SYNC FRZ QB1 SYNC FRZ QB2 SYNC FRZ QB3 FSEL_B[0:1] 2 1 FSEL_ B1 B0 0 0 0 1 1 0 1 1 VCO_SEL Pullup PLL_SEL Pullup QBx ÷4 ÷6 ÷8 ÷10 FSEL_C[0:1] 2 FSEL_ C1 C0 0 0 0 1 1 0 1 1 QC0 QCx ÷2 ÷4 ÷6 ÷8 0 1 SYNC FRZ QC1 SYNC FRZ QC2 SYNC FRZ QC3 INV_CLK FSEL_FB[0:2] 3 FSEL_ FB2 FB1 FB0 QFB 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 FRZ_CLK Pullup FRZ_DATA Pullup ©2015 Integrated Device Technology, Inc 3 OUTPUT DISABLE CIRCUITRY QFB SYNC FRZ QSYNC December 7, 2015 87972I-147 Datasheet Table 1. Pin Descriptions Number Name Type Description 1 GNDI Power 2 nMR/OE Input Pullup Master reset and output enable. When HIGH, enables the outputs. When LOW, resets the outputs to Hi-Z and resets output divide circuitry. Enables and disables all outputs. LVCMOS / LVTTL interface levels. 3 FRZ_CLK Input Pullup Clock input for freeze circuitry. LVCMOS / LVTTL interface levels. Power supply ground. 4 FRZ_DATA Input Pullup Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels. 5, 26, 27 FSEL_FB2, FSEL_FB1, FSEL_FB0 Input Pullup Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels. See Table 3B. 6 PLL_SEL Input Pullup Selects between the PLL and reference clocks as the input to the output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks. LVCMOS / LVTTL interface levels. 7 REF_SEL Input Pullup Selects between crystal and reference clock. When LOW, selects CLK0 or CLK1. When HIGH, selects crystal inputs. LVCMOS / LVTTL interface levels. 8 CLK_SEL Input Pullup Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. 9, 10 CLK0, CLK1 Input Pullup Single-ended reference clock inputs. LVCMOS/LVTTL interface levels. 11, 12 XTAL_1, XTAL_2 Input Crystal oscillator interface. XTAL_1 is the input. XTAL_2 is the output. 13 VDDA Power Analog supply pin. 14 INV_CLK Input 15, 24, 30, 35, 39, 47, 51 GNDO Power Power supply ground. 16, 18, 21, 23 QC3, QC2, QC1, QC0 Output Single-ended Bank C clock outputs. LVCMOS/ LVTTL interface levels. 17, 22, 33, 37, 45, 49 VDDO Power Output power supply pins. 19, 20 FSEL_C1, FSEL_C0 Input 25 QYSNC Output Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams. LVCMOS / LVTTL interface levels. 28 VDD Power Power supply pin. 29 QFB Output 31 EXT_FB Input 32, 34, 36, 38 QB3, QB2, QB1, QB0 Output 40, 41 FSEL_B1, FSEL_B0 Input Pullup Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. See Table 3A. 42, 43 FSEL_A1, FSEL_A0 Input Pullup Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. See Table 3A. 44, 46 48, 50 QA3, QA2, QA1, QA0 Output 52 VCO_SEL Input Pullup Pullup Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels. Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. See Table 3A. Single-ended feedback clock output. LVCMOS / LVTTL interface levels. Pullup External feedback. LVCMOS / LVTTL interface levels. Single-ended Bank B clock outputs. LVCMOS/ LVTTL interface levels. Single-ended Bank A clock outputs. LVCMOS/ LVTTL interface levels. Pullup Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. ©2015 Integrated Device Technology, Inc 4 December 7, 2015 87972I-147 Datasheet Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k CPD Power Dissipation Capacitance (per output) ROUT Output Impedance VDD, VDDA, VDDO = 3.465V 5 7 Units 18 pF 12  Function Tables Table 3A. Output Bank Configuration Select Function Table Inputs Outputs Inputs Outputs Inputs Outputs FSEL_A1 FSEL_A0 QA FSEL_B1 FSEL_B0 QB FSEL_C1 FSEL_C0 QC 0 0 ÷4 0 0 ÷4 0 0 ÷2 0 1 ÷6 0 1 ÷6 0 1 ÷4 1 0 ÷8 1 0 ÷8 1 0 ÷6 1 1 ÷12 1 1 ÷10 1 1 ÷8 Table 3B. Feedback Configuration Select Function Table Inputs Outputs FSEL_FB2 FSEL_FB1 FSEL_FB0 QFB 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 Table 3C. Control Input Select Function Table Control Pin Logic 0 Logic 1 VCO_SEL VCO/2 VCO REF_SEL CLK0 or CLK1 XTAL CLK_SEL CLK0 CLK1 PLL_SEL BYPASS PLL Enable PLL nMR/OE Master Reset/Output Hi-Z Enable Outputs INV_CLK Non-Inverted QC2, QC3 Inverted QC2, QC3 ©2015 Integrated Device Technology, Inc 5 December 7, 2015 87972I-147 Datasheet fVCO 1:1 Mode QA QC QSYNC 2:1 Mode QA QC QSYNC 3:1 Mode QC(÷2) QA(÷4) QSYNC 3:2 Mode QC(÷2) QA(÷8) QSYNC 4:1 Mode QC(÷2) QA(÷8) QSYNC 4:3 Mode QA(÷6) QC(÷8) QSYNC 6:1 Mode QA(÷12) QC(÷2) QSYNC Figure 1. Timing Diagrams ©2015 Integrated Device Technology, Inc 6 December 7, 2015 87972I-147 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 42.3C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 250 mA IDDA Analog Supply Current 20 mA Maximum Units 2 VDD + 0.3 V VCO_SEL, PLL_SEL, REF_SEL, CLK_SEL, EXT_FB, FSEL_FB[0:2], FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FRZ_DATA -0.3 0.8 V CLK0, CLK1, INV_CLK, FRZ_CLK -0.3 1.3 V ±120 µA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage Test Conditions IIN Input Current VOH Output High Voltage; NOTE 1 IOH = -20mA VOL Output Low Voltage; NOTE 1 IOL = 20mA Minimum Typical 2.4 V 0.5 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagram. ©2015 Integrated Device Technology, Inc 7 December 7, 2015 87972I-147 Datasheet Table 5. Input Frequency Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical CLK0, CLK1; NOTE 1 FIN Input Frequency XTAL1, XTAL 12 FRZ_CLK Maximum Units 150 MHz 40 MHz 20 MHz NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * feedback divide" is in the VCO range of 240MHz to 500MHz. Table 6. Crystal Characteristics Parameter Test Conditions Minimum Maximum Units 40 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF Maximum Units ÷2 150 MHz ÷4 125 MHz ÷6 83.33 MHz ÷8 62.5 MHz Mode of Oscillation Typical Fundamental Frequency 12 AC Electrical Characteristics Table 7. AC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Parameter fMAX Symbol Test Conditions Output Frequency CLK0 t(Ø) Static Phase Offset; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tjit(cc) Cycle-to-Cycle Jitter; NOTE 3 CLK1 QFB ÷ 8, In Frequency = 50MHz Minimum Typical -10 145 300 ps -65 90 245 ps 200 ps 55 ps 500 MHz 10 ms 0.15 0.7 ns 45 55 % All Banks ÷ 4 fVCO PLL VCO Lock Range tLOCK PLL Lock Time; NOTE 4 240 tR / tF Output Rise/Fall Time odc Output Duty Cycle tPZL, tPZH Output Enable Time; NOTE 4 10 ns tPLZL, tPHZ Output Disable Time; NOTE 4 8 ns 0.8V to 2V NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. ©2015 Integrated Device Technology, Inc 8 December 7, 2015 87972I-147 Datasheet Parameter Measurement Information 1.65V±5% SCOPE VDD, VDDA, VDDO Qx Qx Qy GND tsk(o) -1.65V±5% 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit Output Skew V DDO V V DDO 2 DDO 2 ➤ tcycle n ➤ QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB V DDO ➤ 2 tcycle n+1 2 QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles t PW t odc = PERIOD t PW x 100% t PERIOD Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width Period VDD CLK0, CLK1 2 QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB VDD 2 EXT_FB ➤ ➤ t(Ø) 2V 2V 0.8V 0.8V tR tF t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges Static Phase Offset ©2015 Integrated Device Technology, Inc Output Rise/Fall Time 9 December 7, 2015 87972I-147 Datasheet Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The 87972I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 2. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK Inputs For applications not requiring the use of the clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK to ground. LVCMOS Control Pins All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. ©2015 Integrated Device Technology, Inc 10 December 7, 2015 87972I-147 Datasheet Crystal Input Interface The 87972I-147 has been characterized with 18 pF parallel resonant crystals. External capacitors are not required for this crystal interface. While layout the PC board, it is recommended to have spare footprints capacitor C1 and C2. If required, the spare C1 and C2 footprints can be used for fine tuned further for more accurate frequency. The possible C1 and C2 value are ranged from 2pF – 25pF. The suggest footprint size is 0402 or 0603. XTAL_IN C1 Spare X1 18pF Parallel Crystal XTAL_OUT C2 Spare Figure 3. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 4. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. VCC VCC R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface ©2015 Integrated Device Technology, Inc 11 December 7, 2015 87972I-147 Datasheet Using the Output Freeze Circuitry OVERVIEW FRZ_DATA bit with the rising edge of the FRZ_CLK signal. To place an output in the freeze state, a logic “0” must be written to the respective freeze enable bit in the shift register. To unfreeze an output, a logic “1” must be written to the respective freeze enable bit. Outputs will not become enabled/disabled until all 12 data bits are shifted into the shift register. When all 12 data bits are shifted in the register, the next rising edge of FRZ_CLK will enable or disable the outputs. If the bit that is following the 12th bit in the register is a logic “0”, it is used for the start bit of the next cycle; otherwise, the device will wait and won’t start the next cycle until it sees a logic “0” bit. Freezing and unfreezing of the output clock is synchronous (see the timing diagram below). When going into a frozen state, the output clock will go LOW at the time it would normally go LOW, and the freeze logic will keep the output low until unfrozen. Likewise, when coming out of the frozen state, the output will go HIGH only when it would normally go HIGH. This logic, therefore, prevents runt pulses when going into and out of the frozen state. To enable low power states within a system, each output of 87972I-147 (Except QC0 and QFB) can be individually frozen (stopped in the logic “0” state) using a simple serial interface to a 12 bit shift register. A serial interface was chosen to eliminate the need for each output to have its own Output Enable pin, which would dramatically increase pin count and package cost. Common sources in a system that can be used to drive the 87972I-147 serial interface are FPGA’s and ASICs. PROTOCOL The Serial interface consists of two pins, FRZ_Data (Freeze Data) and FRZ_CLK (Freeze Clock). Each of the outputs which can be frozen has its own freeze enable bit in the 12 bit shift register. The sequence is started by supplying a logic “0” start bit followed by 12NRZ freeze enable bits. The period of each FRZ_DATA bit equals the period of the FRZ_CLK signal. The FRZ_DATA serial transmission should be timed so the 87972I-147 can sample each FRZ_DATA rt Sta it B QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC FRZ_CLK FRZ Clocked FRZ Latched Figure 5A. Freeze Data Input Protocol Qx FREEZE Internal Qx Internal Qx Out Figure 5B. Output Disable Timing Diagram ©2015 Integrated Device Technology, Inc 12 December 7, 2015 87972I-147 Datasheet Reliability Information Table 8. JA vs. Air Flow Table for a 52 Lead LQFP JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 47.1°C/W 42.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 42.3°C/W 36.4°C/W 34.0°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for 87972I-147: 8364 Pin Compatible with MPC972 ©2015 Integrated Device Technology, Inc 13 December 7, 2015 87972I-147 Datasheet Package Outline and Package Dimensions Package Outline - Y Suffix for 52 Lead LQFP Table 9. Package Dimensions for 52 Lead LQFP JEDEC Variation: BCC All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 52 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.22 0.38 c 0.09 0.20 D&E 12.00 Basic D1 & E1 10.00 Basic D2 & E2 7.80 Ref. e 0.65 Basic L 0.45 0.60 0.75  0° 7° ccc 0.10 Reference Document: JEDEC Publication 95, MS-026 ©2015 Integrated Device Technology, Inc 14 December 7, 2015 87972I-147 Datasheet Ordering Information Table 10. Ordering Information Part/Order Number 87972DYI-147LF 87972DYI-147LFT Marking ICS87972DI147L ICS87972DI147L ©2015 Integrated Device Technology, Inc Package “Lead-Free” 52 Lead LQFP “Lead-Free” 52 Lead LQFP 15 Shipping Packaging Tray Tape & Reel Temperature -40C to 85C -40C to 85C December 7, 2015 87972I-147 Datasheet Revision History Sheet Rev A A Table Page Description of Change T9 T10 1 10 11 14 15 Features Section - added leaf-free bullet. Added Recommendations for Unused Input/Output Pins section. Added LVCMOS to XTAL Interface section. Package Dimensions Table - added L and  dimensions. Ordering Information Table - added 52 Lead LQFP ordering information; corrected non-LF marking from ICS87972DYI147 to ICS87972DYI-147. 6/5/08 T10 15 Ordering Information - Removed leaded devices, shipping tape and reel quantity and the LF note below the table. Updated datasheet format. 12/7/15 ©2015 Integrated Device Technology, Inc Date 16 December 7, 2015 87972I-147 Datasheet ©2015 Integrated Device Technology, Inc 17 December 7, 2015 87972I-147 Datasheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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