Crystal-to-LVDS Clock Synthesizer
ICS844625I
DATA SHEET
General Description
Features
The ICS844625I is a high frequency clock generator. The
ICS844625I uses an external 25MHz crystal to synthesize
312.5MHz, 156.25MHz and 125MHz clocks. The ICS844625I has
excellent cycle-to-cycle and RMS period jitter performance.
•
•
Ten selectable differential LVDS outputs
•
Crystal oscillator interface designed for 18pF, 25MHz parallel
resonant crystal
•
•
Cycle-to-cycle jitter: 13ps (typical)
•
RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.387ps (typical), VDD = 3.3V
•
•
Output duty cycle: 50%, (typical)
•
•
-40°C to 85°C ambient operating temperature
The ICS844625I operates at full 3.3V, 2.5V or mixed 3.3V, 2.5V
supply modes and is available in a fully RoHS compliant 48-lead
TQFP, E-Pad package.
Output frequencies of 312.5MHz, 156.25MHz or 125MHz using a
25MHz crystal.
RMS phase jitter at 125MHz (1.875MHz - 20MHz):
0.417ps (typical), VDD = 3.3V
Supply modes:
VDD / VDDA / VDDO
3.3V / 3.3V / 3.3V
2.5V / 2.5V / 2.5V
3.3V / 3.3V / 2.5V
Available in lead-free (RoHS 6) package
Frequency Table for Bank A, B and C Outputs
Crystal Frequency (MHz)
Feedback Divider
VCO Frequency (MHz)
Output Divider
Output Frequency (MHz)
25
25
625
÷2
312.5
25
25
625
÷4
156.25
25
25
625
÷5
125
VDDO
nQC1
SELB1
GND
ICS844625I
ICS844625BYI REVISION A NOVEMBER 12, 2012
1
QA1
nQA1
QA2
nQA2
VDDO
GND
QA3
nQA3
QA4
nQA4
QA5
nQA5
VDDO
OEB
OEC
SELB0
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
5
48 Lead TQFP, E-Pad 32
6
31
7mm x 7mm x 1.0mm 30
7
package body
8
29
9
28
Y Package
10
27
Top View
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
QC1
nQC0
QC0
nc
VDDO
nQB1
QB1
nQB0
QB0
XTAL_IN
XTAL_OUT
GND
SELC0
SELC1
OEA
VDD
VDDO
VDD
REF_CLK
GND
BYPASS
MR
nc
SELA0
SELA1
VDDA
QA0
nQA0
Pin Assignment
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Block Diagram
OEA
Pullup
SELA[0:1]
Pulldown
BYPASS
Pulldown
REF_CLK
Pulldown
XTAL_IN
2
1
25MHz
Phase
Detector
OSC
÷2, ÷4, ÷5
VCO
625MHz
6
QA[0:5]
nQA[0:5]
0
XTAL_OUT
M = ÷25
MR
OEB
SELB[0:1]
Pulldown
Pullup
Pulldown
2
2
QB[0:1]
÷2, ÷4, ÷5
nQB[0:1]
2
÷2, ÷4, ÷5
SELC[0:1]
OEC
Pulldown
QC[0:1]
nQC[0:1]
2
Pullup
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
1,
2
XTAL_IN
XTAL_OUT
Type
Description
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
3, 12, 31, 46
GND
Power
Power supply pins.
4,
5
SELC0,
SELC1
Input
Pulldown
6
OEA
Input
Pullup
7, 48
VDD
Power
8
OEB
Input
Pullup
Active high output enable. When logic HIGH, Bank B outputs are enabled
and active. When logic LOW, the outputs are disabled and forced to
HIGH/LOW. LVCMOS/LVTTL interface levels.
9
OEC
Input
Pullup
Active high output enable. When logic HIGH, Bank C outputs are enabled
and active. When logic LOW, the outputs are disabled and forced to
HIGH/LOW. LVCMOS/LVTTL interface levels.
10,
11
SELB0,
SELB1
Input
Pulldown
13, 19, 24,
32, 37
VDDO
Power
Output supply pins.
14, 15
nQC1, QC1
Output
Differential output pair. LVDS interface levels.
16, 17
nQC0, QC0
Output
Differential output pair. LVDS interface levels.
18, 43
nc
Unused
No connect.
20, 21
nQB1, QB1
Output
Differential output pair. LVDS interface levels.
22, 23
nQB0, QB0
Output
Differential output pair. LVDS interface levels.
25, 26
nQA5, QA5
Output
Differential output pair. LVDS interface levels.
27, 28
nQA4, QA4
Output
Differential output pair. LVDS interface levels.
29, 30
nQA3, QA3
Output
Differential output pair. LVDS interface levels.
33, 34
nQA2, QA2
Output
Differential output pair. LVDS interface levels.
35, 36
nQA1, QA1
Output
Differential output pair. LVDS interface levels.
38, 39
nQA0, QA0
Output
Differential output pair. LVDS interface levels.
40
VDDA
Power
Analog supply pin.
41,
42
SELA1,
SELA0
Input
Pulldown
Selects the output divider value. See Table 3A.
LVCMOS/LVTTL interface levels.
44
MR
Input
Pulldown
Master Reset. LVCMOS/LVTTL interface levels.
45
BYPASS
Input
Pulldown
BYPASS signal allows to bypass the PLL. LVCMOS/LVTTL interface levels.
47
REF_CLK
Input
Pulldown
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects the output divider value. See Table 3C.
LVCMOS/LVTTL interface levels.
Active high output enable. When logic HIGH, Bank A outputs are enabled
and active. When logic LOW, the outputs are disabled and forced to
HIGH/LOW. LVCMOS/LVTTL interface levels.
Core supply pins.
Selects the output divider value. See Table 3B.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
Function Tables
Table 3A. SELA Function Table
Input
SELA0
SELA1
Bank A Output Divider
0
0
N/A
0
1
÷2
1
0
÷4
1
1
÷5
Table 3B. SELB Function Table
Input
SELB0
SELB1
Bank B Output Divider
0
0
N/A
0
1
÷2
1
0
÷4
1
1
÷5
Table 3C. SELC Function Table
Input
SELC0
SELC1
Bank C Output Divider
0
0
N/A
0
1
÷2
1
0
÷4
1
1
÷5
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, LVDS IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
29C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.31
2.5
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
101
125
mA
IDDA
Analog Supply Current
25
31
mA
IDDO
Output Supply Current
113
140
mA
Table 4B. LVDS Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
Analog Supply Voltage
VDD – 0.21
2.5
VDD
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
96
120
mA
IDDA
Analog Supply Current
17
21
mA
IDDO
Output Supply Current
95
128
mA
ICS844625BYI REVISION A NOVEMBER 12, 2012
Test Conditions
5
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Table 4C. LVDS Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.31
2.5
VDD
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
100
125
mA
IDDA
Analog Supply Current
25
31
mA
IDDO
Output Supply Current
112.5
140
mA
Typical
Maximum
Units
Table 4D. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High
Current
IIL
Input
Low
Current
Test Conditions
Minimum
VDD = 3.3V
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
REF_CLK, MR,
BYPASS, SELA[1:0],
SELB[1:0], SELC[1:0]
VDD = VIN = 3.465V or 2.625V
150
µA
OEA, OEB, OEC
VDD = VIN = 3.465V or 2.625V
5
µA
REF_CLK, MR,
BYPASS, SELA[1:0],
SELB[1:0], SELC[1:0]
VDD = 3.465V or 2.625V,
VIN = 0V
-5
µA
OEA, OEB, OEC
VDD = 3.465V or 2.625V,
VIN = 0V
-150
µA
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Table 4E. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
248
380
480
V
50
V
1.52
V
50
V
1.30
1.43
Table 4F. LVDS DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
205
329
420
V
50
V
1.50
V
50
V
1.00
1.15
Table 4G. LVDS DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
248
380
480
V
50
V
1.52
V
50
V
Maximum
Units
1.30
1.43
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
AC Electrical Characteristics
Table 6A. LVDS AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter (Random);
QAx = QBx = QCx
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Test Conditions
Minimum
Typical
Maximum
Units
Qx = ÷2
312.5
MHz
Qx = ÷4
156.25
MHz
Qx = ÷5
125
MHz
125MHz, (1.875MHz – 20MHz)
0.417
0.484
ps
156.25MHz, (1.875MHz – 20MHz)
0.387
0.429
ps
156.25MHz, (1MHz – 20MHz)
0.509
0.570
ps
312.5MHz, (1.875MHz – 20MHz)
0.335
0.410
ps
13
50
ps
fOUT = 312.5MHz, 20% to 80%
350
600
1200
ps
fOUT = 125MHz, 156.25MHz, 20% to 80%
400
700
1200
ps
fOUT = 312.5MHz
35
48
60
%
fOUT = 125MHz, 156.25MHz
45
50
55
%
100
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
Table 6B. LVDS AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
fOUT
Parameter
Output Frequency
tjit(Ø)
RMS Phase Jitter (Random);
QAx = QBx = QCx
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Test Conditions
Minimum
Typical
Maximum
Units
Qx = ÷2
312.5
MHz
Qx = ÷4
156.25
MHz
Qx = ÷5
125
125MHz, (1.875MHz – 20MHz)
0.498
0.633
MHz
ps
156.25MHz, (1.875MHz – 20MHz)
0.454
0.552
ps
156.25MHz, (1MHz – 20MHz)
0.646
0.768
ps
312.5MHz, (1.875MHz – 20MHz)
0.350
0.429
ps
13
50
ps
fOUT = 312.5MHz, 20% to 80%
350
600
1200
ps
fOUT = 125MHz, 156.25MHz, 20% to 80%
400
700
1200
ps
fOUT = 312.5MHz
35
48
60
%
fOUT = 125MHz, 156.25MHz
45
50
55
%
100
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Table 6C. LVDS AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter (Random);
QAx = QBx = QCx
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Test Conditions
Minimum
Typical
Maximum
Units
Qx = ÷2
312.5
MHz
Qx = ÷4
156.25
MHz
Qx = ÷5
125
MHz
125MHz, (1.875MHz – 20MHz)
0.413
0.480
ps
156.25MHz, (1.875MHz – 20MHz)
0.384
0.423
ps
156.25MHz, (1MHz – 20MHz)
0.505
0.568
ps
312.5MHz, (1.875MHz – 20MHz)
0.329
0.384
ps
13
50
ps
fOUT = 312.5MHz, 20% to 80%
350
600
1200
ps
fOUT = 125MHz, 156.25MHz, 20% to
80%
400
700
1200
ps
fOUT = 312.5MHz
35
48
60
%
fOUT = 125MHz, 156.25MHz
45
50
55
%
100
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Noise Power
dBc
Hz
Typical Phase Noise at 125MHz, LVDS Output (VDD = 3.3V, VDDO = 3.3V)
Offset Frequency (Hz)
Noise Power
dBc
Hz
Typical Phase Noise at 156.25MHz, LVDS Output (VDD = 3.3V, VDDO = 3.3V)
Offset Frequency (Hz)
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Noise Power
dBc
Hz
Typical Phase Noise at 156.25MHz, LVDS Output (VDD = 3.3V, VDDO = 3.3V)
Offset Frequency (Hz)
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Parameter Measurement Information
SCOPE
SCOPE
3.3V±5%
POWER SUPPLY
+ Float GND –
Qx
VDD,
VDDO
LVDS
VDDA
VDD,
VDDO
2.5V±5%
POWER SUPPLY
+ Float GND –
Qx
VDDA
nQx
nQx
3.3V Core/ 3.3V LVDS Output Load AC Test Circuit
2.5V Core/ 2.5V LVDS Output Load AC Test Circuit
Phase Noise Plot
3.3V±5%
VDD
Qx
Noise Power
2.5V±5%
SCOPE
VDDA
+ +
VDDO
–
POWER
SUPPLY
Float GND
nQx
Offset Frequency
f1
f2
RMS Phase Jitter =
1
* Area Under Curve Defined by the Offset Frequency Markers
2* *ƒ
3.3V Core/ 2.5V LVDS Output Load AC Test Circuit
RMS Phase Jitter
nQAx, nQBx, nQCx
nQAx,
nQBx,
nQCx
QAx, QBx, QCx
t PW
t
odc =
80%
80%
PERIOD
t PW
QAx,
QBx,
QCx
x 100%
VOD
20%
20%
t PERIOD
tR
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
ICS844625BYI REVISION A NOVEMBER 12, 2012
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tF
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Parameter Measurement Information, continued
VDD
VDD
out
out
DC Input
DC Input
LVDS
LVDS
100
out
VOS/Δ VOS
out
ä
Differential Output Voltage Setup
Offset Voltage Setup
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
REF_CLK Input
LVDS Outputs
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1k
resistor can be tied from the REF_CLK to ground.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 1A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 1B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS844625BYI REVISION A NOVEMBER 12, 2012
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©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
LVDS
Driver
standard termination schematic as shown in Figure 2A can be used
with either type of output structure. Figure 2B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
ZT
LVDS
Receiver
Figure 2A. Standard Termination
LVDS
Driver
ZO ZT
C
ZT
2 LVDS
ZT Receiver
2
Figure 2B. Optional Termination
LVDS Termination
ICS844625BYI REVISION A NOVEMBER 12, 2012
15
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
PIN
PIN PAD
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
Figure 3. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
ICS844625BYI REVISION A NOVEMBER 12, 2012
16
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Schematic Layout
Figure 4 shows an example ICS844625I application schematic in
which the device is operated at VDD = VDDA = 3.3V.3V and VDDO =
2.5V. The schematic example focuses on functional connections and
is intended as an example only and may not represent the exact user
configuration. Refer to the pin description and functional tables in the
datasheet to ensure the logic control inputs are properly set. For
example MR, BYPASS and the output enables, OE[A:C] can be
configured from an FPGA instead of pull up and pull down resistors
as shown.
This device package has an ePAD that is connected to ground
internally. The ePAD is to be connected to GND through vias in order
to improve heat dissipation.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise, so to achieve optimum jitter performance
isolation of the VDD pin from power supply is required. In order to
achieve the best possible filtering, it is recommended that the
placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, all the 0.1uf
capacitors associated with the VDD, VDDA and VDDO pins as well as
the 10 resistor of the VDDA filter must be placed on the device side
with direct return to the ground plane though vias. The remaining filter
components can be on the opposite side of the PCB.
There are two LVDS termination options shown as examples of valid
terminations.
1)
The standard 100 resistor termination of R2.
2)
An AC termination, used when coupling the ICS844625I LVDS
output stage to a different logic family receiver. Always check to
make sure LVDS p-p swing is sufficient to drive the receiver to
valid logic levels.
a)
If the receiver is HCSL, then the R6-R7 voltage divider is
set at the common mode center voltage of 0.35V.
b)
If the receiver is 1.5V CML, then R6 = 0 and R7 and C12
are not populated. Typically in this case, the termination
resistors, R3 and R4 are integrated into the receiver. In this
case only the external coupling caps, C13 and C14 are
necessary for the proper termination of the LVDS output.
ICS844625BYI REVISION A NOVEMBER 12, 2012
Power supply filter component recommendations are a general
guideline to be used for reducing external noise from coupling into
the devices. The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
17
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Logic Control Input Examples
VD D
Set Logic
Input to '1'
3.3V
Set Logic
Input to '0'
VD D
F B1
2
VD D
R U1
1K
BLM18BB221SN 1
RU 2
Not I nstall
R 5 10
C4
10uF
VD DA
To Logic
Input
pins
To Logic
Input
pins
R D1
N ot Inst all
1
C3
0.1uF
C5
10uF
2.5V
RD 2
1K
F B2
VD D O
2
1
BLM18BB221SN 1
C9
10uF
C8
0.1uF
VDD
C6
0. 1uF
C 11
0. 1uF
41
42
SELB1
SELB0
11
10
SELC1
SELC0
5
4
O EA
O EB
O EC
6
8
9
45
44
BYPASS
MR
40
SELA1
SELA0
SELB1
SELB0
C7
0 .1uF
VDD A
SELA1
SELA0
VDD
7
VD D
U1
48
VDD A
VD D O
VD D O
VD D O
SELC 1
SELC 0
VD D O
VD DO
13
19
C 18
0 .1uF
24
C17
0. 1uF
32
C 16
0.1uF
37
OEA
OEB
OEC
Place each 0.1uF bypass cap directly
adjacent to its corresponding VDD,
VDDA or VDDO pin.
C 15
0.1uF
VD D O
C 10
0 .1uF
BYPASS
MR
Z o = 50 O hm
3. 3V
Ro
=7 Ohm
QA0
nQA0
R1
QA1
nQA1
43
QA2
nQA2
LVC MO S D riv er
QA3
nQA3
Z o = 50 O hm
47
REF _C LK
QA4
nQA4
QA5
nQA5
39
38
Q A0
nQ A0
36
35
Q A1
nQ A1
34
33
Q A2
nQ A2
30
29
Q A3
nQ A3
28
27
Q A4
nQ A4
26
25
Q A5
nQ A5
23
22
Q B0
nQ B0
21
20
Q B1
nQ B1
-
LVDS R eceiv er
LVDS Terminations
C 13
1
25MH z ( 18pf )
XTAL_IN
QB0
nQB0
XTAL_OU T
QB1
nQB1
2
X1
C1
27pF
C2
33p F
Q C0
nQ C0
Q C1
nQ C1
18
43
+
R2
1 00
Z o = 50 O hm
Z o = 50 O hm
QC 1
0.1u
VDD _R eveiv er
R3
50
R6
17
16
Q C0
nQ C0
15
14
Q C1
nQ C1
R7
-
C 12
0. 01uF
R4
50
nc
nc
C 14
+
Receiv er
Z o = 50 O hm
ePAD
0.1u
49
3
12
31
46
GN D
GN D
GN D
GN D
nQ C 1
Alternate AC coupled LVDS Termination
(Select R6 and R7 to center the LVDS swing in the
common mode center of the Receiver.)
Figure 4. ICS844625I Application Schematic
ICS844625BYI REVISION A NOVEMBER 12, 2012
18
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844625I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS844625I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (125mA + 31mA) = 540.54mW
•
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 140mA = 485.1mW
Total Power_MAX = 540.54mW + 485.1mW = 1025.64mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 29°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.026W * 29°C/W = 114.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 48 Lead TQFP, E-Pad Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS844625BYI REVISION A NOVEMBER 12, 2012
0
1
2.5
29.0°C/W
22.6°C/W
21.1°C/W
19
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Reliability Information
Table 8. JA vs. Air Flow Table for a 48 Lead TQFP, E-Pad
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
29.0°C/W
22.6°C/W
21.1°C/W
Transistor Count
The transistor count for ICS844625I is: 3,716
ICS844625BYI REVISION A NOVEMBER 12, 2012
20
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - Y Suffix for 48 Lead TQFP, E-Pad
-HD VERSION
EXPOSED PAD DOWN
0.20 TAB
-TAB, EXPOSED PART OF CONNECTION BAR OR TIE BAR
Table 9. Package Dimensions for 48 Lead TQFP, E-Pad
Symbol
N
A
A1
A2
b
c
D&E
D1 & E1
D2 & E2
D3 & E3
e
L
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Minimum
Nominal
48
0.05
0.95
0.17
0.09
0.45
0°
0.10
1.00
0.22
9.00 Basic
7.00 Basic
5.50 Ref.
3.5
0.5 Basic
0.60
Maximum
1.20
0.15
1.05
0.27
0.20
0.75
7°
Reference Document: JEDEC Publication 95, MS-026
ICS844625BYI REVISION A NOVEMBER 12, 2012
21
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number
844625BYILF
844625BYILFT
Marking
ICS844625BIL
ICS844625BIL
ICS844625BYI REVISION A NOVEMBER 12, 2012
Package
“Lead-Free” 48 Lead TQFP, E-Pad
“Lead-Free” 48 Lead TQFP, E-Pad
22
Shipping Packaging
Tray
Tape & Reel
Temperature
-40C to 85C
-40C to 85C
©2012 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
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party owners.
Copyright 2012. All rights reserved.
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