8705I
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
Not Recommend for New Designs
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The 8705I is a highly versatile 1:8 Differential-to-LVCMOS/
LVTTL Clock Generator. The 8705I has two selectable clock
inputs. The CLK1, nCLK1 pair can accept most standard
differential input levels. The single ended CLK0 input accepts
LVCMOS or LVTTL input levels.The 8705I has a fully integrated
PLL and can be configured as zero delay buffer, multiplier
or divider and has an input and output frequency range of
15.625MHz to 250MHz. The reference divider, feedback divider
and output divider are each programmable, thereby allowing for
the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system test and
debug purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output dividers.
• Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs
• CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• CLK0 input accepts LVCMOS or LVTTL input levels
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: CLK0, 65ps (maximum)
CLK1, nCLK1, 55ps (maximum)
• Static Phase Offset: 25 ±125ps (maximum), CLK0
• Full 3.3V or 2.5V operating supply
• Lead-Free package available
• -40°C to 85°C ambient operating temperature
• Not Recommended for New Designs
For new designs, contact IDT.
BLOCK DIAGRAM
PIN ASSIGNMENT
32-Lead LQFP
7mm x 7mm x 1.4 mm
Y Package
Top View
8705I REVISION E 7/13/15
1
©2015 Integrated Device Technology, Inc.
8705I DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
SEL0, SEL1
Input
Pulldown
3
CLK0
Input
Pulldown Clock input. LVCMOS/LVTTL interface levels.
4
nc
5
CLK1
Input
6
nCLK1
Input
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
No connect.
7
CLK_SEL
Input
8
MR
Input
9, 32
VDD
Power
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Clock select input. When HIGH, selects differential CLK1, nCLK1. When
Pulldown
LOW, selects LVCMOS CLK0. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels
Core supply pins.
LVCMOS/LVTTL feedback input to phase detector for regenerating
Pulldown clocks with “zero delay”. Connect to one of the outputs.
LVCMOS/LVTTL interface levels.
Determines output divider values in Table 3.
Pulldown
LVCMOS/LVTTL interface levels.
10
FB_IN
Input
11
SEL2
Input
12, 16, 20, 24,
28
VDDO
Power
Output supply pins.
13, 15, 17, 19,
21, 23, 25, 27
Q0, Q1, Q2,
Q3, Q4, Q5,
Q6, Q7
Output
Clock output. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
14, 18, 22, 26
GND
Power
Power supply ground.
29
SEL3
Input
30
VDDA
Power
Analog supply pin.
Input
Selects between the PLL and reference clock as input to the dividers.
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
31
PLL_SEL
Pulldown
Pullup
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
KΩ
RPULLDOWN
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
51
KΩ
23
pF
CPD
ROUT
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
VDD, VDDA, VDDO = 3.465V
5
2
7
12
Ω
REVISION E 7/13/15
8705I DATA SHEET
TABLE 3A. PLL ENABLE FUNCTION TABLE
Outputs
PLL_SEL = 1
PLL Enable Mode
Inputs
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)
Q0:Q7
0
0
0
0
125 - 250
÷1
0
0
0
1
62.5 - 125
÷1
0
0
1
0
31.25 - 62.5
÷1
0
0
1
1
15.625 -31.25
÷1
0
1
0
0
125 - 250
÷2
0
1
0
1
62.5 - 125
÷2
0
1
1
0
31.25 - 62.5
÷2
0
1
1
1
125 - 250
÷4
1
0
0
0
62.5 - 125
÷4
1
0
0
1
125 - 250
÷8
1
0
1
0
62.5 - 125
x2
1
0
1
1
31.25 - 62.5
x2
1
1
0
0
15.625 - 31.25
x2
1
1
0
1
31.25 - 62.5
x4
1
1
1
0
15.625 - 31.25
x4
1
1
1
1
15.625 - 31.25
x8
TABLE 3B. PLL BYPASS FUNCTION TABLE
Outputs
PLL_SEL = 0
PLL Bypass Mode
Inputs
SEL3
SEL2
SEL1
SEL0
Q0:Q7
0
0
0
0
÷8
0
0
0
1
÷8
0
0
1
0
÷8
0
0
1
1
÷ 16
0
1
0
0
÷ 16
0
1
0
1
÷ 16
0
1
1
0
÷ 32
0
1
1
1
÷ 32
1
0
0
0
÷ 64
1
0
0
1
÷ 128
1
0
1
0
÷4
1
0
1
1
÷4
1
1
0
0
÷8
1
1
0
1
÷2
1
1
1
0
÷4
1
1
1
1
÷2
REVISION E 7/13/15
3
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
90
mA
IDDA
Analog Supply Current
15
mA
IDDO
Output Supply Current
20
mA
Maximum
Units
2
VDD + 0.3
V
2
VDD + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V
5
µA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
VIH
VIL
IIH
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
Test Conditions
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
CLK0
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
CLK0
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
PLL_SEL
IIL
VOH
Input
Low Current
Minimum
Typical
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
VDD = 3.465V, VIN = 0V
-5
µA
PLL_SEL
VDD = 3.465V, VIN = 0V
-150
µA
Output High Voltage; NOTE 1
2.6
VOL
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information section,
see “3.3V Output Load Test Circuit” figure.
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
4
V
0.5
V
REVISION E 7/13/15
8705I DATA SHEET
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
IIH
Input High Current
Test Conditions
CLK1
Minimum
nCLK1
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
-5
nCLK1
VDD = 3.465V, VIN = 0V
-150
Input Low Current
VPP
Peak-to-Peak Input Voltage
Maximum
Units
150
µA
VDD = VIN = 3.465V
CLK1
IIL
Typical
5
µA
µA
µA
0.15
1.3
V
VDD - 0.85
V
Maximum
Units
15.625
250
MHz
5
7
ns
5
7.3
ns
Common Mode Input Voltage;
GND + 0.5
NOTE 1, 2
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V.
VCMR
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
tpLH
Propagation Delay,
Low-to-High; NOTE 1
Test Conditions
CLK0
CLK1, nCLK1
CLK0
t(Ø)
tsk(o)
Static Phase Offset;
NOTE 2, 4
Output Skew;
NOTE 3, 4
CLK1, nCLK1
CLK0
Minimum
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 3.3V,
fREF ≤ 200MHz, Qx ÷ 1
PLL_SEL = 3.3V,
fREF ≤ 167MHz, Qx ÷ 1
PLL_SEL = 3.3V,
fREF = 200MHz, Qx ÷ 1
PLL_SEL = 0V
Typical
-100
25
150
ps
-15
+135
285
ps
-50
+100
250
ps
65
ps
55
45
ps
ps
1
mS
tjit(cc)
CLK1, nCLK1
Cycle-to-Cycle Jitter; NOTE 4
tL
PLL Lock Time
tR
Output Rise Time
400
950
ps
tF
Output Fall Time
400
950
ps
odc
Output Duty Cycle
43
57
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
%
REVISION E 7/13/15
PLL_SEL = 0V
fOUT > 40MHz
5
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I DATA SHEET
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
90
mA
IDDA
Analog Supply Current
15
mA
IDDO
Output Supply Current
20
mA
Maximum
Units
2
VDD + 0.3
V
2
VDD + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
VDD = VIN = 2.625V
150
µA
VDD = VIN = 2.625V
5
µA
TABLE 4E. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
VIH
VIL
IIH
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
Test Conditions
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
CLK0
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
CLK0
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
PLL_SEL
IIL
VOH
Input
Low Current
Minimum
Typical
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
VDD = 2.625V, VIN = 0V
-5
µA
PLL_SEL
VDD = 2.625V, VIN = 0V
-150
µA
Output High Voltage; NOTE 1
1.8
V
Output Low Voltage; NOTE 1
VOL
NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information section,
see “2.5V Output Load Test Circuit” figure.
0.5
V
Maximum
Units
150
µA
TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
IIH
Input High Current
Test Conditions
CLK1
Minimum
VDD = VIN = 2.625V
nCLK1
VDD = VIN = 2.625V
CLK1
VDD = 2.625V, VIN = 0V
-5
nCLK1
VDD = 2.625V, VIN = 0V
-150
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
Typical
5
0.15
Common Mode Input Voltage;
GND + 0.5
NOTE 1, 2
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V.
VCMR
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
6
µA
µA
µA
1.3
V
VDD - 0.85
V
REVISION E 7/13/15
8705I DATA SHEET
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
tpLH
Propagation Delay,
Low-to-High; NOTE 1
Test Conditions
CLK0
CLK1, nCLK1
CLK0
t(Ø)
tsk(o)
Static Phase Offset;
NOTE 2, 4
Output Skew;
NOTE 3, 4
CLK1, nCLK1
CLK0
Minimum
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 2.5V,
fREF ≤ 200MHz, Qx ÷ 1
PLL_SEL = 2.5V,
fREF = 133MHz, Qx ÷ 1
PLL_SEL = 2.5V,
fREF = 200MHz, Qx ÷ 1
PLL_SEL = 0V
Typical
Maximum
Units
15.625
250
MHz
5
7
ns
5
7.3
ns
-250
25
200
ps
-50
100
250
ps
-100
+100
300
ps
65
ps
55
45
ps
ps
±50
ps
1
mS
tjit(cc)
CLK1, nCLK1
Cycle-to-Cycle Jitter; NOTE 4
tjit(q)
Phase Jitter; NOTE 4, 5
tL
PLL Lock Time
tR
Output Rise Time
400
950
ps
tF
Output Fall Time
400
950
ps
odc
Output Duty Cycle
43
57
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Phase jitter is dependent on the input source used.
%
REVISION E 7/13/15
PLL_SEL = 0V
fOUT > 40MHz
PLL_SEL = 2.5V,
fREF = 66MHz, Qx * 2
7
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8
REVISION E 7/13/15
8705I DATA SHEET
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
PHASE JITTER & STATIC PHASE OFFSET
PROPAGATION DELAY
tPW, odc AND tPERIOD
REVISION E 7/13/15
9
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 8705I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
10
REVISION E 7/13/15
8705I DATA SHEET
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet
the VPP and VCMR input requirements. Figures 3A to 3D show
interface examples for theCLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for LVHSTL
drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
1.8V
3.3V
3.3V
3.3V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
nCLK
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
LVPECL
HiPerClockS
Input
R1
50
R2
50
R3
50
FIGURE 3A. CLK/nCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 3B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
R3
125
3.3V
R4
125
Zo = 50 Ohm
LVDS_Driv er
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
Zo = 50 Ohm
R2
84
FIGURE 3C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
REVISION E 7/13/15
HiPerClockS
Input
R2
50
FIGURE 3D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
11
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
nCLK
Receiv er
8705I DATA SHEET
LAYOUT GUIDELINE
The schematic of the 8705I layout example is shown in
Figure 4A. The 8705I recommended PCB board layout
for this example is shown in Figure 4B. This layout example is
used as a general guideline. The layout in the actual system will
R7
10 - 15
R1
SEL3
PLL_SEL
VDD
depend on the selected component types, the density of the
components, the density of the traces, and the stack up of the
P.C. board.
VDDA
43
Driv er_LVCMOS
R5
1K
VDD=3.3V or 2.5V
R4
1K
1
2
3
4
5
6
7
8
SEL0
SEL1
CLK0
nc
CLK1
nCLK1
CLK_SEL
MR
24
23
22
21
20
19
18
17
VDDO
Q5
GND
Q4
VDDO
Q3
GND
Q2
VDD
FB_IN
SEL2
VDDO
Q0
GND
Q1
VDDO
R4
SEL0
SEL1
Zo = 50
VDD
PLL_SEL
VDDA
SEL3
VDDO
Q7
GND
Q6
U1
Ro ~ 7 Ohm
VDD
C11
0.01u
ICS8705
9
10
11
12
13
14
15
16
VDD
Zo = 50
32
31
30
29
28
27
26
25
C16
10u
43
Logic Input Pin Examples
RU1
1K
Set Logic
Input to
'0'
VDD
Zo = 50
SEL2
Set Logic
Input to
'1'
VDD
R2
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
(U1-9)
VDD
(U1-12)
C2
0.1uF
C3
0.1uF
(U1-16)
43
(U1-20)
C4
0.1uF
C5
0.1uF
(U1-24)
C6
0.1uF
(U1-28)
C1
0.1uF
(U1-32)
C7
0.1uF
FIGURE 4A. 8705I LVCMOS CLOCK GENERATOR SCHEMATIC EXAMPLE
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
12
REVISION E 7/13/15
8705I DATA SHEET
trace and the trace delay might be restricted by the available
space on the board and the component location. While routing
the traces, the clock signal traces should be routed first and
should be locked prior to routing other signal traces.
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor
on the component side is preferred. This can reduce unwanted
inductance between the decoupling capacitor and the power
pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity
than other signals. Any ringing on the rising or falling edge or
excessive ring back can cause system failure. The shape of the
• The differential 50Ω output traces should have same
length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces
in parallel with the clock traces. If running parallel traces
is unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between
the clock trace pair.
• The series termination resistors should be located as
close to the driver pins as possible.
FIGURE 4B. PCB BOARD LAYOUT FOR 8705I
REVISION E 7/13/15
13
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I DATA SHEET
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 8705I is: 3126
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
14
REVISION E 7/13/15
8705I DATA SHEET
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
N
MAXIMUM
32
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
REVISION E 7/13/15
15
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I DATA SHEET
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8705BYILF
ICS8705BYILF
8705BYILFT
ICS8705BYILF
32 Lead “Lead Free” LQFP
tray
-40°C to 85°C
32 Lead “Lead Free” LQFP
tape & reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
16
REVISION E 7/13/15
8705I DATA SHEET
REVISION HISTORY SHEET
Rev
Table
Page
3A
3
PLL Enable Function Table - revised the Reference Frequency Range column
5A
5
3.3V AC Characteristics Table - updated the Output Frequency row from
275MHz Max. to 250MHz Max.
B
5B
Pin Description Table - revised power pin descriptions.
4/10/02
Pin Characteristics Table - added 23pF to CPD row.
7/15/02
2
B
2
2
B
1
C
D
1
4A & 4D
5A & 5B
T5B
T2
D
D
T8
T8
E
E
E
T8
REVISION E 7/13/15
4/5/02
2.5V AC Characteristics Table - updated the Output Frequency row from
275MHz Max. to 250MHz Max.
1
1
Date
7
B
B
Description of Change
2
2
Pin Description Table - Pin# 10 from description, replaced “Connect to pin 10.”
with “Connect to one of the outputs.”
Revised CLK0 description and MR description.
8
2
4&6
Revised Output Rise/Fall Time Diagram.
Pin Description table - revised MR and VDD descriptions.
Power Supply Table - changed VDD parameter to correspond with the pin description.
5&7
AC tables - Changed the Static Phase Offset limits for CLK1, nCLK1.
7
2.5V AC Characteristics Table - added Phase Jitter spec, and Note 5.
9
2
Replaced Static Phase Offset Diagram with Phase Jitter & SPO Diagram.
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
ROUT, added 5W min. and 12W max.
11
Added Differential Clock Input Interface section.
12 & 13 Added Layout Guideline and PCB Board Layout.
1
Added Lead-Free bullet to Features section.
16
Added Lead-Free part number to Ordering Information table.
Updated datasheet’s header/footer with IDT from ICS.
16
Removed “”ICS”” prefix from Part/Order Number column. Corrected packaging
18
column
Added Contact Page.
8/1/02
8/21/02
1/22/03
3/14/03
7/14/03
7/8/04
7/16/10
1
NRND - Nor Recommended For New Designs
5/30/13
16
Ordering Information - removed leaded devices.
Updated data sheet format
7/13/15
17
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
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