ICS8725-21
DIFFERENTIAL-TO-HSTL ZERO DELAY
CLOCK GENERATOR
General Description
Features
The ICS8725-21 is a highly versatile 1:1 Differentialto-HSTL Clock Generator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The CLK, nCLK pair can accept
most standard differential input levels. The
ICS8725-21 has a fully integrated PLL and can be configured as
zero delay buffer, multiplier or divider, and has an output frequency
range of 31.25MHz to 630MHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios: 8:1, 4:1,
2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to
achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal output
dividers.
•
One differential HSTL output pair
One differential feedback output pair
•
•
Differential CLK/nCLK input pair
•
•
•
•
Output frequency range: 31.25MHz to 630MHz
•
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
•
•
•
•
•
•
Cycle-to-cycle jitter: 35ps (maximum)
•
Industrial temperature information available upon request
ICS
Input frequency range: 31.25MHz to 630MHz
VCO range: 250MHz to630MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Output skew: 50ps (maximum)
Static phase offset: 30ps ± 125ps
3.3V core, 1.8V output operating supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
PLL_SEL Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
CLK Pulldown
nCLK Pullup
0
1
Q
nQ
QFB
nQFB
PLL
FB_IN Pulldown
nFB_IN Pullup
CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
CLK
nCLK
MR
VDD
nFB_IN
FB_IN
SEL2
GND
nQFB
QFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
VDDO
Q
nQ
ICS8725-21
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
SEL0 Pulldown
SEL1 Pulldown
SEL2 Pulldown
SEL3 Pulldown
MR Pulldown
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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ICS8725-21
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
Type
1
CLK
Input
Pulldown
2
nCLK
Input
Pullup
Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q and QFB to go low and the inverted outputs nQ and
nQFB to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
3
MR
Input
4, 17
VDD
Power
5
nFB_IN
Input
Pullup
6
FB_IN
Input
Pulldown
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.” Connect to pin 10.
7, 14,
18, 19
SEL2, SEL3,
SEL0 SEL1
Input
Pulldown
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Core supply pins.
Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.” Connect to pin 9.
8
GND
Power
Power supply ground.
9, 10
nQFB, QFB
Output
Differential feedback output pair. HSTL interface levels.
11, 12
nQ/Q
Output
Differential output pair. HSTL interface levels.
13
VDDO
Power
Output supply pin.
15
VDDA
Power
Analog supply pin.
16
PLL_SEL
Input
20
nc
Unused
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
No connect.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
Test Conditions
2
Minimum
Typical
Maximum
Units
ICS8725AM-21 REV. A FEBRUARY 27, 2008
ICS8725-21
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)*
Q/nQ
0
0
0
0
250 - 630
÷1
0
0
0
1
125 - 315
÷1
0
0
1
0
62.5 - 157.5
÷1
0
0
1
1
31.25 - 78.75
÷1
0
1
0
0
250 - 630
÷2
0
1
0
1
125 - 315
÷2
0
1
1
0
62.5 - 157.5
÷2
0
1
1
1
31.25 - 78.75
÷4
1
0
0
0
125 - 315
÷4
1
0
0
1
250 - 630
÷8
1
0
1
0
125 - 315
x2
1
0
1
1
62.5 - 157.5
x2
1
1
0
0
31.25 - 78.75
x2
1
1
0
1
62.5 - 157.5
x4
1
1
1
0
31.25 - 78.75
x4
1
1
1
1
31.25 - 78.75
x8
*NOTE: VCO frequency range for all configurations above is 250MHz to 630MHz.
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q/nQ, QFB/nQFB
0z
0
0
0
÷4
0
0
0
1
÷4
0
0
1
0
÷4
0
0
1
1
÷8
0
1
0
0
÷8
0
1
0
1
÷8
0
1
1
0
÷16
0
1
1
1
÷16
1
0
0
0
÷32
1
0
0
1
÷64
1
0
1
0
÷2
1
0
1
1
÷2
1
1
0
0
÷4
1
1
0
1
÷1
1
1
1
0
÷2
1
1
1
1
÷1
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
46.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
1.6
1.8
2.0
V
IDD
Power Supply Current
137
mA
IDDA
Analog Supply Current
17
mA
IDDO
Output Supply Current
0
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
SEL[0:3], MR
VDD = VIN = 3.465V
150
µA
PLL_SEL
VDD = VIN = 3.465V
5
µA
SEL[0:3], MR
VDD = 3.465V, VIN = 0V
-5
µA
PLL_SEL
VDD = 3.465V, VIN = 0V
-150
µA
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Table 4C. Differential DC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C
Symbol
Parameter
IIH
Input High Current
IIL
Test Conditions
Minimum
Typical
Maximum
Units
CLK, FB_IN
VDD = VIN = 3.465V
150
µA
nCLK, nFB_IN
VDD = VIN = 3.465V
5
µA
CLK, FB_IN
VDD = 3.465V,
VIN = 0V
-5
µA
nCLK, nFB_IN
VDD = 3.465V,
VIN = 0V
-150
µA
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. HSTL DC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Minimum
Typical
Maximum
Units
1.0
1.4
V
Output Low Voltage; NOTE 1
0
0.4
V
VOX
Output Crossover Voltage; NOTE 2
40
60
%
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.1
V
NOTE 1: Outputs termination with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Table 5. Input Frequency Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C
Symbol
Parameter
FIN
Input Frequency
Test Conditions
Minimum
PLL_SEL = 1
31.25
Typical
Maximum
Units
630
MHz
630
MHz
CLK, nCLK
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
PLL_SEL = 0
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C
Parameter
Symbol
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
tsk(Ø)
Static Phase Offset; NOTE 2, 5
tsk(o)
Output Skew; NOTE 3, 5
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 5, 6
tjit(θ)
Phase Jitter; NOTE 4, 5, 6
tL
PLL Lock Time
tR / tF
Output Rise/Fall Time
tPW
Output Pulse Width
Test Conditions
Minimum
PLL_SEL = 0V, f ≤ 700MHz
3.2
PLL_SEL = 3.3V
-95
Typical
30
PLL_SEL = 0V
20% to 80%
300
tPERIOD/2 - 85
tPERIOD/2
Maximum
Units
630
MHz
4.5
ns
155
ps
50
ps
35
ps
±50
ps
1
ms
700
ps
tPERIOD/2 + 85
ps
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked
and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information
3.3V±5%
1.8V±0.2V
VDD
VDD,
VDDA
Qx
SCOPE
nCLK
VDDO
V
Cross Points
PP
HSTL
V
CMR
CLK
nQx
GND
GND
GND = 0V
Differential Input Level
3.3V Core/1.8V Output Load AC Test Circuit
nCLK
VOH
CLK
VOL
nQ, nQFB
nQx
Qx
VOH
VOL
Q, QFB
nQy
➤
➤ t(Ø)
tjit(Ø) = t(Ø) – t(Ø) mean= Phase Jitter
t(Ø) mean = Static Phase Offset
Qy
tsk(o)
Where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on the controlled edges)
Output Skew
Phase Jitter and Static Phase Offset
nQ, nQFB
nQ, nQFB
Q, QFB
Q, QFB
VDDO
2
VDDO
2
VDDO
2
Pulse Width
➤
tcycle n
➤
tcycle n+1
➤
t PERIOD
➤
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
Output Pulse Width
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ICS8725AM-21 REV. A FEBRUARY 27, 2008
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information, continued
nCLK
80%
80%
CLK
VSW I N G
Clock
Outputs
nQ, nQFB
20%
20%
tR
tF
Q, QFB
tPD
Propagation Delay
Output Rise/Fall Time
Application Information
Power Supply Filtering Technique
To achieve optimum jitter performance, power supply isolation is
required. The ICS8725-21 provides separate power supplies to
isolate any high switching noise from the outputs to the internal
PLL. VDD, VDDA and VDDO should be individually connected to the
power supply plane through vias, and 0.01µF bypass capacitors
should be used for each pin. Figure 1 illustrates this for a generic
VDD pin and also shows that VDDA requires that an additional 10Ω
resistor along with a 10µF bypass capacitor be connected to the
VDDA pin. The 10Ω resistor can also be replaced by a ferrite bead.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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ICS8725AM-21 REV. A FEBRUARY 27, 2008
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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ICS8725AM-21 REV. A FEBRUARY 27, 2008
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
nCLK
HiPerClockS
Input
LVHSTL
R1
50
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
LVPECL
R2
50
R1
50
R2
50
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
Zo = 50Ω
nCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
nCLK
Zo = 50Ω
Receiver
LVDS
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
2.5V
*R3
33
R3
120
Zo = 50Ω
R4
120
Zo = 60Ω
CLK
CLK
Zo = 50Ω
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
33
R1
50
R2
50
HiPerClockS
Input
HiPerClockS
SSTL
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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ICS8725AM-21 REV. A FEBRUARY 27, 2008
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Schematic Example
Figure 4 shows a schematic example of the ICS8725-21. In this
example, the input is driven by an HCSL driver. The zero delay
buffer is configured to operate at 155.52MHz input and 77.75MHz
output. The logic control pins are configured as follows:
SEL[3:0] = 0101
PLL_SEL = 1
(155.5 MHz)
3.3V
VDD
Zo = 50 Ohm
SEL2
HCSL
R8
50
R9
50
R1
50
VDD
RU4
1K
RU5
SP
RU6
1K
RD4
SP
RD5
1K
RD6
SP
CLK
nCLK
MR
VDD
nFB_IN
FB_IN
SEL2
GND
nQFB
QFB
nc
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
VDDO
Q
nQ
R2 ICS8725-21
50
20
19
18
17
16
15
14
13
12
11
C11
0.01u
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
VDDO
Zo = 50 Ohm
(77.75 MHz)
RD7
1K
10
C16
10u
Zo = 50 Ohm
C3
0.1uF
VDD=3.3V
VDD
+
RU7
SP
PLL_SEL
SEL0
SEL1
SEL2
SEL3
RD3
SP
1
2
3
4
5
6
7
8
9
10
R7
VDDA
U1
Zo = 50 Ohm
RU3
1K
For ICS8725-21, the decoupling capacitors should be physically
located near the power pin.
LVHSTL_input
R4
50
R5
50
Bypass capacitors located
near the power pins
VDDO=1.8V
SEL[3:0] = 0101,
Divide by 2
(U1-4) VDD
C1
0.1uF
(U1-17)
C2
0.1uF
SP = Space (i.e. not intstalled)
Figure 4. ICS8725-21 HSTL Buffer Schematic Example
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8725-21.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8725-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX)= 3.465V * (137mA + 17mA) = 533.6mW
•
Power (outputs)MAX = 32.8mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 533.6mW + 32.8mW = 566.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.566W * 39.7°C/W = 111°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7. Thermal Resistance θJA for 20 Lead SOIC, Forced Convection
θJA vs. Air Flow
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
Linear Feet per Minute
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 5.
VDD
Q1
VOUT
RL
50Ω
Figure 5. HSTL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /RL) * (VDDO_MAX - VOH_MAX)
Pd_L = (VOL_MAX /RL) * (VDDO_MAX - VOL_MAX)
Pd_H = (1.0V/50Ω) * (2V - 1.0V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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Reliability Information
Table 8. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA vs. Air Flow
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
Linear Feet per Minute
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS8725-21 is: 2969
Package Outline and Package Dimensions
Package Outline - M Suffix for 20 Lead SOIC
Table 9. Package Dimensions for 20 Lead SOIC
300 Millimeters
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
20
A
2.65
A1
0.10
A2
2.05
2.55
B
0.33
0.51
C
0.18
0.32
D
12.60
13.00
E
7.40
7.60
e
1.27 Basic
H
10.00
10.65
h
0.25
0.75
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-013, MS-119
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Ordering Information
Table 10. Ordering Information
Part/Order Number
ICS8725AM-21
ICS8725AM-21T
ICS8725AM-21LF
ICS8725AM-21LFT
Marking
ICS8725AM-21
ICS8725AM-21
ICS8725AM-21LF
ICS8725AM-21LF
Package
20 Lead SOIC
20 Lead SOIC
“Lead-Free” 20 Lead SOIC
“Lead-Free” 20 Lead SOIC
Shipping Packaging
Tube
1000 Tape & Reel
Tube
1000 Tape & Reel
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev
Table
Page
A
T10
14
Ordering Information Table - added Lead-Free marking and note.
6/9/05
A
T1
2
8
Pin Descriptions Table - corrected MR description.
Added Recommendations for Unused Input and Output Pins.
5/22/06
11
12
Updated Differential Clock Input Interface section.
Updated Schematic Example section.
2/27/08
A
Description of Change
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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Date
ICS8725AM-21 REV. A FEBRUARY 27, 2008
ICS8725-21
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
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