PRELIMINARY
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/
CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET
General Description
Features
The ICS8743004I is Zero-Delay Buffer/Frequency
Multiplier with four differential LVDS or LVPECL
HiPerClockS™
output pairs (pin selectable output type), and uses
external feedback for “zero delay” clock
regeneration. In PCI Express and Ethernet
applications, 100MHz and 125MHz are the most commonly used
reference clock frequencies and each of the four output pairs can
be independently set for either 100MHz or 125MHz. With an
output frequency range of 98MHz to 165MHz, the device is also
suitable for use in a variety of other applications such as Fibre
Channel (106.25MHz) and XAUI (156.25MHz). The M-LVDS
Input/Output pair is useful in backplane applications when the
reference clock can either be local (on the same board as the
ICS8743004I) or remote via a backplane connector. In output
mode, an input from a local reference clock applied to the
CLK/nCLK input pins is translated to M-LVDS and driven out to the
MLVDS/nMLVDS pins. In input mode, the internal M_LVDS driver
is placed in Hi-Z state using the OE_MLVDS pin and
MLVDS/nMLVDS pin then becomes an input (e.g. from a
backplane).
•
Four differential output pairs with selectable pin type: LVDS or
LVPECL. Each output pair is individually selectable for 100MHz
or 125MHz (for PCIe and Ethernet applications).
•
One differential clock input pair CLK/nCLK can accept the
following differential input levels: LVPECL, LVDS, M-LVDS,
LVHSTL, HCSL
•
•
•
•
•
•
•
One M-LVDS I/O (MLVDS/nMLVDS)
•
•
•
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
ICS
Output frequency range: 98MHz - 165MHz
Input frequency range: 19.6MHz - 165MHz
VCO range: 490MHz - 660MHz
PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
External feedback for “zero delay” clock regeneration
RMS phase jitter @ 125MHz (1.875MHz – 20MHz):
0.57ps (typical)
Available in lead-free (RoHS 6) packages
The ICS8743004I uses very low phase noise FemtoClock™
technology, thus making it ideal for such applications as PCI
Express Generation 1 and 2 as well as for Gigabit Ethernet, Fibre
Channel, and 10 Gigabit Ethernet. It is packaged in a 40-VFQFN
package (6mm x 6mm).
nQ1
nQ0
Q1
VDDA
VDDO
Q0
CLK
nCLK
PDIV0
PDIV1
Pin Assignment
VDD
1
40 39 38 37 36 35 34 33 32 31
30
OE_MLVDS
2
29
Q2
VDDO
MLVDS
3
28
nQ2
nMLVDS
4
27
GND
PLL_SEL
5
26
Q3
FBO_DIV
MR
6
25
nQ3
7
24
FBOUT
OE0
8
nFBOUT
OE1
9
23
22
GND
10
21
Q_TYPE
VDDO
QDIV3
QDIV1
QDIV2
QDIV0
GND
FBIN
nFBIN
FBI_DIV1
VDD
FBI_DIV0
11 12 13 14 15 16 17 18 19 20
ICS8743004I
40-Lead VFQFN
6mm x 6mm x 0.925mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 1
ICS8743004DKI REV. A AUGUST 25, 2008
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Block Diagram
2
OE1:0 (PU, PU)
QDIV0 (PD)
PDIV1 (PD)
PDIV0 (PD)
CLK (PD)
nCLK (PU/PD)
QDIV0
0 ÷4 (default)
1 ÷5
PDIV1:0
00 ÷4 (default)
01 ÷5
10 ÷8
11 ÷1
MR (PD)
0
MLVDS
QDIV1
0 ÷4 (default)
1 ÷5
Q1
nQ1
QDIV2 (PD)
nMLVDS
PD
VCO
490-660 MHz
1
FBI_DIV1 (PU)
QDIV2
0 ÷4 (default)
1 ÷5
Q2
nQ2
QDIV3 (PD)
FBI_DIV0 (PU)
nFBIN (PU/PD)
nQ0
QDIV1 (PD)
OE_MLVDS (PU)
FBIN (PD)
Q0
FBI_DIV1:0
00 ÷1
01 ÷2
10 ÷4
11 ÷5 (default)
QDIV3
0 ÷4 (default)
1 ÷5
Q3
nQ3
FBO_DIV (PD)
PLL_SEL (PU)
MR (PD)
FBO_DIV
0 ÷4 (default)
1 ÷5
FBOUT
nFBOUT
Q_TYPE (PD)
PU means internal pull-up resistor on pin (power-up default is HIGH if not externally driven)
PD means internal pull-down resistor on pin (power-up default is LOW if not externally driven)
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 2
ICS8743004DKI REV. A AUGUST 25, 2008
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Table 1. Pin Descriptions
Number
Name
1, 11
VDD
2
3
4
OE_MLVDS
MLVDS
nMLVDS
Type
Description
Power
Core supply pins.
Input
Active High Output Enable. When HIGH, the M-LVDS output driver is active
and provides a buffered copy of reference clock applied the CLK/nCLK input
to the MLVDS/nMLVDS output pins. The MLVDS/nMLVDS frequency equals
the CLK/ nCLK frequency divided by the PDIV Divider value (selectable ÷1,
÷4, ÷5, ÷8). When LOW, the M-LVDS output driver is placed into a Hi-Z state
and the MLVDS/nMLVDS pins can accept a differential input.
LVCMOS/LVTTL interface levels.
Pullup
I/O
Non-Inverting M-LVDS input/output. The input/output state is determined by
the OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and
drives the non-inverting M-LVDS output. When OE_MLVDS = LOW, this pin
is an input and can accept the following differential input levels: M-LVDS,
LVDS, LVPECL, HSTL, HCSL.
I/O
Inverting M-LVDS input/output. The input/output state is determined by the
OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives
the inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input
and can accept the following differential input levels: M-LVDS, LVDS,
LVPECL, HSTL, HCSL. The output driver is always M-LVDS and is not
affected by the state of the Q-TYPE pin which affects Q0/nQ0:Q3/nQ3, and
FBOUT/nFBOUT.
PLL select. Determines if the PLL is in bypass or enabled mode (default). In
enabled mode, the output frequency = VCO frequency/QDIV divider. In
bypass mode, the output frequency = reference clock frequency/
(PDIV*QDIV). LVCMOS/LVTTL interface levels.
5
PLL_SEL
Input
Pullup
6
FBO_DIV
Input
Pulldown
Output Divider Control for the feedback output pair, FBOUT/nFBOUT.
Determines if the output divider = ÷4 (default), or ÷5.
LVCMOS/LVTTL interface levels.
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the Qx/nQx outputs to drive Hi-Z. Note that assertion of MR overrides
the OE[0:2] control pins and all outputs are disabled. When logic LOW, the
internal dividers are enabled and the state of the outputs is determined by
OE[0:2]. MR must be asserted on power-up to ensure outputs phase aligned.
LVCMOS/LVTTL interface levels.
Pullup
Output Enable. Together with OE1, determines the output state of the outputs
with the default state: all output pairs switching. When an LVDS or LVPECL
output pair is disabled, the disable state is Qx/nQx = Hi-Z. It should also be
noted that the feedback output pins (FBOUT/nFBOUT) are always switching
and are not affected by the state of OE[0:1]. Refer to table 3B for truth table.
LVCMOS/LVTTL Interface levels.
Pullup
Output Enable. Together with OE0, determines the output state of the outputs
with the default state: all output pairs switching. When an LVDS or LVPECL
output pair is disabled, the disable state is Qx/nQx = Hi-Z. It should also be
noted that the feedback output pins (FBOUT/nFBOUT) are always switching
and are not affected by the state of OE[1:0]. Refer to table 3B for truth table.
LVCMOS/LVTTL Interface levels
Pullup
7
8
MR
OE0
Input
Input
9
OE1
Input
10, 16, 27
GND
Power
Power supply ground.
Input
Feedback Input Divide Select 0. Together with FB_DIV1, determines the
feedback input divider value. LVCMOS/LVTTL interface levels.
12
FBI_DIV0
Pin Descriptions continue on the next page.
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 3
ICS8743004DKI REV. A AUGUST 25, 2008
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
Type
PRELIMINARY
Number
Name
Description
13
FBI_DIV1
Input
Pullup
14
nFBIN
Input
Pullup/
Pulldown
Inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
15
FBIN
Input
Pulldown
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.”
17
QDIV0
Input
Pulldown
Output Divider Control for Q0/nQ0. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
18
QDIV1
Input
Pulldown
Output Divider Control for Q1/nQ1. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
19
QDIV2
Input
Pulldown
Output Divider Control for Q2/nQ2. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
20
QDIV3
Input
Pulldown
Output Divider Control for Q3/nQ3. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
Pulldown
Output Type Select. 0 = LVDS outputs (default); 1 = LVPECL outputs on
Q0/nQ0:Q3/nQ3, and FBOUT/nFBOUT. The MLVDS/nMLVDS driver is
always M-LVDS and is NOT affected by the state of this pin.
LVCMOS/LVTTL interface levels.
Feedback Input Divide Select 1. Together with FB_DIV0, determines the
feedback input divider value. LVCMOS/LVTTL interface levels.
21
Q_TYPE
Input
22, 30, 35
VDDO
Power
Output supply pins.
23,
24
nFBOUT
FBOUT
Output
Differential feedback output pair. The feedback output pair always switches
independent of the output enable settings on the OE[1:0] pins.
LVDS or LVPECL interface levels.
25, 26
nQ3/Q3
Output
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
28, 29
nQ2/Q2
Output
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
31, 32
nQ1/Q1
Output
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
33, 34
nQ0/Q0
Output
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
36
VDDA
Power
Analog supply pin.
37
CLK
Input
Pulldown
Non-inverting differential clock input.
Accepts HCSL, LVDS, M-LVDS, HSTL input levels.
38
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input.
Accepts HCSL, LVDS, M-LVDS, HSTL input levels.
39
PDIV0
Input
Pulldown
Input Divide Select 0. Together with PDIV1 determines the input divider
value. LVCMOS/LVTTL Interface levels.
40
PDIV1
Input
Pulldown
Input Divide Select 1. Together with PDIV0 determines the input divider
value. LVCMOS/LVTTL Interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 4
ICS8743004DKI REV. A AUGUST 25, 2008
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
Function Tables
Table 3A. Common Configuration Table (not exhaustive) NOTE 1
Input
Frequency
Output
Frequency
Application
Frequency
Mult. Factor
PDIV
FBI_DIV
FBO_DIV
QDIVx
100MHz
100MHz
PCIe Buffer
1
÷1
÷1
÷5
÷5
125MHz
125MHz
PCIe, Ethernet Buffer
1
÷1
÷1
÷4
÷4
100MHz
125MHz
PCIe Multiplier
5/4
÷1
÷1
÷5
÷4
125MHz
100MHz
PCIe Divider
4/5
÷1
÷1
÷4
÷5
25MHz
100MHz
PCIe Multiplier
4
÷1
÷4
÷5
÷5
25MHz
125MHz
PCIe, Ethernet Multiplier
5
÷1
÷4
÷5
÷4
25MHz
156.25MHz
25/4
÷1
÷5
÷5
÷4
62.5MHz
125MHz
Ethernet Multiplier
2
÷1
÷2
÷4
÷4
53.125MHz
106.25MHz
Fibre Channel Multiplier
2
÷1
÷2
÷5
÷5
XAUI Multiplier
NOTE 1: This table shows more common configurations and is not exhaustive. When using alternate configurations, the designer must
ensure the VCO frequency is always within its range of 490MHz – 660MHz.
Table 3B. Output Enable Truth Table
Inputs
State
OE1
OE0
Q[0:3] /nQ[0:3]
0
0
Q0/nQ0 switching, Q1/nQ1, Q2/nQ2, Q3/nQ3 disabled (Qx/nQx = Hi-Z)
0
1
Q0/nQ0, Q1/nQ1 switching, Q2/nQ2, Q3/nQ3 disabled (Qx/nQx = Hi-Z)
1
0
Q0/nQ0, Q1/nQ1, Q2/nQ2 switching, Q3/nQ3 disabled (Q3/nQ3 = Hi-Z)
1
1
All output pairs switching (default)
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 5
ICS8743004DKI REV. A AUGUST 25, 2008
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuos Current
Surge Current
10mA
15mA
Outputs, IO (LVPECL)
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
32.4°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.18
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
140
mA
IDDA
Analog Supply Current
18
mA
IDDO
Output Supply Current
140
mA
Table 4B. LVPECL Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.19
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
240
mA
IDDA
Analog Supply Current
19
mA
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 6
ICS8743004DKI REV. A AUGUST 25, 2008
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Test Conditions
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
PDIV[0:1], QDIV[0:3],
MR, FBO_DIV, Q_TYPE
VDD = VIN = 3.465V
150
µA
OE_MLVDS, OE[0:1],
FBI_DIV[0:1], PLL_SEL
VDD = VIN = 3.465V
5
µA
PDIV[0:1], QDIV[0:3],
MR, FBO_DIV, Q_TYPE
VDD = 3.465V, VIN = 0V
-5
µA
OE_MLVDS, OE[0:1],
FBI_DIV[0:1], PLL_SEL
VDD = 3.465V, VIN = 0V
-150
µA
Input High Current
Input Low Current
Table 4D. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
IIH
Input High Current
IIL
Test Conditions
CLK/nCLK,
FBIN/nFBIN
Minimum
Typical
VDD = VIN = 3.465V
Maximum
Units
150
µA
CLK, FBIN
VDD = 3.465V,
VIN = 0V
-5
µA
nCLK, nFBIN
VDD = 3.465V,
VIN = 0V
-150
µA
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4E. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VOD
Differential Output Voltage
360
mV
∆VOD
VOD Magnitude Change
20
mV
VOS
Offset Voltage
1.31
V
∆VOS
VOS Magnitude Change
25
mV
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 7
Minimum
Typical
Maximum
Units
ICS8743004DKI REV. A AUGUST 25, 2008
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Table 4F. M-LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOD
Differential Output Voltage
440
mV
∆VOD
VOD Magnitude Change
50
mV
VOS
Offset Voltage
1.6
V
∆VOS
VOS Magnitude Change
50
mV
ISC
Output Short Circuit Current
48
mA
Table 4G. LVPECL DC Characteristics, VDD = VDDO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Current; NOTE 1
VOL
Output Low Current; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VDDO – 1.4
VDDO – 0.9
µA
VDDO – 2.0
VDDO – 1.7
µA
0.6
1.0
V
NOTE 1: Outputs termination with 50Ω to VDDO – 2V.
AC Electrical Characteristics
Table 5A. LVDS AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Parameter
Symbol
fMAX
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
25
ps
tsk(o)
Output Skew; NOTE 2
60
ps
125MHz, Integration Range:
1.875MHz – 20MHz
0.65
ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
100MHz, Integration Range:
1.875MHz – 20MHz
0.73
ps
125MHz, (1.2MHz – 21.9MHz),
106 samples
13.49
ps
125MHz
1.29
ps
20% to 80%
600
ps
50
%
tj
Phase Jitter Peak-to-Peak;
NOTE 4
tREFCLK_HF_RMS Phase Jitter RMS; NOTE 5
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
98
Maximum
Units
160
MHz
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential cross points.
NOTE 3: Please refer to the Phase Noise plots.
NOTE 4: RMS jitter after applying system transfer function. See IDT Application Note PCI Express Reference Clock Requirements.
Maximum limit for PCI Express is 86ps peak-to-peak.
NOTE 5: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and
5-16MHz. See IDT Application Note PCI Express Reference Clock Requirements. Maximum limit for PCI Express Generation 2 is 3.1ps
rms.
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 8
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Table 5B. LVPECL AC Characteristics, VDD = VDDO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Parameter
Symbol
fMAX
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tsk(o)
Output Skew; NOTE 2
tjit(Ø)
tj
RMS Phase Jitter (Random);
NOTE 3
Phase Jitter Peak-to-Peak;
NOTE 4
tREFCLK_HF_RMS Phase Jitter RMS; NOTE 5
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
98
Maximum
Units
160
MHz
25
ps
60
ps
125MHz, Integration Range:
1.875MHz – 20MHz
0.57
ps
100MHz, Integration Range:
1.875MHz – 20MHz
0.69
ps
125MHz, (1.2MHz – 21.9MHz),
106 samples
13.49
ps
125MHz
1.29
ps
20% to 80%
600
ps
50
%
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential cross points.
NOTE 3: Please refer to the Phase Noise plots.
NOTE 4: RMS jitter after applying system transfer function. See IDT Application Note PCI Express Reference Clock Requirements.
Maximum limit for PCI Express is 86ps peak-to-peak.
NOTE 5: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and
5-16MHz. See IDT Application Note PCI Express Reference Clock Requirements. Maximum limit for PCI Express Generation 2 is 3.1ps
rms.
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 9
ICS8743004DKI REV. A AUGUST 25, 2008
ICS8743004I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Typical LVDS Phase Noise at 125MHz
➝
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.65ps (typical)
Raw Phase Noise Data
➝
➝
Noise Power
dBc
Hz
Ethernet Filter
Phase Noise Result by adding
an Ethernet filter to raw data
Offset Frequency (Hz)
Typical LVDS Phase Noise at 100MHz
➝
100MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.73ps (typical)
Raw Phase Noise Data
➝
➝
Noise Power
dBc
Hz
10Gb Ethernet Filter
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
Offset Frequency (Hz)
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 10
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Typical LVPECL Phase Noise at 125MHz
➝
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.57ps (typical)
Raw Phase Noise Data
➝
➝
Noise Power
dBc
Hz
Ethernet Filter
Phase Noise Result by adding
an Ethernet filter to raw data
Offset Frequency (Hz)
Typical LVPECL Phase Noise at 100MHz
➝
100MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.69ps (typical)
Raw Phase Noise Data
➝
➝
Noise Power
dBc
Hz
10Gb Ethernet Filter
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
Offset Frequency (Hz)
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 11
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Parameter Measurement Information
SCOPE
3.3V±5%
POWER SUPPLY
+ Float GND –
VDDO
V
SCOPE
Qx
VDD,
DDA
3.3V±5%
POWER SUPPLY
+ Float GND –
LVDS
nQx
3.3V LVDS Output Load AC Test Circuit
VDD,
VDDO
Qx
VDDA
M-LVDS
nQx
3.3V M-LVDS Output Load AC Test Circuit
2V
2V
VDD
VDD,
VDDO V
DDA
Qx
SCOPE
nCLK
V
V
Cross Points
PP
CMR
CLK
LVPECL
nQx
VEE
GND
-1.3V±0.165V
3.3V LVPECL Output Load AC Test Circuit
Differential Input Level
nQ0:Q3,
nFBOUT
nQx
Qx
Q0:Q3,
FBOUT
tcycle n
➤
➤
nQy
➤
tcycle n+1
➤
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Qy
tsk(o)
Output Skew
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 12
Cycle-to-Cycle Jitter
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Parameter Measurement Information, continued
nQ0:Q3,
nFBOUT
80%
80%
nQ0:Q3,
nFBOUT
VOD
80%
80%
VSW I N G
20%
20%
Q0:Q3,
FBOUT
tF
tR
VOS
tF
tR
GND
LVPECL Output Rise/Fall Time
LVDS Output Rise/Fall Time
Phase Noise Plot
Noise Power
nQ0:Q3,
nFBOUT
Q0:Q3,
FBOUT
20%
20%
Q0:Q3,
FBOUT
t PW
t
odc =
PERIOD
t PW
Phase Noise Mask
x 100%
t PERIOD
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
LVPECL/LVDS Output Duty Cycle/Pulse Width/Period
RMS Phase Jitter
VDD
VDD
out
LVDS
➤
out
➤
out
➤
DC Input
LVDS
100
VOS/∆ VOS
➤
VOD/∆ VOD
out
➤
DC Input
➤
Offset Voltage Setup
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 13
Differential Output Voltage Setup
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Parameter Measurement Information, continued
VDD
VDD
out
M-LVDS
➤
out
➤
DC Input
➤
out
M-LVDS
100
100
➤
VOD/∆ VOD
VOS/∆ VOS
out
➤
DC Input
➤
M-LVDS Offset Voltage Setup
M-LVDS Differential Output Voltage Setup
20
0
-3dB
1.2MHz
Mag (dB)
-20
-3dB
21.9MHz
-40
-60
-80
-100
104
105
106
107
108
Frequency (Hz)
H3(s) * (H1(s) – H2(s))
Composite PCIe Transfer Function
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 14
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Application Information
Overview
The is a high performance FemtoClock Zero Delay Buffer/
Multiplier/Divider which uses external feedback for accurate clock
regeneration and low static and dynamic phase offset. It can be
used in a number different ways:
• Backplane clock multiplier. Many backplane clocks are
relatively low frequency because of heavy electrical loading.
The ICS8743004I can multiply a low frequency backplane
clock (e.g. 25MHz) to an appropriate reference clock
frequency for PCIe, Ethernet, 10G Ethernet: 100MHz,
125MHz, 156.25MHz. The device can also accept a high
frequency local reference (100MHz or 125 MHz, for example)
and divide the frequency down to 25MHz M-LVDS to drive a
backplane.
• PCIe frequency translator for PCIe add-in cards. In personal
computers, the PCIe reference clock is 100MHz, but some
2.5G serdes used in PCI Express require a 125MHz
reference. The ICS8743004I can perform the 100MHz →
125MHz and 125MHz → 100MHz frequency translation for a
PCI Express add-in card while delivering low dynamic and
static phase offset.
• General purpose, low phase noise Zero Delay Buffer
Configuration Notes and Examples
When configuring the output frequency, the main consideration is
keeping the VCO within its range of 490MHz - 660MHz. The
designer must ensure that the VCO will always be within its allowed
range for the expected input frequency range by using the
appropriate choice of feedback output and input dividers. There
are two input modes for the device. In the first mode, a reference
clock is provided to the CLK/nCLK input and this reference clock is
divided by the value of the PDIV divider (selectable ÷1, ÷4, ÷5, ÷8).
In the second mode, a reference clock is provided to the MLVDS/
nMLVDS input pair. OE_MLVDS determines the input mode. When
OE_MLVDS = HIGH (default), the M-LVDS driver is active and
provides an M-LVDS output to the MLVDS/nMLVDS pins and also
the reference to the phase detector via the PDIV divider. When
OE_MLVDS is LOW, the internal M-LVDS driver is in Hi-Z state and
the MLVDS/nMLVDS pin pair becomes an input and the reference
clock applied to this input is applied to the phase detector.
MLVDS/nMLVDS Output Mode
OE_MLVDS = HIGH (default)
VCO frequency = CLK/nCLK frequency * FBI_DIV * FBO_DIV/
(PDIV value)
Allowed VCO frequency = 490MHz – 660MHz
Output frequency = VCO frequency/QDIVx value =
CLK/nCLK freq. * FBI_DIV * FBO_DIV/(PDIV*QDIVx)
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 15
Example: a frequency synthesizer provides a 125MHz reference
clock to CLK/nCLK input. The ICS8743004I must provide a 25MHz
M-LVDS clock to the backplane and also provide two local clocks:
one 100MHz LVDS output to an ASIC and one 125MHz output to
the PCI Express serdes.
Solution. Since only two outputs are needed, the two unused
outputs can be disabled. Set OE[1:0] = 01b so that only Q0/nQ0
and Q1/nQ1 are switching. Since a 25MHz backplane clock is
needed from a 125MHz reference clock, set PDIV = ÷5 and
OE_MLVDS = HIGH to enable the M-LVDS driver. 25MHz is
applied to the MLVDS/nMLVDS pins and to the phase detector
input. Set FBO_DIV = 4 and FBI_DIV = 5 which makes the VCO
run at 500MHz (25MHz * 4 * 5 = 500MHz). Set QDIV0 = 0 (÷4) for
125MHz output and QDIV1 = 1 (÷5) for 100MHz output. To figure
out what pins must pulled up or down externally with resistors,
check the internal pullup or pulldown resistors on each pin in the
pin description table or on the block diagram. PDIV[1:0] defaults to
00/÷4 and we need 01/÷5. So PDIV1 can be left floating (it has an
internal pulldown resistor) and PDIV0 must be driven or pulled up
via external pullup resistor to HIGH state. OE_MLVDS defaults to
Logic 1 (active) and this is what we need, so that pin can be left
floating. The FBO_DIV and FBIN dividers default to the desired
values, so their respective control pins can be left floating
(FBO_DIV and FBI_DIV[1:0]). QDIV0 needs to be ÷4, which is a
default value so this pin can be left floating. QDIV1 must be HIGH
for ÷5, so this pin must be pulled high or driven high externally.
OE[1:0] = 01, so OE0 can Float and OE1must be pulled Low.
MLVDS/nMLVDS Input Mode
OE_MLVDS = LOW
VCO frequency = MLVDS/nMLVDS freq. * FBI_DIV * FBO_DIV
Output frequency = VCO frequency/QDIVx value =
MLVDS/nMLVDS freq. * FBI_DIV * FBO_DIV/(QDIVx)
Example - backplane: The 8743004I sits on a backplane card and
must multiply a 25MHz reference that comes from the backplane
into one 125MHz reference clock for a gigabit Ethernet serdes and
one 100MHz reference clock for a PCI Express serdes.
Solution. Since only two outputs are needed, the two unused
outputs can be disabled. Set OE1:0 = 01b so that only Q0/nQ0 and
Q1/nQ1 are switching. Set OE_MLVDS = 0 so the internal M-LVDS
driver is in a Hi-Z state, allowing the MLVDS/nMLVDS pins to
function as an input for the 25MHz clock reference. Set FBO_DIV
= 4 and FBI_DIV = 5 which makes the VCO run at 500MHz (25MHz
* 4 * 5 = 500MHz). Set QDIV0 = 0 (÷4) for 125MHz output and
QDIV1 = 1 (÷5) for 100MHz output. To figure out what pins must
pulled up or down externally with resistors, check the internal
pullup or pulldown resistors on each pin in the pin description table
or on the block diagram. PDIV[1:0] defaults to 00/÷4 and we need
01/÷5. So PDIV1 can be left floating (it has an internal pulldown
resistor) and PDIV0 must be driven or pulled up via external pullup
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
resistor to HIGH state. OE_MLVDS defaults to Logic 1 (active) and
this is what we need, so that pin can be left floating. The FBO_DIV
and FBIN dividers default to the desired values, so their respective
control pins can be left floating (FBO_DIV and FBI_DIV1:0).
PRELIMINARY
QDIV0 needs to be ÷4, which is a default value so this pin can be
left floating. QDIV1 must be HIGH for ÷5, so this pin must be pulled
high or driven high externally. OE[1:0] = 01, so OE0 can Float and
OE1must be pulled Low.
Master
Master Clock
Clock Card
Card
25
25 MHz
MHz
ICS8743004I
ICS8743004I
CLK
CLK
MLVDS
MLVDS
100
100 MHz
MHz LVDS
LVDS
÷4
÷4
CLK
nCLK
nMLVDS
nMLVDS
SSC
SSC Synthesizer
Synthesizer
ICS841402I
ICS841S32I
100
100 MHz
MHz LVDS
LVDS
FPGA
FPGA
FemtoClock
FemtoClock
VCO
VCO
125
125 MHz
MHz LVDS
LVDS
PCIe
PCIe Serdes
Serdes
Slave
Slave synthesizer
synthesizer
Off
Off or
or output
output disabled
disabled
Backplane
Backplane
Slave
Slave Clock
Clock Card
Card
25
25 MHz
MHz
MLVDS
MLVDS
ICS8743004I
ICS8743004I
CLK
CLK
SSC
SSC Synthesizer
Synthesizer
ICS8411402I
ICS841S32I
÷4
÷4
nCLK
CLK
100
100 MHz
MHz LVDS
LVDS
FPGA
FPGA
FemtoClock
FemtoClock
VCO
VCO
125
125 MHz
MHz LVDS
LVDS
PCIe
PCIe Serdes
Serdes
Figure 1, Example Backplane Application
Bold lines
indicate active clock path
This example shows a case where each card may be dynamically
configured as a master or slave card, hence the need for an
ICS8743004I and ICS841402I on each card. On the master timing
card, the ICS841402I provides a 100MHz reference to the
ICS8743004I CLK/nCLK input. The M-LVDS pair on the
ICS8743004I is configured as an output (OE_MLVDS = Logic 1)
and the internal divider is set to ÷4 to generate 25MHz M-LVDS to
the backplane. The 25MHz clock is also used as a reference to the
FemtoClock PLL which multiplies to a VCO frequency of 500MHz.
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 16
Each of the four output pairs may be individually set for ÷4 or ÷5 for
125MHz or 100MHz operation respectively and in this example,
one output pair is set to 100MHz for the FPGA and another output
pair is set to 125MHz for the PCI Express serdes. For the slave
card, the M-LVDS pair is configured as an input (OE_MLVDS =
LOW) and the FemtoClock PLL multiplies this reference frequency
to 500MHz VCO frequency and the output dividers are set to
provide 100MHz to the FPGA and 125MHz to the PCI Express
Serdes as shown.
ICS8743004DKI REV. A AUGUST 25, 2008
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8743004I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA and VDDO
should be individually connected to the power supply plane
through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 2 illustrates how a 10Ω resistor along with a 10µF
and a 0.01µF bypass capacitor should be connected to each VDDA
pin.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 2. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 3. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 17
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4E show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 4A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
nCLK
HiPerClockS
Input
LVHSTL
R1
50
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
LVPECL
R2
50
R1
50
R2
50
R2
50
Figure 4B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 4A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
Zo = 50Ω
nCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
nCLK
Receiver
Figure 4D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 4C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
Zo = 50Ω
LVDS
3.3V
*R3
33
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
HCSL
*R4
33
R1
50
R2
50
HiPerClockS
Input
*Optional – R3 and R4 can be 0Ω
Figure 4E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 18
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 5. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
PIN
PIN PAD
SOLDER
application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as many
vias connected to ground as possible. It is also recommended that
the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz
copper via barrel plating. This is desirable to avoid any solder
wicking inside the via during the soldering process which may
result in voids in solder between the exposed pad/slug and the
thermal land. Precautions should be taken to eliminate any solder
voids between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For
further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadfame Base Package, Amkor Technology.
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 19
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 6. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
R1
100Ω
–
50Ω
100Ω Differential Transmission Line
Figure 6. Typical LVDS Driver Termination
3.3V M-LVDS Driver Termination
A general M-LVDS interface is shown in Figure 7 In a 100Ω
differential transmission line environment, M-LVDS drivers require
a matched load termination of 100Ω across near the receiver input.
For a multiple M-LVDS outputs buffer, if only partial outputs are
used, it is recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
R2
100Ω
R1
100Ω
–
50Ω
100Ω Differential Transmission Line
Figure 7. Typical M-LVDS Driver Termination
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 20
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 8A and 8B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
125Ω
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
Figure 8A. 3.3V LVPECL Output Termination
84Ω
84Ω
Figure 8B. 3.3V LVPECL Output Termination
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK/nCLK Inputs
LVDS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
M-LVDS Outputs
MLVDS/nMLVDS Inputs
For applications not requiring the use of the differential input, both
MLVDS and nMLVDS can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from MLVDS to
ground.
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 21
All unused M-LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
ICS8743004DKI REV. A AUGUST 25, 2008
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FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Power Considerations – LVPECL Outputs
This section provides information on power dissipation and junction temperature for the ICS8743004I, for all outputs that are configured
to LVPECL. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8743004I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * IEE_MAX = 3.465V * 240mA = 831.6mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 831.6mW + 120mW = 951.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 32.4°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.952W * 32.4°C/W = 115.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board.
Table 6. Thermal Resistance θJA for 40 Lead VFQFN, Forced Convection
θJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
32.4°C/W
28.3°C/W
25.4°C/W
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 9.
VDDO
Q1
VOUT
RL
50Ω
VDDO - 2V
Figure 9. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VDDO – 2V.
•
For logic high, VOUT = VOH_MAX = VDDO_MAX – 0.9V
(VDDO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VDDO_MAX – 1.7V
(VDDO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – (VDDO_MAX – VOH_MAX))/RL] * (VDDO_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – (VDDO_MAX – VOL_MAX))/RL] * (VDDO_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Power Considerations – LVDS Outputs
This section provides information on power dissipation and junction temperature for the ICS8743004I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8743004I is the sum of the core power plus the analog power plus the power dissipated in the
load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (140mA + 18mA) = 547.47mW
•
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 140mA = 485.1mW
Total Power_MAX = 547.47mW + 485.1mW = 1032.57mW
•
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 32.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.033W * 32.4°C/W = 118.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board.
Table 7. Thermal Resistance θJA for 40 Lead VFQFN, Forced Convection
θJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
32.4°C/W
28.3°C/W
25.4°C/W
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Reliability Information
Table 8. θJA vs. Air Flow Table for a 40 Lead VFQFN
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
32.4°C/W
28.3°C/W
25.4°C/W
Transistor Count
The transistor count for ICS8743004I is: 4893
Package Outline and Package Dimensions
Package Outline - K Suffix for 40 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
L
N
e (Ty p.)
2 If N & N
1
Anvil
Singula tion
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
N &N
Odd
0. 08
C
D2
2
Th er mal
Ba se
D2
C
Table 9. Package Dimensions
JEDEC Variation: VJJD-2/-5
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
40
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.30
10
ND & NE
D&E
6.00 Basic
D2 & E2
1.75
4.80
e
0.50 Basic
L
0.30
0.50
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This
drawing is not intended to convey the actual pin count or pin layout
of this device. The pin count and pinout are shown on the front
page. The package dimensions are in Table 8 below
Reference Document: JEDEC Publication 95, MO-220
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Ordering Information
Table 10. Ordering Information
Part/Order Number
8743004DKILF
8743004DKILFT
Marking
ICS743004DIL
ICS743004DIL
Package
“Lead-Free” 40 Lead VFQFN
“Lead-Free” 40 Lead VFQFN
Shipping Packaging
Tray
1000 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
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Contact Information:
www.IDT.com
www.IDT.com
Sales
Technical Support
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
netcom@idt.com
+480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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