894D115BGI-01LFT

OC-12/STM-4 and OC-3/STM-1 Clock/Data Recovery Device 894D115I-01 DATA SHEET General Description Features The 894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock signal from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The output signals of the device are the recovered clock and retimed data signals. Input and output are differential signals for best signal integrity and to support high clock and data rates. All control inputs and outputs are single-ended signals. An internal PLL is used for clock generation and recovery. An external clock input is provided to establish an initial operating frequency of the clock recovery PLL and to provide a clock reference in the absence of serial input data. The device supports a signal detect input and a lock detect output. A bypass circuit is provided to facilitate factory tests. • Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3) • • Input: NRZ data (622.08 or 155.52 Mbit/s) • • • • • • • • • Internal PLL for clock generation and clock recovery • See ICS894D115I-04 for a clock/data recovery circuit with LVDS outputs Output: clock signal (622.08MHz or 155.52MHz) and retimed data signal at 622.08 or 155.52 Mbit/s Differential inputs can accept LVPECL levels Differential LVPECL data and clock outputs Lock reference input and PLL lock output 19.44MHz reference clock input Full 3.3V supply mode -40°C to 85°C operating temperature Available in lead-free (RoHS 6) package See ICS894D115I for a clock/data recovery circuit with a TSSOP EPAD package Pin Assignment Block Diagram CAP VCCA DATA_IN nDATA_IN VEE_PLL LOCK_DET STS12 REF_CLK nCAP DATA_IN Pulldown nDATA_IN Pullup/Pulldown PLL LOCK_REFN VEE VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCCA VEE_PLL CAP nCAP BYPASS SD DATA_OUT nDATA_OUT CLK_OUT nCLK_OUT 894D115I-01 DATA_OUT 0 nDATA_OUT REF_CLK Pulldown 1 CLK_OUT STS12 Pulldown SD Pulldown nCLK_OUT LOCK_REFN Pullup LOCK_DET BYPASS Pulldown 894D115I-01 Rev C 2/19/15 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View 1 ©2015 Integrated Device Technology, Inc. 894D115I-01 DATA SHEET Functional Description The 894D115I-01 is designed to extract the clock from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The output signals are the recovered clock and retimed data signal. The device contains an integrated PLL for clock generation and to lock the output clock to the input data stream. The PLL attempts to lock to the reference clock input (REF_CLK) in absence of the serial data stream or if it is forced to by the control inputs LOCK_REFN or SD. The output clock frequency is controlled by the STS12 input. The output frequency is 622.08MHz in STM-4/OC-12/STS-12 mode and 155.52MHz in STM-1/OC-3/STS-3 mode. LOCK_REFN (lock-to-reference) inputs to accept loss of signal status information from electro-optical receivers. Please refer to Figure 1, “Signal Detect/PLL Bypass Operation Control Diagram”, for details. The lock detect output (LOCK_DET) can be used to monitor the operating state of the clock/data recovery circuit. LOCK_DET is set to logic LOW level when the internal oscillator of the PLL and the reference clock (REF_CLK) deviate from each other by more than 500ppm, or when the CDR is forced to lock the REF_CLK input by the LOCK_REFN or SD control input. LOCK_DET is set to HIGH when the PLL is locked to the input data stream and indicates valid clock and data output signals. The 894D115I-01 will maintain an output (CLK_OUT/ nCLK_OUT) frequency deviation of less than ±500ppm with respect to the REF_CLK reference frequency in a loss of signal state (LOS). During the LOS state, DATA_OUT is held at logic LOW state and nDATA_OUT is held at logic HIGH state. An LOS state of the 894D115I-01 is given when BYPASS is set to the logic LOW state and either one of the SD or LOCK_REFN inputs are at a logic LOW state. This will enable the use of the SD (signal detect) and the The BYPASS pin should be set to logic LOW state in all applications. BYPASS set to logic HIGH state is used during factory test. In BYPASS mode (BYPASS and STS12 are at logic HIGH state), the internal PLL is bypassed and the inverted REF_CLK input signal is output at CLK_OUT/nCLK_OUT. DATA_OUT DATA_IN Pulldown nDATA_IN Pullup/Pulldown PLL Clock (on-chip) REF_CLK Pulldown nDATA_OUT 0 CLK_OUT 1 nCLK_OUT STS12 Pulldown BYPASS Pulldown LOCK_REFN Pullup LOS (on-chip) SD Pulldown Figure 1. Signal Detect/PLL BYPASS Operation Control Diagram OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 2 Rev C 2/19/15 894D115I-01 DATA SHEET Table 1. Signal Detect/PLL BYPASS Operation Control Table Inputs Outputs STS12 BYPASS LOCK_REFN SD DATA_OUT CLK_OUT 1 0 1 1 DATA_IN PLL Clock 1 0 1 0 LOW PLL Clock 1 0 0 1 LOW PLL Clock 1 0 0 0 LOW PLL Clock 1 1 X X DATA_IN REF_CLK 0 0 1 1 DATA_IN PLL Clock 0 0 1 0 LOW PLL Clock 0 0 0 1 LOW PLL Clock 0 0 0 0 LOW PLL Clock 0 1 X X Not Allowed Not Allowed Table 2. Pin Descriptions Number Name Type Description 1, 20 VCCA Power 2 DATA_IN Input Pulldown Analog supply pins. Non-inverting differential signal input. 3 nDATA_IN Input Pullup/ Pulldown Inverting differential signal input. VCC/2 default when left floating. 4, 19 VEE_PLL Power Negative supply pins. 5 LOCK_DT Output Lock detect output. See Table 4A. Single-ended LVPECL interface levels. 6 STS12 Input Pulldown STM-4 (OC-12, STS-12) or STM-1 (OC-3, STS-3) selection mode. See Table 4B. LVCMOS/LVTTL interface levels. 7 REF_CLK Input Pulldown Reference clock input of 19.44MHz. LVCMOS/LVTTL interface levels. 8 LOCK_REFN Input Pullup 9 VEE Power Negative supply pin. 10 VCC Power Core supply pin. 11, 12 nCLK_OUT, CLK_OUT Output Differential clock output pair. LVPECL interface levels. 13, 14 nDATA_OUT, DATA_OUT Output Differential clock output pair. LVPECL interface levels. 15 SD Input Pulldown Signal detect input. Typically, SD is driven by the signal detect output of the electro-optical module. See Table 4D. Single-ended LVPECL interface levels. 16 BYPASS Input Pulldown PLL bypass mode. See Table 4E. LVCMOS/LVTTL interface levels. 17, 18 nCAP, CAP Input Lock to REF_CLK input. See Table 4C. LVCMOS/LVTTL interface levels. External loop filter (1.0µF ±10%). NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values. OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 3 Rev C 2/19/15 894D115I-01 DATA SHEET Table 3. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k Function Tables Table 4A. LOCK_DET Operation Table Output Operation LOCK_DET The PLL is not locked to the serial input data stream if any of these three conditions occur: A. Internal oscillator and REF_CLK input frequency are not within 500ppm of each other. B. SD input is at logic LOW state. C. LOCK_REFN is at logic LOW state. LOW When the PLL is locked to the serial input data stream, the CLK_OUT and DATA_OUT signals are valid. HIGH Table 4B. STS12 Mode Configuration Table Input STS12 Operation 0 STM-1 (OC-3, STS-3) operation. The clock/data recovery circuit attempts to recover the clock from a 155.52 Mbit/s input data stream. The output clock frequency is 155.52MHz. 1 STM-4 (OC-12, STS-12) operation. The clock/data recovery circuit attempts to recover the clock from a 622.08 Mbit/s input data stream. The output clock frequency is 622.08MHz. Table 4C. LOCK_REFN Mode Configuration Table Input LOCK_REFN Operation 0 Lock to reference clock. CLK_OUT/nCLK_OUT output frequency is within ±500ppm of the reference clock (REF_CLK). DATA_OUT is set to logic LOW state and nDATA_OUT is set to logic HIGH state. (DATA_OUT = L, nDATA_OUT = H). 1 Normal operation. Table 4D. SD Mode Configuration Table Input SD Operation 0 Indicates a loss-of-signal (LOS) condition to the device. CLK_OUT/nCLK_OUT output frequency is within ±500ppm of the reference clock (REF_CLK). DATA_OUT is set to logic LOW state and nDATA_OUT is set to logic HIGH state. (DATA_OUT = L, nDATA_OUT = H). 1 Normal operation. Rev C 2/19/15 4 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 894D115I-01 DATA SHEET Table 4E. BYPASS Mode Configuration Table Input BYPASS Operation 0 Normal operation. 1 PLL bypassed (for factory test). The inverted REF_CLK input signal is output at CLK_OUT/nCLK_OUT. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 81.3C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 5A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.10 3.3 VCC V IEE Power Supply Current 80 mA ICCA Analog Supply Current 10 mA Table 5B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V REF_CLK, STS12, BYPASS VCC = VIN = 3.465V 150 µA LOCK_REFN VCC = VIN = 3.465V 10 µA REF_CLK, STS12, BYPASS VCC = 3.465V, VIN = 0V -10 µA LOCK_REFN VCC = 3.465V, VIN = 0V -150 µA OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 5 Rev C 2/19/15 894D115I-01 DATA SHEET Table 5C. Differential DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical IIH Input High Current DATA_IN/nDATA_IN IIL Input Low Current VIH Input High Voltage VDD – 1.75 VDD – 0.4 V VIL Input Low Voltage VDD – 2.0 VDD – 0.7 V VIN Differential Input Voltage VCC = VIN = 3.465V Maximum Units 150 µA DATA_IN VCC = 3.465V, VIN = 0V -10 µA nDATA_IN VCC = 3.465V, VIN = 0V -150 µA 250 mV Table 5D. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum VIH Input High Voltage SD VIL Input Low Voltage SD IIH Input High Current SD VCC = VIN = 3.465V IIL Input Low Current SD VCC = 3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.9 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V VCC – 1.125 Units V VCC – 1.5 V 150 µA -10 µA NOTE 1: Outputs terminated with 50 to VCC – 2V. Rev C 2/19/15 6 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 894D115I-01 DATA SHEET AC Electrical Characteristics Table 6. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C Parameter Symbol Test Conditions fVCO VCO Center Frequency fTOL CRU’s Reference Clock Frequency Tolerance fTREF_CLK OC-12/STS-12 Capture Range tLOCK Acquisition Lock Time OC-12/STS-12 JGEN_CLK Jitter Generation CLK_OUT/ nCLK_OUT JTOL Jitter Tolerance OC-12/STS-12; NOTE 1 tR / tF Output Rise/Fall Time; NOTE 1 odc Output Duty Cycle; NOTE 1 tS Setup Time; NOTE 1 tH Minimum Typical Maximum 622.08 -250 With respect to the fixed reference frequency ±500 14ps rms (max.) jitter on DATA_IN/nDATA_IN Sinusoidal input jitter of DATA_IN/ nDATA_IN from 250kHz to 5MHz 0.005 20% minimum transition density 45 STS-3 2000 ppm ppm 16 µs 0.01 UI 0.45 UI 20% to 80% Hold Time; NOTE 1 MHz 250 Valid REF_CLK and device already powered-up Units 500 ps 55 % 3220 ps STS-12 450 800 ps STS-3 3000 3220 ps STS-12 650 800 ps NOTE 1: See diagram in Parameter Measurement Information section. OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 7 Rev C 2/19/15 894D115I-01 DATA SHEET Parameter Measurement Information Requirement Mask 2V Input Jitter Amplitude (UIpp) .2V VCC VCCA slope = -20dB/decade 15 1.5 0.15 10 30 -1.3V±0.165V 3.3V Output Load AC Test Circuit 300 25k Jitter Frequency (Hz) 250k 5M Jitter Tolerance Specification nDATA_OUT DATA_OUT nCLK_OUT, nDATA_OUT t SU CLK_OUT, DATA_OUT tH CLK_OUT nCLK_OUT The re-timed data output (DATA_OUT) can be captured with the rising edge of the clock output signal (CLOCK_OUT). DATA_OUT is valid the specified setup time before the rising CLK_OUT signal and remains valid the specified hold time after the rising edge of the CLK_OUT signal. Output Duty Cycle/Pulse Width/Period Setup/Hold Time VCC ΔVIN = DATA_IN - nDATA_IN nDATA_IN VPP Cross Points VIH DATA_IN VEE Differential Input Level Rev C 2/19/15 8 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 894D115I-01 DATA SHEET Parameter Measurement Information, continued nCLK_OUT, nDATA_OUT CLK_OUT, DATA_OUT Output Rise/Fall Time Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 894D115I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VCCA pin. 3.3V VCC 0.01µF VCCA 0.01µF 10µF Figure 2. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 9 Rev C 2/19/15 894D115I-01 DATA SHEET Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 3A. 3.3V LVPECL Output Termination Rev C 2/19/15 R2 84 Figure 3B. 3.3V LVPECL Output Termination 10 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 894D115I-01 DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the 894D115I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 894D115I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.20mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.3V, with all outputs switching) = 277mW + 60mW = 337mW 2. Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. Lower temperature refers to ambient temperature, maximum temperature refers to case temperature. Table 7. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 81.3°C/W 76.9°C/W 74.8°C/W 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 11 Rev C 2/19/15 894D115I-01 DATA SHEET LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 4. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW Rev C 2/19/15 12 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 894D115I-01 DATA SHEET Reliability Information Table 8. JA vs. Air Flow Table for a 20 Lead TSSOP JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 81.3°C/W 76.9°C/W 74.8°C/W Transistor Count The transistor count for 894D115I-01 is: 10,406 Compatible with VSC8115 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 13 Rev C 2/19/15 894D115I-01 DATA SHEET Ordering Information Table 10. Ordering Information Part/Order Number 894D115BGI-01LF 894D115BGI-01LFT Marking ICSD115BI01L ICSD115BI01L Package “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 14 Rev C 2/19/15 894D115I-01 DATA SHEET Revision History Sheet Rev B Table Page T6 7 AC Characteristics Table - corrected typo for Hold Time, STS-3 spec. from 300ps to 3000ps max. 6/24/08 T5C 6 Differential DC Characteristics Table - deleted VPP and VCMR specs and added VIH, VIL, VIN specs. Parameter Measurement Information Section - updated Differential Input Level diagram. 10/15/08 Ordering Information - removed leaded devices, PDN CQ-13-02 Updated data sheet format 2/19/15 C C 8 T10 14 Description of Change OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE Date 15 Rev C 2/19/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. 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