FemtoClock® NG Clock Generator
with 4 Dividers
8V49NS0312
Datasheet
Description
Features
The 8V49NS0312 is a Clock Generator with four output dividers:
three integer and one that is either integer or fractional. When used
with an external crystal, the 8V49NS0312 generates
high-performance timing geared towards the communications and
datacom markets, especially for applications that demand extremely
low phase noise, such as 10, 40, and 100GE.
▪ Eleven differential LVPECL, LVDS outputs with programmable
voltage swings
▪ One LVCMOS output
— Input reference maybe bypassed to this output
▪ The clock input operates in full differential mode (LVDS, LVPECL)
or single-ended LVCMOS mode
▪ Driven from a crystal or differential clock input
▪ 2.4-2.5GHz PLL frequency range supports Ethernet, SONET and
CPRI frequency plans
▪ Four Integer output dividers with a range of output divide ratios
(see Table 7)
▪ One Fractional Output divider can generate any desired output
frequency
▪ Support of output power-down
▪ Excellent clock output phase noise
Offset
Output Frequency
Single-side Band Phase Noise
The 8V49NS0312 provides versatile frequency configurations and
output formats and is optimized to deliver excellent phase noise
performance. The device delivers an optimum combination of high
clock frequency and low phase noise performance, combined with
high power supply noise rejection.
The 8V49NS0312 supports two types of output levels: LVPECL or
LVDS on eleven of its outputs. In addition, there is a single LVCMOS
output that has the option of providing a generated clock or acting as
a reference bypass output.
The device can be configured to deliver specific output
configurations under pin control only or additional configurations
through an I2C serial interface.
▪
It is offered in a lead-free (RoHS6) 64-VFQFPN package.
▪
▪
▪
▪
▪
©2019 Integrated Device Technology, Inc.
1
100kHz
156.25MHz
-143dBc/Hz
Phase Noise RMS, 156.25MHz, 12kHz to 20MHz integration
range: 110fs (maximum)
Select configurations may be controlled via the use of control
input pins without need for serial port access
LVCMOS compatible I2C serial interface gives access to
additional configurations either alone or in combination with the
control input pins
Single 3.3V supply voltage
Lead-free (RoHS 6) 64-VFQFPN packaging
-40°C to 85°C ambient operating temperature
April 24, 2019
8V49NS0312 Datasheet
Block Diagram
Figure 1: 8V49NS0312 Block Diagram
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8V49NS0312 Datasheet
REF_SEL
VCC_CK
nCLK
CLK
FIN[1]
FIN[0]
CAPXTAL
OSCO
OSCI
VCCA_XT
NA[0]
RES
SDATA
SCLK
VCC_SP
LOCK
Pin Assignment
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VCCOB
1
48
VCCOA
QB0
2
47
QA0
nQB0
3
46
nQA0
QB1
4
45
QA1
nQB1
5
44
nQA1
QB2
6
43
QA2
nQB2
7
42
nQA2
QB3
8
41
QA3
nQB3
9
40
nQA3
VCCOB
10
39
VCCOA
ND[0]
11
38
VCCOC
ND[1]
12
37
QC0
VCCOD
13
36
nQC0
QD1
14
35
QC1
QD0
15
34
nQC1
16
33
VCCOC
nQD0
8V49NS0312
VCC_CP
ICP
nc
VCCA
LFF
LFFR
CAPREG
CR
VCCA_IN2
NA[1]
CAPBIAS
NC[1]
VCCA_IN1
NB[1]
NC[0]
NB[0]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-pin, 9mm x 9mm VFQFN Package
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8V49NS0312 Datasheet
Pin Description and Pin Characteristic Tables
Table 1: Pin Descriptionsa
Number
Name
Type
1
VCCOB
Power
2
QB0
Output
3
nQB0
Output
4
QB1
Output
5
nQB1
Output
6
QB2
Output
7
nQB2
Output
8
QB3
Output
9
nQB3
Output
10
VCCOB
Power
11
ND[0]
Input
Pullup /
Pulldown
Control Inputs for Output Bank D. 3-level signals. Refer to Table 12.
12
ND[1]
Input
Pullup /
Pulldown
Control Inputs for Output Bank D. 3-level signals. Refer to Table 12.
13
VCCOD
Power
Power Supply Voltage for Output Bank D (3.3V).
14
QD1
Output
Single-ended output clock. LVCMOS output levels.
15
QD0
Output
16
nQD0
Output
17
NB[0]
Input
Pullup /
Pulldown
Control Inputs for Output Bank B. 3-level signals. Refer to Table 10.
18
NB[1]
Input
Pullup /
Pulldown
Control Inputs for Output Bank B. 3-level signals. Refer to Table 10.
19
NC[0]
Input
Pullup /
Pulldown
Control Inputs for Output Bank C. 3-level signals. Refer to Table 11.
20
NC[1]
Input
Pullup /
Pulldown
Control Inputs for Output Bank C. 3-level signals. Refer to Table 11.
21
VCCA_IN1
Power
22
NA[1]
Input
23
CAPBIAS
Analog
Internal VCO bias decoupling capacitor. Use a 4.7µF capacitor between the
CAPBIAS terminal and VEE.
24
VCCA_IN2
Power
Analog Power Supply Voltage for VCO (3.3V).
25
CR
Analog
Internal VCO regulator decoupling capacitor. Use a 1µF capacitor between the CR
and the VCCA terminals.
26
CAPREG
Analog
Internal VCO regulator decoupling capacitor. Use a 4.7µF capacitor between the
CAPREG terminal and VEE.
©2019 Integrated Device Technology, Inc.
Description
Power Supply Voltage for Output Bank B (3.3V).
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Power Supply Voltage for Output Bank B (3.3V).
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Analog Power Supply Voltage for PLL (3.3V).
Pullup /
Pulldown
Control Inputs for Output Bank A. 3-level signals. Refer to Table 9.
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8V49NS0312 Datasheet
Table 1: Pin DescriptionsaCont.
Number
Name
Type
27
LFFR
Analog
Ground return path pin for the PLL loop filter.
28
LFF
Output
Loop filter/charge pump output for the FemtoClock NG PLL. Connect to the external
loop filter.
29
VCCA
Power
Analog Power Supply Voltage for VCO (3.3V).
30
nc
-
31
VCC_CP
Power
Analog Power Supply Voltage for PLL charge pump (3.3V).
32
ICP
Analog
Charge pump current input for PLL. Connect to LFF pin (28).
33
VCCOC
Power
Power Supply Voltage for Output Bank C (3.3V).
34
nQC1
Output
35
QC1
Output
36
nQC0
Output
37
QC0
Output
38
VCCOC
Power
Power Supply Voltage for Output Bank C (3.3V).
39
VCCOA
Power
Power Supply Voltage for Output Bank A (3.3V).
40
nQA3
Output
41
QA3
Output
42
nQA2
Output
43
QA2
Output
44
nQA1
Output
45
QA1
Output
46
nQA0
Output
47
QA0
Output
48
VCCOA
Power
49
REF_SEL
Input
50
VCC_CK
Power
51
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VCC_CK.
52
CLK
Input
Pulldown
Non-inverting differential clock input.
53
FIN[1]
Input
Pullup /
Pulldown
Control Inputs for Input Reference Frequencies. 3-level signals. Refer to Table 5.
54
FIN[0]
Input
Pullup /
Pulldown
Control Inputs for Input Reference Frequencies. 3-level signals. Refer to Table 5.
55
CAPXTAL
Analog
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Description
-
No connect. Do not use.
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Differential device clock output pair. LVPECL or LVDS with configurable amplitude.
Power Supply Voltage for Output Bank A (3.3V).
Pulldown
Selects Input Reference source. LVCMOS interface levels.
0 = Crystal input on pins OSCI, OSCO (default)
1 = Reference clock input on pins CLK, nCLK
Power Supply Voltage for input CLK, nCLK (3.3V).
Crystal oscillator circuit decoupling capacitor. Use a 4.7µF capacitor between the
CAPXTAL and the VEE terminals.
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8V49NS0312 Datasheet
Table 1: Pin DescriptionsaCont.
Number
Name
Type
Description
56
OSCO
Output
Crystal oscillator interface.
57
OSCI
Input
Crystal oscillator interface.
58
VCCA_XT
Power
59
NA[0]
Input
60
RES
Analog
61
SDATA
I/O
Pullup
I2C data Input/Output: LVCMOS interface levels. Open Drain Pin.
62
SCLK
Input
Pullup
I2C clock input. LVCMOS interface levels.
63
VCC_SP
Power
Power Supply Voltage for the I2C port (3.3V).
64
LOCK
Output
Lock status output. LVCMOS interface levels.
Logic Low = PLL not locked
Logic High = PLL locked
ePad
VEE
Power
Negative supply. Exposed pad must be connected to ground
Analog Power Supply Voltage for the Crystal Oscillator (3.3V).
Pullup /
Pulldown
Control Inputs for Output Bank A. 3-level signals. Refer to Table 9.
Connect a 2.8 k (1%) resistor to VEE for output current calibration.
a. Pulldown and Pullup refer to internal input resistors. See Table 2, Input Characteristics, for typical values.
Table 2: Input Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input
Capacitancea
3.5
pF
RPULLDOWN
Input Pulldown Resistor
51
k
RPULLUP
Input Pullup Resistor
51
k
a. This specification does not apply to OSCI and OSCO pins.
Table 3: Output Characteristics
Symbol
Parameter
ROUT
Output
Impedance
Test Conditions
LOCK
QD1
VCCa = 3.3V ± 5%
Minimum
Typical
Maximum
Units
20
30
a. VCC denotes VCC_SP, VCCOD.
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8V49NS0312 Datasheet
Principles of Operation
The 8V49NS0312 can be locked to either an input reference clock or a 10MHz to 50MHz fundamental-mode crystal and generate a wide range
of synchronized output clocks. Lock status may be monitored via the LOCK pin.
It could be used for example in either the transmit or receive path of Synchronous Ethernet or SONET/SDH equipment.
The 8V49NS0312 accepts a differential or single-ended input clock ranging from 5MHz up to 1GHz. It generates up to twelve output clocks
with up to four different output frequencies, ranging from 10.91MHz up to 2.5GHz.
The device outputs are divided into 4 output banks. Each bank supports conversion of the input frequency to a different output frequency: one
independent or integer-related output frequency on Bank D (QD[0:1]) and three more integer-related frequencies on Bank A (QA[0:3]), Bank B
(QB[0:3]) and Bank C (QC[0:1]). All outputs within a bank will have the same frequency.
The device is programmable through an I2C serial interface or control input pins.
Pin versus Register Control
The 8V49NS0312 can be configured by the use of input control pins and/or over an I2C serial port. The pins / registers used to control each
function are shown in Table 4. At power-up, control of each function is via the control input pins. Access over the serial port can change each
function individually to be controlled by registers. This allows for any mixture of register or pin control. However any of the indicated functions
can only be controlled by register or by pin at any given time, not by both. Use of register control will allow access to a wider range of
configuration options, but values are lost on power-down.
Table 4: Control of Specific Functions
Function
Control Select Bit
Control Input Pins
Register Fields Affected
Prescaler & PLL
Feedback Divider
FIN_CTL
FIN[1:0]
PS[5:0], FDP M[8:0]
Bank A
Divider & Output Type
NA_CTL
NA[1:0]
NA_DIV, PD_A, EN_A,
PD_QAx, STY_QAx,
AMP_QAx[1:0]
Bank B
Divider & Output Type
NB_CTL
NB[1:0]
NB_DIV, PD_B, EN_B,
PD_QBx, STY_QBx,
AMP_QBx[1:0]
Bank C
Divider & Output Type
NC_CTL
NC[1:0]
NC_DIV, PD_C, EN_C,
PD_QCx, STY_QCx,
AMP_QCx[1:0]
ND[1:0]
ND[5:0], ND_FINT[3:0],
ND_FRAC[23:0],
ND_DIVF[1:0], ND_SRC[1:0],
PD_D, EN_D, PD_QDx,
STY_QD0, AMP_QD0[1:0]
Bank D
Divider & Output Type
ND_CTL
Changes to the control input pins while the part is active are allowed, but can not be guaranteed to be glitch-free. It is recommended that any
such changes be performed by disabling the outputs using the I2C-accessible registers, then re-enabling once changes are completed. Also,
the output dividers, which are synchronized on power-up will not be re-synchronized without an explicit access to the INIT_CLK register bit
over the I2C interface.
Any change to the output dividers performed over the I2C interface must be followed by an assertion of the INIT_CLK register bit to force the
loading of the new divider values, as well as to synchronize the output dividers.
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8V49NS0312 Datasheet
Input Clock Selection (REF_SEL)
The 8V49NS0312 needs to be provided with an input reference frequency either from its crystal input pins (OSCI, OSCO) or its reference clock
input pins (CLK, nCLK). The REF_SEL input pin controls which source is used.
The crystal input on the 8V49NS0312 is capable of being driven by a parallel-resonant, fundamental mode crystal with a frequency of 10MHz
to 50MHz.
The crystal input also supports being driven by a single-ended crystal oscillator or reference clock, but only a frequency from 10MHz to 50MHz
may be used on these pins.
The reference clock input accepts clocks with frequencies ranging from 5MHz up to 1GHz. Each input can accept LVPECL, LVDS, LVHSTL,
HCSL or LVCMOS inputs using 2.5V or 3.3V logic levels as shown in the Applications Information section of this datasheet.
Prescaler and PLL Configuration
When the input frequency (fIN), whether generated by a crystal or clock input is known, and the desired PLL operating frequency has been
determined, several constraints need to be met:
▪ The Phase / Frequency Detector operating frequency (fPFD) must be within the specified limits shown in Table 28. This is controlled by
selecting an appropriate doubler (FDP) and prescaler (PS) value. If multiple values are possible, a higher f PFD will provide better phase
noise performance.
▪ The VCO operating frequency (fVCO) must be within the specified limits shown in Table 28. This is controlled by selecting an appropriate
PLL feedback Divider (M) value. Note that it may be necessary to chose a different prescaler value if the limits can not be met by the
available values of M. It may also be necessary to select an appropriate input frequency value.
Several preset configurations may be selected directly from the FIN[1:0] control input pins. These configurations are based on a particular
input frequency fIN and a particular fVCO (see Table 5). These selections apply whether the input frequency is provided from the crystal or
reference clock inputs
Table 5: Input Selection Control
FIN[1]
FIN[0]
fIN (MHz)
fVCO (MHz)
High
High
38.88
2488.32
a
High
Middle
38.4
2457.6
High
Low
31.25
2500
Middle
High
312.5
2500
Middle
Middle
125
2500
Middle
Low
156.25
2500
Low
High
100
2500
Low
Middle
25
2500
Low
Low
50
2500
a. A ‘middle’ voltage level is defined in Table 22. Leaving the input pin open will also
generate this level via a weak internal resistor network.
Alternatively the user may directly access the registers for M, FDP & PS over the serial interface for a wider range of options. See Table 6 for
some examples.
Inputs do not support transmission of spread-spectrum clocking sources. Since this family is intended for high-performance applications, it will
assume input reference sources to have stabilities of +100ppm or better.
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8V49NS0312 Datasheet
Table 6: PLL Frequency Control Examples
fIN (MHz)
PS
FDP
fPFD (MHz)
M
PLL Operating Frequency
(MHz)
25
1
2
50
50
2500
39.0625
1
2
78.125
32
2500
50
1
2
100
25
2500
100
1
1
100
25
2500
125
1
1
125
20
2500
156.25
1
1
156.25
16
2500
200
2
1
100
25
2500
250
2
1
125
20
2500
312.5
2
1
156.25
16
2500
400
4
1
100
25
2500
500
4
1
125
20
2500
625
4
1
156.25
16
2500
19.44
1
2
38.88
64
2488.32
38.88
1
2
77.76
32
2488.32
38.4
1
2
76.8
32
2457.6
PLL Loop Bandwidth
The 8V49NS0312 uses one external capacitor of fixed value to support its loop bandwidth. A fixed loop bandwidth of approximately 200kHz is
provided.
Output Divider Frequency Sources
Output dividers associated with Banks A, B & C take their input frequency directly from the PLL.
Bank D also has the option to bypass the input frequency (after mux) directly to the output.
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8V49NS0312 Datasheet
Integer Output Dividers (Banks A, B, C, and D)
The 8V49NS0312 supports four integer output dividers: one per output bank. Each integer output divider block independently supports one of
several divide ratios as shown in their respective register descriptions (Table 15, Table 16, Table 17 or Table 18). Select divide ratios can be
chosen directly from the control input pins for that particular output bank. The remaining ratios can only be selected via the serial interface.
Bank D may choose whether to use the integer divider or a separate fractional divider to generate the output.
Some example output frequencies are shown in Table 7 for the minimum fVCO (2400MHz), the maximum fVCO (2500MHz) and two other
common VCO frequencies. With appropriate input frequencies and configuration selections, any fVCO and fOUT between the minimum and
maximum can be generated.
Table 7: Integer Output Divider Control Examples
fOUT (MHz)
Divide Ratio
fVCO = 2400MHz
fVCO = 2457.6MHz
fVCO = 2488.32MHz
fVCO = 2500MHz
1
2400
2457.6
2488.32
2500
2
1200
1228.8
1244.16
1250
4
600
614.4
622.08
625
5
480
491.52
497.664
500
6
400
409.6
414.72
416.667
8
300
307.2
311.04
318.75
9
266.667
273.07
276.48
277.78
10
240
245.76
248.832
250
12
200
204.8
207.36
208.333
16
150
153.6
155.52
156.25
18
133.333
136.533
138.24
138.889
20
120
122.88
124.416
125
25
96
98.3
99.53
100
32
75
76.8
77.76
78.125
36
66.667
68.267
69.12
69.444
40
60
61.44
62.208
62.5
50
48
49.152
49.766
50
64
37.5
38.4
38.88
39.063
72
33.333
34.133
34.56
34.722
80
30
30.72
31.104
31.25
100
24
24.576
24.883
25
128
18.75
19.2
19.44
19.531
160
15
15.36
15.552
15.625
200
12
12.29
12.44
11.36
220
10.91
11.17
11.31
11.36
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8V49NS0312 Datasheet
Fractional Output Divider (Bank D)
For the fractional output divider in Bank D, the output divide ratio is given by:
f VCO
f OUT = -----------------------------------------------------------------------------FRAC- FDIV
2 FINT + --------------
24
2
Where,
▪ FINT = Integer Part: 5, 6, ...(24-1) - given by ND_FINT[3:0]
▪ FRAC = Fractional Part: 0, 1, 2, ...(224-1)- given by ND_FRAC[23:0]
▪ FDIV = post-divider: 1, 2 or 4- given by ND_DIVF[1:0]
This provides a frequency range of 20MHz to 312.5MHz.
Output Drivers
Each of the four output banks are provided with pin or register-controlled output drivers. Differential outputs may be individually selected as
LVDS, LVPECL or POWER-DOWN. When powered down, both outputs of the differential output pair will drive a logic-high level, and the
single-ended QD1output will be in Hi-Z state.
The differential outputs may individually choose one of several different output voltage swings: 350mV, 500mV or 750mV, measured
single-ended.
Note that under pin-control, all differential outputs within an output bank will assume the same configuration. Pin-control does not allow
configuration of individual outputs within a bank.
Pin Control of the Output Frequencies and Protocols
See Table 8, Table 9, Table 10, Table 11 and Table 12, for pin-control settings. All of the output frequencies assume fVCO = 2500MHz. With
different fVCO configurations, the pins may still be used to select the indicated divide ratios for each bank, but the fOUT will be different.
Note that the control pins do not affect the internal register values, but act directly on the output structures. So register values will not change
to match the control input pin selections.
Each output bank may be powered-up / down and enabled / disabled by register bits. In the disabled state, an output will drive a logic low level.
The default state is all outputs enabled. Pin-control does not require register access to enable the outputs. Additionally, individual outputs
within a bank may be powered up / down.
Table 8: Definition of Output Disabled / Power-down
OUTPUT CONDITION
QMNa
nQMNb
QD1
DISABLED (register-control only)
LOW
HIGH
LOW
POWER-DOWN (pin-control or register-control)
HIGH
HIGH
Hi-Z
a. QMN refers to output pins QA[0:3], QB[0:3], QC[0:1] and QD0.
b. nQMN refers to output pins nQA[0:3], nQB[0:3], nQC[0:1] and nQD0.
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8V49NS0312 Datasheet
Table 9: Bank A Divider/ Driver Pin-Control
Table 11: Bank C Divider/ Driver Pin-Control
(3-level control signals)
(3-level control signals)
NA[1]
NA[0]
Output Type
Divide
Ratio
fOUT
(MHz)
NC[1]
NC[0]
Output Type
Divide
Ratio
fOUT
(MHz)
Low
Low
LVPECLa
16
156.25
Low
Low
LVPECLa
8
312.5
Low
Middle
LVPECL
20
125
Low
Middle
LVPECL
16
156.25
Low
High
LVPECL
25
100
Low
High
LVPECL
20
125
Middle
Low
LVPECL
100
25
Middle
Low
LVPECL
100
25
Middle
Middle
POWER-DOWN
c
b
-
-
Middle
Middle
POWER-DOWN
c
b
-
Middle
High
LVDS
16
156.25
Middle
High
LVDS
20
125
High
Low
LVDS
20
125
High
Low
LVDS
25
100
High
Middle
LVDS
25
100
High
Middle
LVDS
50
50
High
High
LVDS
50
50
High
High
LVDS
100
25
a. Under pin control, all outputs of the bank are LVPECL using 750mV output swing.
b. No active receivers should be connected to QA outputs.
c. Under pin control, all outputs of the bank are LVDS using 350mV output swing.
a. Under pin control, all outputs of the bank are LVPECL using 750mV output swing.
b. No active receivers should be connected to QC outputs.
c. Under pin control, all outputs of the bank are LVDS using 350mV output swing.
Table 10: Bank B Divider/ Driver Pin-Control
Table 12: Bank D Divider/ Driver Pin-Control
(3-level control signals)
(3-level control signals)
NB[1]
NB[0]
Divide
Ratio
fOUT
(MHz)
a
Output Type
Low
Low
LVPECL
16
156.25
Low
Middle
LVPECL
20
125
Low
High
LVPECL
25
100
Middle
Low
LVPECL
100
25
Middle
Middle
-
-
POWER-DOWN
b
QD1
Output
Type
Divide
Ratio
fOUT
(MHz)
100
ND[1]
ND[0]
QD0
Output Type
Low
Low
LVDSa
Hi-Z
25
Low
Middle
LVDS
Hi-Z
50
Low
Middle
High
Low
LVDS
LVDS
Middle Middle POWER-DOWNc
c
50
b
Hi-Z
18.75
b
133.333
66.667
Hi-Z
37.5
Hi-Z
-
-
LVCMOS
75
33.333
Hi-Z
100
25
Middle
High
LVDSc
16
156.25
Middle
High
POWER-DOWN
High
Low
LVDS
20
125
High
Low
LVDS
High
Middle
LVDS
25
100
High
Middle
LVDS
Hi-Z
20
125
50
High
High
LVDS
LVCMOS
1
fINd
High
High
LVDS
50
a. Under pin control, all outputs of the bank are LVDS using 350mV output swing.
b. Generated from Fractional divider.
c. No active receivers should be connected to QD0 output.
d. This bypasses the input frequency directly to the output.
a. Under pin control, all outputs of the bank are LVPECL using 750mV output swing.
b. No active receivers should be connected to QB outputs.
c. Under pin control, all outputs of the bank are LVDS using 350mV output swing.
©2019 Integrated Device Technology, Inc.
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8V49NS0312 Datasheet
Device Start-up and Reset Behavior
The 8V49NS0312 has an internal power-on reset (POR) circuit.The POR circuit will remain active for a maximum of 175msec after device
power-up.
While in the reset state (POR active), the device will operate as follows:
▪
▪
▪
▪
▪
All registers will return to & be held in their default states as indicated in the applicable register description.
All internal state machines will be in their reset conditions.
The serial interface will not respond to read or write cycles.
All clock outputs will be enabled.
Lock status will be cleared.
Upon the internal POR circuit expiring, the device will exit reset and begin self-configuration.
Self-configuration will consist of loading appropriate default values into each register as indicated by the control input pins and the defaults
indicated in the register descriptions.
Once the full configuration has been loaded, the device will respond to accesses on the serial port and will attempt to lock the PLL to the input
frequency and begin operation. Once the PLL is locked, all the outputs derived from it will be synchronized.
©2019 Integrated Device Technology, Inc.
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April 24, 2019
8V49NS0312 Datasheet
Serial Control Port Description
Serial Control Port Configuration Description
The device has a serial control port capable of responding as a slave in an I2C compatible configuration at a base address of 1101100b, to
allow access to any of the internal registers for device programming or examination of internal status.
All registers are configured to have default values. See the specifics for each register for details. Default values for registers will be set after
reset by the configuration pins.
Any changes to the configuration pins will result in the appropriate register(s) being changed to reflect the new pin-controlled setup. Any such
change while the part is operating may result in glitches on output clocks, even if those particular clocks are not being reconfigured.
I2C Mode Operation
The I2C interface is designed to fully support v1.2 of the I2C Specification for Normal and Fast mode operation. The device acts as a slave
device on the I2C bus at 100kHz or 400kHz using a fixed base address of 1101100b. The interface accepts byte-oriented block write and block
read operations. One address byte specifies the register address of the byte position of the first register to write or read. Data bytes (registers)
are accessed in sequential order from the lowest to the highest byte (most significant bit first). Read and write block transfers can be stopped
after any complete byte transfer. During a write operation, data will not be moved into the registers until the STOP bit is received, at which
point, all data received in the block write will be written simultaneously.
For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors have
a size of 51k typical.
Current Read
S
Dev Addr + R
A
Data X
A
Data X +1
A
A
Data n
A
P
Sequential Read
S
Dev Addr + W
A
Offset Addr X
A
A
Offset Addr X
A
Sr
Dev Addr + R
A
Data X
Data X +1
A
A
Data X +1
A
A
Data n
A
P
Sequential Write
S
Dev Addr + W
from master to slave
from slave to master
Data X
A
A
Data n
A
P
NOTE:
Data X refers to the data at Offset Addr X,
Data X+1 refers to the data at Offset Addr +1, etc.
S = start
Sr = repeated start
A = acknowledge
A = non-acknowledge
P = stop
Figure 2: I2C Slave Read and Write Cycle Sequencing
©2019 Integrated Device Technology, Inc.
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8V49NS0312 Datasheet
Register Description
Table 13: Register Blocks
Register Ranges Offset (Hex)
Register Block Description
00 - 08
Prescaler & PLL Control Registers
09 - 0F
Reserveda
10 - 17
Bank A Control Registers
18 - 1F
Bank B Control Registers
20 - 27
Bank C Control Registers
28 - 31
Bank D Control Registers
32 - 37
Reserved
38 - 3C
Reserved
3D - 40
Device Control Registers
41 - 4B
Reserved
4C - 4F
Reserved
50 - FF
Reserved
a. Reserved registers should not be written to and have indeterminate read values.
©2019 Integrated Device Technology, Inc.
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8V49NS0312 Datasheet
Table 14: Prescaler & PLL Control Register Bit Field Locations and Descriptions
Prescaler & PLL Control Register Block Field Locations
Address (Hex)
D7
D6
00
Rsvd
Rsvd
D5
D4
D3
D2
D1
D0
PS[5:0]
01
Rsvd
02
FDP
Rsvd
FIN_CTL
03
OSC_LOW
Rsvd
04
Rsvd
M[8]
05
M[7:0]
06
Rsvd
07
Rsvd
08
Rsvd
CP[4:0]
Prescaler & PLL Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
PS[5:0]
R/W
000000b
FDP
R/W
1b
Input frequency doubler:
0 = disabled
1 = enabled
FIN_CTL
R/W
0b
Prescaler and PLL Configuration Control:
0 = PS[5:0], FDP and M settings determined by FIN[1:0] control pins
1 = PS[5:0], FDP and M settings determined by register settings over I2C
OSC_LOW
R/W
0b
Crystal oscillator gain control selection:
0 = normal gain for crystal frequencies of 25MHz and up
1 = low gain for crystal frequencies less than 25MHz
M[8:0]
R/W
019h
CP[4:0]
R/W
11001b
Rsvd
R/W
-
©2019 Integrated Device Technology, Inc.
Description
Prescaler - scales input frequency by the value:
00h = Reserved
01h - 7Fh = divide by the value used (e.g. 04 = divide-by-4)
PLL Feedback divider ratio:
000h - 003h = Reserved (do not use)
004h - 1FFh = divide fVCO by the value
PLL Charge Pump Current Control:
ICP = 200μA x (CP[4:0] + 1).
Max. charge pump current is 6.4 mA. Default setting is 5.2mA: ((25+1) x 200μA).
Reserved. Always write 0 to this bit location. Read values are not defined.
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8V49NS0312 Datasheet
Table 15: Bank A Control Register Bit Field Locations and Descriptions
Bank A Control Register Block Field Locations
Address (Hex)
D7
10
D6
D5
D4
D2
D1
D0
NA[5:0]
11
12
D3
Rsvd
Rsvd
PD_A
Rsvd
13
NA_CTL
Rsvd
14
PD_QA0
Rsvd
STY_QA0
AMP_QA0[1:0]
15
PD_QA1
Rsvd
STY_QA1
AMP_QA1[1:0]
16
PD_QA2
Rsvd
STY_QA2
AMP_QA2[1:0]
17
PD_QA3
Rsvd
STY_QA3
AMP_QA3[1:0]
Bank A Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
Description
Divider ratio for Bank A:
Any changes made to this register will not take effect until the INIT_CLK register bit is
toggled.
NA[5:0]
PD_A
NA_CTL
PD_QAx
R/W
R/W
R/W
R/W
©2019 Integrated Device Technology, Inc.
0Dh
00 0000b = Reserved
00 0001b = ÷1
00 0010b = ÷2
00 0011b = ÷3
00 0100b = ÷4
00 0101b = ÷5
00 0110b = ÷6
00 0111b = ÷8
00 1000b = ÷9
00 1001b = ÷10
00 1010b = ÷12
00 1011b = ÷14
00 1100b = ÷15
00 1101b = ÷16
00 1110b = ÷18
00 1111b = ÷20
01 0000b = ÷21
01 0001b = ÷22
01 0010b = ÷24
01 0011b = ÷25
01 0100b = ÷27
01 0101b = ÷28
01 0110b = ÷30
01 0111b = ÷32
01 1000b = ÷33
01 1001b = ÷35
01 1010b = ÷36
01 1011b = ÷40
01 1100b = ÷42
01 1101b = ÷44
01 1110b = ÷45
01 1111b = ÷48
10 0000b = ÷50
10 0001b = ÷54
10 0010b = ÷55
10 0011b = ÷56
10 0100b = ÷60
10 0101b = ÷64
10 0110b = ÷66
10 0111b = ÷70
10 1000b = ÷72
10 1001b = ÷80
10 1010b = ÷84
10 1011b = ÷88
10 1100b = ÷90
10 1101b = ÷96
10 1110b = ÷100
10 1111b = ÷108
11 0000b = ÷110
11 0001b = ÷112
11 0010b = ÷120
11 0011b = ÷128
11 0100b = ÷132
11 0101b = ÷140
11 0110b = ÷144
11 0111b = ÷160
11 1000b = ÷176
11 1001b = ÷180
11 1010b = ÷200
11 1011b = ÷220
11 1100b = Reserved
11 1101b = Reserved
11 1110b = Reserved
11 1111b = Reserved
0b
Power-down Bank A:
0 = Bank A & all QA outputs powered and operate normally
1 = Bank A & all QA outputs powered-down - no active receivers should be connected
to QA outputs. When powering-down the output bank, it is recommended to also write
a ‘1’ to the PD_QAx registers.
0b
Bank A Configuration Control:
0 = NA[5:0], PD_A, EN_A, STY_Ax and AMP_Ax[1:0] settings determined by NA[1:0]
control pins
1 = NA[5:0], PD_A, EN_A, STY_Ax and AMP_Ax[1:0] settings determined by register
settings over I2C
0b
Power-down Output QAx:
0 = QAx output powered and operates normally
1 = QAx output powered-down - no active receivers should be connected to the QAx
output
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8V49NS0312 Datasheet
Bank A Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
STY_QAx
R/W
0b
Output Style for Output QAx:
0 = QAx is LVDS
1 = QAx is LVPECL
Output Amplitude for Output QAx (measured single-ended):
00 = 350mV
01 = 500mV
10 = 750mV
11 = Reserved
AMP_QAx[1:0]
R/W
00b
Rsvd
R/W
-
©2019 Integrated Device Technology, Inc.
Description
Reserved. Always write 0 to this bit location. Read values are not defined.
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8V49NS0312 Datasheet
Table 16: Bank B Control Register Bit Field Locations and Descriptions
Bank B Control Register Block Field Locations
Address (Hex)
D7
18
D6
D5
D4
D2
D1
D0
NB[5:0]
19
1A
D3
Rsvd
Rsvd
PD_B
Rsvd
1B
NB_CTL
Rsvd
1C
PD_QB0
Rsvd
STY_QB0
AMP_QB0[1:0]
1D
PD_QB1
Rsvd
STY_QB1
AMP_QB1[1:0]
1E
PD_QB2
Rsvd
STY_QB2
AMP_QB2[1:0]
1F
PD_QB3
Rsvd
STY_QB3
AMP_QB3[1:0]
Bank B Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
Description
Divider ratio for Bank B:
Any changes made to this register will not take effect until the INIT_CLK register bit is
toggled.
NB[5:0]
PD_B
NB_CTL
PD_QBx
R/W
R/W
R/W
R/W
©2019 Integrated Device Technology, Inc.
0Dh
00 0000b = Reserved
00 0001b = ÷1
00 0010b = ÷2
00 0011b = ÷3
00 0100b = ÷4
00 0101b = ÷5
00 0110b = ÷6
00 0111b = ÷8
00 1000b = ÷9
00 1001b = ÷10
00 1010b = ÷12
00 1011b = ÷14
00 1100b = ÷15
00 1101b = ÷16
00 1110b = ÷18
00 1111b = ÷20
01 0000b = ÷21
01 0001b = ÷22
01 0010b = ÷24
01 0011b = ÷25
01 0100b = ÷27
01 0101b = ÷28
01 0110b = ÷30
01 0111b = ÷32
01 1000b = ÷33
01 1001b = ÷35
01 1010b = ÷36
01 1011b = ÷40
01 1100b = ÷42
01 1101b = ÷44
01 1110b = ÷45
01 1111b = ÷48
10 0000b = ÷50
10 0001b = ÷54
10 0010b = ÷55
10 0011b = ÷56
10 0100b = ÷60
10 0101b = ÷64
10 0110b = ÷66
10 0111b = ÷70
10 1000b = ÷72
10 1001b = ÷80
10 1010b = ÷84
10 1011b = ÷88
10 1100b = ÷90
10 1101b = ÷96
10 1110b = ÷100
10 1111b = ÷108
11 0000b = ÷110
11 0001b = ÷112
11 0010b = ÷120
11 0011b = ÷128
11 0100b = ÷132
11 0101b = ÷140
11 0110b = ÷144
11 0111b = ÷160
11 1000b = ÷176
11 1001b = ÷180
11 1010b = ÷200
11 1011b = ÷220
11 1100b = Reserved
11 1101b = Reserved
11 1110b = Reserved
11 1111b = Reserved
0b
Power-down Bank B:
0 = Bank B & all QB outputs powered and operate normally
1 = Bank B & all QB outputs powered-down - no active receivers should be connected
to QB outputs
0b
Bank A Configuration Control:
0 = NB[5:0], PD_B, EN_B, STY_Bx and AMP_Bx[1:0] settings determined by NB[1:0]
control pins
1 = NB[5:0], PD_B, EN_B, STY_Bx and AMP_Bx[1:0] settings determined by register
settings over I2C
0b
Power-down Output QBx:
0 = QBx output powered and operates normally
1 = QBx output powered-down - no active receivers should be connected to the QBx
output. When powering-down the output bank, it is recommended to also write a ‘1’ to
the PD_QBx registers.
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8V49NS0312 Datasheet
Bank B Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
STY_QBx
R/W
0b
Output Style for Output QBx:
0 = QBx is LVDS
1 = QBx is LVPECL
Output Amplitude for Output QBx (measured single-ended):
00 = 350mV
01 = 500mV
10 = 750mV
11 = Reserved
AMP_QBx[1:0]
R/W
00b
Rsvd
R/W
-
©2019 Integrated Device Technology, Inc.
Description
Reserved. Always write 0 to this bit location. Read values are not defined.
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8V49NS0312 Datasheet
Table 17: Bank C Control Register Bit Field Locations and Descriptions
Bank C Control Register Block Field Locations
Address (Hex)
D7
20
D6
D5
D4
D2
D1
D0
NC[5:0]
21
22
D3
Rsvd
Rsvd
PD_C
Rsvd
23
NC_CTL
Rsvd
24
PD_QC0
Rsvd
STY_QC0
AMP_QC0[1:0]
25
PD_QC1
Rsvd
STY_QC1
AMP_QC1[1:0]
26
Rsvd
27
Rsvd
Bank C Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
Description
Divider ratio for Bank C:
Any changes made to this register will not take effect until the INIT_CLK register bit is
toggled.
NC[5:0]
PD_C
NC_CTL
PD_QCx
R/W
R/W
R/W
R/W
©2019 Integrated Device Technology, Inc.
0Dh
00 0000b = Reserved
00 0001b = ÷1
00 0010b = ÷2
00 0011b = ÷3
00 0100b = ÷4
00 0101b = ÷5
00 0110b = ÷6
00 0111b = ÷8
00 1000b = ÷9
00 1001b = ÷10
00 1010b = ÷12
00 1011b = ÷14
00 1100b = ÷15
00 1101b = ÷16
00 1110b = ÷18
00 1111b = ÷20
01 0000b = ÷21
01 0001b = ÷22
01 0010b = ÷24
01 0011b = ÷25
01 0100b = ÷27
01 0101b = ÷28
01 0110b = ÷30
01 0111b = ÷32
01 1000b = ÷33
01 1001b = ÷35
01 1010b = ÷36
01 1011b = ÷40
01 1100b = ÷42
01 1101b = ÷44
01 1110b = ÷45
01 1111b = ÷48
10 0000b = ÷50
10 0001b = ÷54
10 0010b = ÷55
10 0011b = ÷56
10 0100b = ÷60
10 0101b = ÷64
10 0110b = ÷66
10 0111b = ÷70
10 1000b = ÷72
10 1001b = ÷80
10 1010b = ÷84
10 1011b = ÷88
10 1100b = ÷90
10 1101b = ÷96
10 1110b = ÷100
10 1111b = ÷108
11 0000b = ÷110
11 0001b = ÷112
11 0010b = ÷120
11 0011b = ÷128
11 0100b = ÷132
11 0101b = ÷140
11 0110b = ÷144
11 0111b = ÷160
11 1000b = ÷176
11 1001b = ÷180
11 1010b = ÷200
11 1011b = ÷220
11 1100b = Reserved
11 1101b = Reserved
11 1110b = Reserved
11 1111b = Reserved
0b
Power-down Bank C:
0 = Bank C & all QC outputs powered and operate normally
1 = Bank C & all QC outputs powered-down - no active receivers should be connected
to QC outputs
0b
Bank C Configuration Control:
0 = NC[5:0], PD_C, EN_C, STY_Cx and AMP_Cx[1:0] settings determined by NC[1:0]
control pins
1 = NC[5:0], PD_C, EN_C, STY_Cx and AMP_Cx[1:0] settings determined by register
settings over I2C
0b
Power-down Output QCx:
0 = QCx output powered and operates normally
1 = QCx output powered-down - no active receivers should be connected to the QCx
output. When powering-down the output bank, it is recommended to also write a ‘1’ to
the PD_QCx registers.
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8V49NS0312 Datasheet
Bank C Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
STY_QCx
R/W
0b
Output Style for Output QCx:
0 = QCx is LVDS
1 = QCx is LVPECL
Output Amplitude for Output QCx (measured single-ended):
00 = 350mV
01 = 500mV
10 = 750mV
11 = Reserved
AMP_QCx[1:0]
R/W
00b
Rsvd
R/W
-
©2019 Integrated Device Technology, Inc.
Description
Reserved. Always write 0 to this bit location. Read values are not defined.
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8V49NS0312 Datasheet
Table 18: Bank D Control Register Bit Field Locations and Descriptions
Bank D Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
28
ND_FRAC[7:0]
29
ND_FRAC[15:8]
2A
ND_FRAC[23:16]
2B
Rsvd
2C
D1
D0
ND_FINT[3:0]
Rsvd
ND[5:0]
2D
2E
D2
Rsvd
ND_DIVF[1:0]
PD_D
ND_DIV
Rsvd
2F
ND_SRC
ND_CTL
Rsvd
30
PD_QD0
31
PD_QD1
Rsvd
STY_QD0
AMP_QD0[1:0]
Rsvd
Bank D Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
ND_FRAC[23:0]
R/W
600000h
ND_FINT[3:0]
R/W
1001b
Description
Fractional portion of divider ratio for fractional divider for Bank D:
Fraction used in divide ratio = ND_FRAC[23:0] / 224
Integer portion of divider ratio for fractional divider for Bank D:
0h - 4h= Reserved
5h - Fh = divide by the value used (e.g. 5 = divide-by-5)
Divider ratio for Bank D:
Any changes made to this register will not take effect until the INIT_CLK register bit is
toggled.
ND[5:0]
R/W
0Dh
00 0000b = Reserved
00 0001b = ÷ 1
00 0010b = ÷ 2
00 0011b = ÷ 3
00 0100b = ÷ 4
00 0101b = ÷ 5
00 0110b = ÷ 6
00 0111b = ÷ 8
00 1000b = ÷ 9
00 1001b = ÷ 10
00 1010b = ÷ 12
00 1011b = ÷ 14
00 1100b = ÷ 15
00 1101b = ÷ 16
00 1110b = ÷ 18
00 1111b = ÷ 20
01 0000b = ÷ 21
01 0001b = ÷ 22
01 0010b = ÷ 24
01 0011b = ÷ 25
01 0100b = ÷ 27
01 0101b = ÷ 28
01 0110b = ÷ 30
01 0111b = ÷ 32
01 1000b = ÷ 33
01 1001b = ÷ 35
01 1010b = ÷ 36
01 1011b = ÷ 40
01 1100b = ÷ 42
01 1101b = ÷ 44
01 1110b = ÷ 45
01 1111b = ÷ 48
10 0000b = ÷ 50
10 0001b = ÷ 54
10 0010b = ÷ 55
10 0011b = ÷ 56
10 0100b = ÷ 60
10 0101b = ÷ 64
10 0110b = ÷ 66
10 0111b = ÷ 70
10 1000b = ÷ 72
10 1001b = ÷ 80
10 1010b = ÷ 84
10 1011b = ÷ 88
10 1100b = ÷ 90
10 1101b = ÷ 96
10 1110b = ÷ 100
10 1111b = ÷ 108
11 0000b = ÷ 110
11 0001b = ÷ 112
11 0010b = ÷ 120
11 0011b = ÷ 128
11 0100b = ÷ 132
11 0101b = ÷ 140
11 0110b = ÷ 144
11 0111b = ÷ 160
11 1000b = ÷ 176
11 1001b = ÷ 180
11 1010b = ÷ 200
11 1011b = ÷ 220
11 1100b = Reserved
11 1101b = Reserved
11 1110b = Reserved
11 1111b = Reserved
NOTE: QD1 CMOS output should be powered-off or disabled for output frequencies
greater than the maximum listed for it in Table 28.
ND_DIVF[1:0]
R/W
©2019 Integrated Device Technology, Inc.
00b
Post-divider ratio for fractional divider for Bank D:
00 = ÷1
01 = ÷2
10 = ÷4
11 = Reserved
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8V49NS0312 Datasheet
Bank D Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
ND_DIV
R/W
0b
Control which divider is used to provide output frequency for Bank D:
0 = Integer divider D (ND configures this)
1 = Fractional mode (ND_FINT, ND_FRAC and ND_DIVF configure this)
ND_SRC
R/W
0b
Output Source Selection for Bank D:
0 = Bank D is driven from the integer or fractional divider as selected by ND_SRC
1 = Bank D is driven from the input reference (after the mux) with fIN
0b
Power-down Bank D:
0 = Bank D & all QD outputs powered and operate normally
1 = Bank D & all QD outputs powered-down - no active receivers should be connected
to QD0 output. QD1 output is in High-Impedance.
0b
Bank D Configuration Control:
0 = ND[5:0], ND_FRAC[23:0], ND_FINT[3:0], ND_DIVF[1:0], ND_DIV, ND_SRC,
PD_D, EN_D, STY_D0 and AMP_D0[1:0] settings determined by ND[1:0] control pins
1 = ND[5:0], ND_FRAC[23:0], ND_FINT[3:0], ND_DIVF[1:0], ND_DIV, ND_SRC,
PD_D, EN_D, STY_D0 and AMP_D0[1:0] settings determined by register settings
over I2C
PD_D
ND_CTL
R/W
R/W
Description
PD_QDx
R/W
0b
Power-down Output QDx:
0 = QD[0:1] outputs powered and operate normally
1 = QD0 output powered-down - no active receivers should be connected to the QD0
output, QD1 output is in High-Impedance. When powering-down the output bank, it is
recommended to also write a ‘1’ to the PD_QDx registers.
STY_QD0
R/W
0b
Output Style for Output QD0:
0 = QD0 is LVDS
1 = QD0 is LVPECL
Output Amplitude for Output QD0 (measured single-ended):
00 = 350mV
01 = 500mV
10 = 750mV
11 = Reserved
AMP_QD0[1:0]
R/W
00b
Rsvd
R/W
-
©2019 Integrated Device Technology, Inc.
Reserved. Always write 0 to this bit location. Read values are not defined.
24
April 24, 2019
8V49NS0312 Datasheet
Table 19: Device Control Register Bit Field Locations and Descriptions
Device Control Register Block Field Locations
Address (Hex)
D7
3D
INIT_CLK
D6
Rsvd
3E
RELOCK
Rsvd
3F
PB_CAL
Rsvd
40
D5
D4
Rsvd
D3
EN_A
D2
D1
D0
EN_B
EN_C
EN_D
Device Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
Description
INIT_CLK
W/Oa
0b
RELOCK
W/Oa
0b
Writing a ‘1’ to this bit location will cause the PLL to re-lock. This bit will auto-clear.
Writing a ‘1’ to this bit location will cause output dividers to be synchronized. Must be
done every time a divider value is changed if output divider synchronization is desired.
This bit will auto-clear after output divider synchronization is completed.
PB_CAL
W/Oa
0b
Precision Bias Calibration:
Setting this bit to 1 will start the calibration of an internal precision bias current source.
The bias current is used as reference for outputs configured as LVDS and for as
reference for the charge pump currents. This bit will auto-clear after the calibration is
completed.
EN_A
R/W
1b
Output Enable control for Bank A:
0 = Bank A outputs QA[0:3] disabled to logic-low state (QAx = 0, nQAx = 1)
1 = Bank A outputs QA[0:3] enabled
EN_B
R/W
1b
Output Enable control for Bank B:
0 = Bank B outputs QB[0:3] disabled to logic-low state (QBx = 0, nQBx = 1)
1 = Bank B outputs QB[0:3] enabled
EN_C
R/W
1b
Output Enable control for Bank C:
0 = Bank C outputs QC[0:1] disabled to logic-low state (QCx = 0, nQCx = 1)
1 = Bank C outputs QC[0:1] enabled
Output Enable control for Bank D:
0 = Bank D outputs QD[0:1] disabled to logic-low state (QD0 = 0, nQD0 = 1, QD1 = 0)
Note that if Bank D is powered down via the PD_D bit or the QD1 output is powered
down by the PD_QD1 bit, then QD1 will be in High-Impedance regardless of the state
of this bit.
1 = Bank D outputs QD[0:1] enabled
EN_D
R/W
1b
Rsvd
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
a. These bits are read as ‘0’. When a ‘1’ is written to them, it will have the indicated effect and then self-clear back to ‘0’.
©2019 Integrated Device Technology, Inc.
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8V49NS0312 Datasheet
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Table 20: Absolute Maximum Ratings
Item
Rating
Supply Voltage, VCC
3.6V
Inputs, VI
OSCI
Other Inputs
-0.5V to 3.6V
-0.5V to 3.6V
Outputs, VO (LVCMOS)
-0.5V to 3.6V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuous Current
Surge Current
50mA
100mA
Maximum Junction Temperature, tJMAX
125C
Storage Temperature, TSTG
-65C to 150C
©2019 Integrated Device Technology, Inc.
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April 24, 2019
8V49NS0312 Datasheet
DC Electrical Characteristics
Table 21: Power Supply DC Characteristics, VCC_xa = VCCOXb = 3.3V±5%, TA = -40°C to +85°C, VEE = 0V,
Symbol
Parameter
VCC_X
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
VCCA_Xc
Analog Supply Voltage
3.135
3.3
3.465
V
VCCOX
Output Supply Voltage
3.135
3.3
3.465
V
ICC_Xd
Core
Supply Current
ICCA_X
g
Analog
Supply Current
Test Conditions
LVPECL
All Outputs Enabled & Terminatede
73
100
mA
LVDS
All Outputs Enabled & Terminatedf
73
100
mA
LVPECL
All Outputs Enabled & Terminatede
141
169
mA
LVDS
All Outputs Enabled & Terminatedf
141
167
mA
350mV, Outputs Enabled & Terminatede
189
226
mA
500mV, Outputs Enabled & Terminatede
183
217
mA
750mV, Outputs Enabled & Terminatede
172
205
mA
350mV, Outputs Enabled & Terminatedf
84
103
mA
500mV, Outputs Enabled & Terminatedf
101
124
mA
750mV, Outputs Enabled & Terminatedf
130
161
mA
350mV, Outputs Disabled & Unterminated
8
10
mA
500mV, Outputs Disabled & Unterminated
10
12
mA
750mV, Outputs Disabled & Unterminated
12
15
mA
350mV, Outputs Disabled & Unterminated
26
32
mA
500mV, Outputs Disabled & Unterminated
36
43
mA
750mV, Outputs Disabled & Unterminated
51
62
mA
LVPECL
LVDS
ICCOAh
Bank A Output
Supply Current
LVPECL
LVDS
©2019 Integrated Device Technology, Inc.
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April 24, 2019
8V49NS0312 Datasheet
Table 21: Power Supply DC Characteristics, VCC_xa = VCCOXb = 3.3V±5%, TA = -40°C to +85°C, VEE = 0V, Cont.
Symbol
Parameter
Test Conditions
LVPECL
LVDS
ICCOBh
Bank B Output
Supply Current
LVPECL
LVDS
LVPECL
LVDS
ICCOCh
Bank C Output
Supply Current
LVPECL
LVDS
©2019 Integrated Device Technology, Inc.
Typical
Maximum
Units
350mV, Outputs Enabled & Terminatede
196
234
mA
500mV, Outputs Enabled & Terminatede
188
224
mA
750mV, Outputs Enabled & Terminatede
177
211
mA
350mV, Outputs Enabled & Terminatedf
86
105
mA
500mV, Outputs Enabled & Terminatedf
103
126
mA
750mV, Outputs Enabled & Terminatedf
132
163
mA
350mV, Outputs Disabled & Unterminated
9
11
mA
500mV, Outputs Disabled & Unterminated
10
13
mA
750mV, Outputs Disabled & Unterminated
13
16
mA
350mV, Outputs Disabled & Unterminated
27
33
mA
500mV, Outputs Disabled & Unterminated
36
44
mA
750mV, Outputs Disabled & Unterminated
52
62
mA
350mV, Outputs Enabled & Terminatede
109
131
mA
500mV, Outputs Enabled & Terminatede
106
127
mA
750mV, Outputs Enabled & Terminatede
100
120
mA
350mV, Outputs Enabled & Terminatedf
55
67
mA
500mV, Outputs Enabled & Terminatedf
64
78
mA
750mV, Outputs Enabled & Terminatedf
78
95
mA
350mV, Outputs Disabled & Unterminated
1
2
mA
500mV, Outputs Disabled & Unterminated
1
2
mA
750mV, Outputs Disabled & Unterminated
1
2
mA
350mV, Outputs Disabled & Unterminated
1
2
mA
500mV, Outputs Disabled & Unterminated
1
2
mA
750mV, Outputs Disabled & Unterminated
1
2
mA
28
Minimum
April 24, 2019
8V49NS0312 Datasheet
Table 21: Power Supply DC Characteristics, VCC_xa = VCCOXb = 3.3V±5%, TA = -40°C to +85°C, VEE = 0V, Cont.
Symbol
Parameter
Test Conditions
LVPECL
LVDS
ICCODh
Bank D Output
Supply Current
LVPECL
LVDS
LVPECL
IEEh
Power Supply
Current
for VEE
LVPECL
Minimum
Typical
Maximum
Units
350mV, Outputs Enabled & Terminatede
91
114
mA
500mV, Outputs Enabled & Terminatede
89
112
mA
750mV, Outputs Enabled & Terminatede
86
109
mA
350mV, Outputs Enabled & Terminatedf
57
69
mA
500mV, Outputs Enabled & Terminatedf
62
75
mA
750mV, Outputs Enabled & Terminatedf
70
85
mA
350mV, Outputs Disabled & Unterminated
3
5
mA
500mV, Outputs Disabled & Unterminated
3
5
mA
750mV, Outputs Disabled & Unterminated
3
5
mA
350mV, Outputs Disabled & Unterminated
3
5
mA
500mV, Outputs Disabled & Unterminated
3
5
mA
750mV, Outputs Disabled & Unterminated
3
5
mA
350mV, Outputs Enabled & Terminatede
385
470
mA
500mV, Outputs Enabled & Terminatede
394
481
mA
750mV, Outputs Enabled & Terminatede
407
497
mA
350mV, Outputs Disabled & Unterminated
233
277
mA
500mV, Outputs Disabled & Unterminated
236
280
mA
750mV, Outputs Disabled & Unterminated
241
286
mA
a. VCC_x denotes VCC_CP, VCC_CK, VCC_SP.
b. VCCOX denotes VCCOA, VCCOB, VCCOC, VCCOD.
c. VCCA_X denotes VCCA_IN1, VCCA_IN2, VCCA, VCCA_XT.
d. ICC_X denotes ICC_CP, ICC_CK, ICC_SP.
e. Differential outputs terminated 50 to VCCOX - 2V. QD1 output terminated 50to VCCOD/2.
f. Differential outputs terminated 100 across Q and nQ. QD1 output terminated 50to VCCOD/2.
g. ICCA_X denotes ICCA_IN1, ICCA_IN2, ICCA, ICCA_XT.
h. Internal maximum dynamic switching current is included.
©2019 Integrated Device Technology, Inc.
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8V49NS0312 Datasheet
Table 22: LVCMOS DC Characteristics for 3-level Pins, VCC_Xa = VCCOXb = 3.3V±5%, TA = -40°C to +85°C,
VEE = 0V
Symbol
Parameter
Test Conditions
VIH
Input High Voltage
VIM
Input Middle Voltage
VIL
Input Low Voltage
IIH
Input High Current
FIN[1:0],
NA[1:0], NB[1:0],
NC[1:0], ND[1:0]
VCCc = VIN = 3.465V
IIM
Input Middle Current
FIN[1:0],
NA[1:0], NB[1:0],
NC[1:0], ND[1:0]
VIN = VCCc / 2
IIL
Input Low Current
FIN[1:0],
NA[1:0], NB[1:0],
NC[1:0], ND[1:0]
VCCc = 3.465V, VIN = 0V
FIN[1:0],
NA[1:0], NB[1:0],
NC[1:0], ND[1:0]
Minimum
Typical
Maximum
Units
0.7 * VCCc
3.465
V
0.4 * VCCc
0.6 * VCCc
V
-0.3
0.3 * VCCc
V
150
µA
±1
µA
-150
µA
a. VCC_X denotes VCC_CP, VCC_CK, VCC_SP.
b. VCCOX denotes VCCOA, VCCOB, VCCOC, VCCOD.
c. VCC denotes VCCA_IN1, VCC_CK.
Table 23: LVCMOS DC Characteristics for 2-level Pins, VCC_Xa = VCCOXb = 3.3V±5%, TA = -40°C to +85°C,
VEE = 0V
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
Test Conditions
Minimum
Typical
Maximum
Units
0.7 * VCCc
3.465
V
REF_SEL
-0.3
0.3 * VCCc
V
SDATA, SCLK
-0.3
0.15 * VCCc
V
SCLK, SDATA
VCCc = VIN = 3.465V
5
µA
REF_SEL
VCCc = VIN = 3.465V
150
µA
SCLK, SDATA
VCCc= 3.465V, VIN = 0V
-150
µA
REF_SEL
VCCc = 3.465V, VIN = 0V
-5
µA
2.2
V
IIL
Input Low Current
VOH
Output High Voltage
LOCK
IOH = -4mA
VOL
Output Low Voltage
SDATA, LOCK
IOL = 4mA
0.45
V
a. VCC_X denotes VCC_CP, VCC_CK, VCC_SP.
b. VCCOX denotes VCCOA, VCCOB, VCCOC, VCCOD.
c. VCC denotes VCC_CK.
©2019 Integrated Device Technology, Inc.
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8V49NS0312 Datasheet
Table 24: Differential Input DC Characteristics, VCC_Xa = VCCOXb = 3.3V±5%, TA = -40°C to +85°C, VEE = 0V
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
IIH
Input
High Current
CLK_IN,
nCLK_IN
VCCc = VIN = 3.465V
150
µA
Input
Low Current
CLK_IN
VCCc = 3.465V, VIN = 0V
-5
µA
IIL
nCLK_IN
VCCc = 3.465V, VIN = 0V
-150
µA
VPP
Peak-to-Peak
Voltaged, e
CLK_IN,
nCLK_IN
0.2
1.4
V
VCMR
Common Mode
Input Voltaged, e
CLK_IN,
nCLK_IN
VEE + 1.1
VCCc – 0.3
V
a. VCC_X denotes VCC_CP, VCC_CK, VCC_SP.
b. VCCOX denotes VCCOA, VCCOB, VCCOC, VCCOD.
c. VCC denotes VCC_CK.
d. Common mode voltage is defined as the cross point.
e. Input voltage cannot be less than VEE - 300mV or more than VCC.
Table 25: LVPECL Output DC Characteristics (Qmna), VCC_Xb = VCCOXc = 3.3V±5%, TA = -40°C to +85°C,
VEE = 0V
Symbol
VOH
VOL
VSWING
Parameter
Output High Voltaged
Output Low Voltaged
Single-ended Peak-to-Peak
Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
350mV Amplitude setting
VCCOX – 1.1
VCCOX – 0.8
500mV Amplitude setting
VCCOX – 1.1
VCCOX – 0.8
750mV Amplitude setting
VCCOX – 1.1
VCCOX – 0.8
350mV Amplitude setting
VCCOX – 1.5
VCCOX – 1.1
500mV Amplitude setting
VCCOX – 1.6
VCCOX – 1.3
750mV Amplitude setting
VCCOX – 1.8
VCCOX – 1.5
350mV Amplitude setting
280
350
420
500mV Amplitude setting
430
500
570
750mV Amplitude setting
630
700
770
Units
V
V
mV
a. In this table, Qmn denotes the differential outputs QA[0:3], QB[0:3], QC[0:1] or QD0. Note that QD1 is not included because it is not differential.
b. VCC_X denotes VCC_CP, VCC_CK, VCC_SP.
c. VCCOX denotes VCCOA, VCCOB, VCCOC, VCCOD.
d. Outputs terminated with 50 to VCCOX – 2V.
©2019 Integrated Device Technology, Inc.
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8V49NS0312 Datasheet
Table 26: LVDS Output DC Characteristics (Qmna), VCC_Xb = VCCOXc = 3.3V±5%, TA = -40°C to +85°C, VEE = 0V
Symbol
VOD
VOD
VOS
VOS
Parameter
Differential Output Voltage
Test Conditions
Minimum
Typical
Maximum
350mV Amplitude setting
0.27
0.32
0.37
500mV Amplitude setting
0.39
0.46
0.53
750mV Amplitude setting
0.62
0.69
0.76
VOD Magnitude Change
Offset Voltaged, e, f
50
350mV Amplitude setting
1.9
2.3
2.7
500mV Amplitude setting
1.8
2.2
2.6
750mV Amplitude setting
1.7
2.1
2.5
VOS Magnitude Change
50
Units
V
mV
V
mV
a. In this table, Qmn denotes the differential outputs QA[0:3], QB[0:3], QC[0:1] or QD0. Note that QD1 is not included because it is not differential.
b. VCC_X denotes VCC_CP, VCC_CK, VCC_SP.
c. VCCOX denotes VCCOA, VCCOB, VCCOC, VCCOD.
d. No external DC pulldown resistor.
e. Loading condition is with 100 across the differential output.
f. Offset voltage (VOS) changes with supply voltage VCCOX.
Table 27: Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
10
CL = 12pF
CL = 18pF
15
Load Capacitance (CL)
Maximum
Units
50
MHz
60
30
12
Maximum Crystal Drive Level
-100
32
pF
W
200
Frequency Stability (total)
©2019 Integrated Device Technology, Inc.
Typical
Fundamental
100
ppm
April 24, 2019
8V49NS0312 Datasheet
AC Electrical Characteristics
Table 28: AC Characteristics,a VCC_Xb = VCCOXc = 3.3V+5%, TA = -40°C to +85°C, VEE = 0V
Symbol
Parameter
fVCO
VCO Frequency
fPFD
Phase / Frequency Detector
Frequency
fOUT
Output
Frequency
Test Conditions
QD0, nQD0
QD1
Bank A
tsk(b)
Bank Skewd, e, f
Bank B
Bank C
t R / tF
odc
Output
Rise/Fall Time
Output
Duty Cycleg
Typical
Units
2400
2500
MHz
5
200
MHz
10.91
2500
MHz
Integer Divider Selected
10.91
2500
MHz
Fractional Divider Selected
20
138
MHz
Integer Divider Selected
10.91
250
MHz
Fractional Divider Selected
20
138
MHz
45
Same Frequency and Output Type
Only valid for skew between outputs in
the same bank
45
ps
20
QA[0:3]
nQA[0:3]
QB[0:3]
nQB[0:3]
QC[0:1]
nQC[0:1]
30% to 70%
QD0, nQD0
30% to 70%
30
90
200
QD1
30% to 70%
220
375
600
FOUT 1250MHz
45
50
55
%
FOUT > 1250MHz
40
50
60
%
FOUT < 156.25MHz
45
50
55
%
FOUT 156.25MHz
40
50
60
%
40
100
ms
QA[0:3]
nQA[0:3]
QB[0:3]
nQB[0:3]
QC[0:1]
nQC[0:1],
QD0, nQD0
QD1
tLOCK
Maximum
QA[0:3]
nQA[0:3]
QB[0:3]
nQB[0:3]
QC[0:1]
nQC[0:1]
Minimum
30
60
110
ps
PLL Lock Timeh
a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
b. VCC_X denotes VCC_CP, VCC_CK, VCC_SP.
c. VCCOX denotes VCCOA, VCCOB, VCCOC, VCCOD.
d. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crosspoints.
e. This parameter is defined in accordance with JEDEC Standard 65.
f. This parameter is guaranteed by characterization. Not tested in production
g. Duty Cycle of bypassed signals (input reference clock or crystal input) is not adjusted by the device.
h. PLL Lock Time is defined as time from input clock availability to frequency locked output. The following loop filter component values may be used: RZ = 221Ω, CZ = 4.7μF
CP = 30pf. Refer to Applications Information.
©2019 Integrated Device Technology, Inc.
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8V49NS0312 Datasheet
Table 29: Qmna and QD1 Phase Noise and Jitter Characteristics, VCC_Xb = VCCOXc = 3.3V+5%,
TA = -40°C to +85°Cd, e, f, g, h, i
Symbol
tjit(Ø)j
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
110
fs
RMS Phase
Jitter Random
Qmn =
156.25MHzk
Integration Range: 12kHz – 20MHz
87
RMS Phase
Jitter Random
Qmn = 125MHz
Integration Range: 12kHz – 20MHz
84
fs
RMS Phase
Jitter Random
Qmn = 100MHz
Integration Range: 12kHz – 20MHz
94
fs
RMS Phase
Jitter Random
Qmn = 25MHz
Integration Range: 12kHz – 5MHz
126
fs
RMS Phase
Jitter Random
QD0 =
133.33MHz
(fractional)l
Integration Range: 12kHz – 20MHz
180
fs
RMS Phase
Jitter Random
QD1= 125MHz
Integration Range: 12kHz – 20MHz
170
fs
QAn = 125MHz
Integration Range: 12kHz – 20MHz
85
fs
QBn = 100MHz
Integration Range: 12kHz – 20MHz
88
fs
QCn = 25MHz
Integration Range: 12kHz – 5MHz
137
fs
QD0 =
133.33MHz
(fractional)
Integration Range: 12kHz – 20MHz
170
fs
RMS Phase
Jitter Randomm
N(10)n
Single-Side Band Noise Power,
10Hz from Carrier
Qmn = 156.25MHz
-75.1
dBc/Hz
N(100)n
Single-Side Band Noise Power,
100Hz from Carrier
Qmn = 156.25MHz
-109.6
dBc/Hz
N(1k)n
Single-Side Band Noise Power,
1kHz from Carrier
Qmn = 156.25MHz
-128.9
dBc/Hz
N(10k)n
Single-Side Band Noise Power,
10kHz from Carrier
Qmn = 156.25MHz
-137.6
dBc/Hz
N(100k)n
Single-Side Band Noise Power,
100kHz from Carrier
Qmn = 156.25MHz
-143.0
dBc/Hz
N(1M)n
Single-Side Band Noise Power,
1MHz from Carrier
Qmn = 156.25MHz
-157.5
dBc/Hz
N(10M)n
Single-Side Band Noise Power,
10MHz from Carrier
Qmn = 156.25MHz
-163.1
dBc/Hz
N()n
Noise Floor (30MHz from Carrier)
Qmn = 156.25MHz
-163.1
dBc/Hz
a. In this table, Qmn denotes the differential outputs QA[0:3], QB[0:3], QC[0:1] or QD0. Note that QD1 is not included because it is not differential.
b. VCC_X denotes VCC_CP, VCC_CK, VCC_SP.
c. VCCOX denotes VCCOA, VCCOB, VCCOC, VCCOD.
d. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
e. All outputs enabled and configured for the same output frequency unless otherwise noted.
f. Characterized using a 50MHz, CL = 18pF crystal, unless otherwise noted.
g. Measured on Qmn configured as ÷16 and ÷20.
h. VCCA requires a voltage regulator. Voltage supplied to VCCA should be derived from a regulator with a typical power supply rejection ratio of 80dB at 1kHz and ultra low
noise generation with a typical value of 3nV/Hz at 10kHz and 7nV/Hz at 1kHz.
i. Characterized with 750mV output voltage swing configuration for all differential outputs.
©2019 Integrated Device Technology, Inc.
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April 24, 2019
8V49NS0312 Datasheet
j. The following loop filter component values were used: RZ = 221, CZ = 4.7µF, CP = 30pF. PLL Charge Pump Current Control set at 5.2mA.
k. Characterized using a 31.25MHz, CL = 18pF crystal, (FOX P/N FX277LF-31.25-1).
l. QAx = 156.25MHz, QBx = 156.25MHz, QCx = 156.25MHz.
m. QAx = 156.25MHz, QBx = 100MHz, QCx = 25MHz, QD0 = 133.33MHz (fractional).
n. Measured using a 50MHz, 12pF crystal as input reference. The following loop filter components were used: RZ = 150, CZ = 0.1µF, CP = 200pF.
PLL Charge Pump Current Control set at 6.4mA.
Noise Power dBc
Typical Phase Noise at 156.25MHza
Offset Frequency (Hz)
a: Measured using a 50MHz, 12pF crystal as input reference. The following loop filter components were used: RZ = 150, CZ = 0.1µF, CP = 200pF.
PLL Charge Pump Current Control set at 6.4mA.
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April 24, 2019
8V49NS0312 Datasheet
Noise Power dBc
Typical Phase Noise at 125MHza
Offset Frequency (Hz)
a. Measured using a 50MHz, 12pF crystal as input reference. The following loop filter components were used: RZ = 150, CZ = 0.1µF, CP = 200pF.
PLL Charge Pump Current Control set at 6.4mA.
©2019 Integrated Device Technology, Inc.
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8V49NS0312 Datasheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-up and/or pull-down resistors; additional resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs should be left floating. It is recommended that there is no trace attached.
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating there should be no trace attached.
LVCMOS Outputs
QD1 output can be left floating if unused. There should be no trace attached.
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8V49NS0312 Datasheet
Overdriving the XTAL Interface
The OSCI input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The OSCO
pin can be left floating. The amplitude of the input signal should be between 500mV and 1.2V and the slew rate should not be less than
0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal
interference with the power rail and to reduce internal noise. Figure 3 shows an example of the interface diagram for a high speed 3.3V
LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals 90.
In addition, matched termination at the crystal input will further attenuate the signal. This can be done in one of two ways. First, R1 and R2 in
parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by
removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS
driver.
OSCO
VCC
R1
100
Ro
C1
Zo = 50Ω
RS
OSCI
0.1μF
Ro + Rs ȍ
R2
100
LVCMOS_Driver
Figure 3: General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 4 shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver
feeding the OSCI input. It is recommended that all components in the schematics be placed in the layout. Though some components might not
be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal
as the input.
OSCO
C2
Zo = 50Ω
OSCI
0.1μF
Zo = 50Ω
LVPECL_Driver
R1
50
R2
50
R3
50
Figure 4: General Diagram for LVPECL Driver to XTAL Input Interface
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8V49NS0312 Datasheet
Wiring the Differential Input to Accept Single-Ended Levels
Figure 5 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 = VCC/2 is generated by the bias
resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the
input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1 in the center of the input voltage swing. For example,
if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the
single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and
the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in
half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50
applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS
driver.
When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can
handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V
and VIH cannot be more than VCC + 0.3V. Suggested edge rate faster than 1V/ns. Though some of the recommended components might not
be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized
and guaranteed by using a differential signal.
Figure 5: Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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8V49NS0312 Datasheet
3.3V Differential Clock Input Interface
CLK/nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figure 6 to Figure 10 show interface examples for the CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 6, the input
termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Figure 6: CLK/nCLK Input Driven by an
Figure 9: CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 7: CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 10: CLK/nCLK Input Driven by a
3.3V LVDS Driver
IDT Open Emitter LVHSTL Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 8: CLK/nCLK Input Driven by a
3.3V HCSL Driver
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8V49NS0312 Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should
be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel
resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the
components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant
devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 11 can
be used with either type of output structure. Figure 12, which can also be used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are
LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output.
Refer to Figure 13, Figure 14 and Figure 15 for additional details on the recommended termination schemes.
Figure 11: Standard LVDS Termination
Figure 12: Optional LVDS Termination
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8V49NS0312 Datasheet
3.3V
3.3V
Z0 = 50Ω
100Ω
Input high
impedance
Z0 = 50Ω
8V9N302
Receiver
Figure 13: DC Termination for LVDS Outputs
Figure 14: AC Termination for LVDS Outputs
3.3V
3.3V
0.1μF
Z0 = 50Ω
0.1μF
Z0 = 50Ω
8V9N32
Internal 50Ω
terminations
Receiver
Figure 15: AC Termination for LVDS outputs used with an Input Clock Receiver with Internal 50 Terminations
and DC Bias.
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8V49NS0312 Datasheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended
only as guidelines.The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to
ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance
techniques should be used to maximize
operating frequency and minimize signal distortion. Figure 16 and Figure 17 show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process variations.
Figure 16: 3.3V LVPECL Output Termination
R3
125Ω
3.3V
R4
125Ω
3.3V
3.3V
Zo = 50Ω
+
_
Input
Zo = 50Ω
R1
84Ω
R2
84Ω
Figure 17: 3.3V LVPECL Output Termination
Figure 16 and Figure 19 show two different LVPECL termination schemes for 750mV amplitude setting which are recommended only as
guidelines. Recommended values of R1/R2/R3/R4 for LVPECL termination (Figure 19; Thevenin Equivalent) for 350mV and 500mV amplitude
settings can be found in the following table.
Table 1. LVPECL Output Termination, VCCOX = 3.3V ±5%
Test Conditions
Bias Voltage
R1
R2
R3
R4
350mV Amplitude Setting
VCCOX – 1.6V
105
105
97.6
97.6
500mV Amplitude Setting
VCCOX – 1.75V
95.3
95.3
107
107
750mV Amplitude Setting
VCCOX – 2.0V
84
84
125
125
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With a fast ramp up VDD, power-up to lock time is:
▪ When CR (pin 25) = 1.0uF, typical lock time is around 108ms
▪ When CR (pin 25) = 0.1uF, typical lock time is around 30ms
VFQFPN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the
Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package,
as shown in Figure 18. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed
pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between
the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder
joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be
connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis
and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when
an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any
solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal
land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These
recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount
Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 18: P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
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8V49NS0312 Datasheet
Schematic Layout
Figure 19 shows an example 8V49NS0312 application schematic operating the device at VCC = 3.3V. This example focuses on functional
connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control
inputs are properly set for the application.
To demonstrate the range of output stage configurations possible, the application schematic assumes that the 8V49NS0312 is programmed
over I2C. For alternative DC coupled LVPECL options please see IDT Application Note, AN-828; for AC coupling options use IDT Application
Note, AN-844.
For a 12pF parallel resonant crystal, tuning capacitors C145 and C146 are recommended for frequency accuracy. Depending on the parasitic
of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load
capacitance specifications can be used. This will require adjusting C145 and C146. For this device, the crystal tuning capacitors are required
for proper operation.
Crystal layout is very important to minimize capacitive coupling between the crystal pads and leads and other metal in the circuit board.
Capacitive coupling to other conductors has two adverse effects; it reduces the oscillator frequency leaving less tuning margin and noise
coupling from power planes and logic transitions on signal traces can pull the phase of the crystal resonance, inducing jitter. Routing I2C under
the crystal is a very common layout error, based on the assumption that it is a low frequency signal and will not affect the crystal oscillation. In
fact, I2C transition times are short enough to capacitively couple into the crystal-oscillator loop if they are routed close enough to the crystal
traces.
In layout, all capacitive coupling to the crystal from any signal trace is to be minimized, that is to the OSCI and OSCO pins, traces to the crystal
pads, the crystal pads and the tuning capacitors. Using a crystal on the top layer as an example, void all signal and power layers under the
crystal connections between the top layer and the ground plane used by the 8V49NS0312. Then calculate the parasitic capacity to the ground
and determine if it is large enough to preclude tuning the oscillator. If the coupling is excessive, particularly if the first layer under the crystal is
a ground plane, a layout option is to void the ground plane and all deeper layers until the next ground plane is reached. The ground connection
of the tuning capacitors should first be made between the capacitors on the top layer, then a single ground via is dropped to connect the tuning
cap ground to the ground plane as close to the 8V49NS0312 as possible as shown in the schematic.
As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power
supply isolation is required. The 8V49NS0312 provides separate power supplies to isolate any high switching noise from coupling into the
internal PLL.
In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB
as close to the power pins as possible. The ferrite bead and the 0.1uF capacitor in each power pin filter should always be placed on the device
side of the board. The other components can be on the opposite side of the PCB if space on the top side is limited. Pull up and pull down
resistors to set configuration pins can all be placed on the PCB side opposite the device side to free up device side area if necessary.
Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. Depending
on the application, the filter may need to be adjusted to get a lower cutoff frequency to adequately attenuate low-frequency noise. Additionally,
good general design practices for power plane voltage stability suggest adding bulk capacitance in the local area of all devices.
For additional layout recommendations and guidelines, contact clocks@idt.com.
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8V49NS0312 Datasheet
Figure 19: 8V49NS0312 Application Schematic
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8V49NS0312 Datasheet
Power Dissipation and Thermal Considerations
The 8V49NS0312 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is
highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions
is enabled.
The 8V49NS0312 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The
ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,
such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable
junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.
The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the
power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your
own specific configuration.
Example 1. LVPECL, 750mV Output Swing
This section provides information on power dissipation and junction temperature when the device differential outputs are configured for
LVPECL level, 750mV output swing. Equations and example calculations are also provided.
Table 30: Power Calculations Configuration #1
Output
Output Style
Output Swing
QA0
LVPECL
750mV
QA1
LVPECL
750mV
QA2
LVPECL
750mV
QA3
LVPECL
750mV
QB0
LVPECL
750mV
QB1
LVPECL
750mV
QB2
LVPECL
750mV
QB3
LVPECL
750mV
QC0
LVPECL
750mV
QC1
LVPECL
750mV
QD0
LVPECL
750mV
QD1
LVCMOS
N/A
1a. Power Dissipation.
The total power dissipation is the sum of the core power plus the power dissipated due to output loading.
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
▪ Power(core)MAX = VCC_MAX * IEE_MAX = 3.465V * 497mA = 1722.1mW
▪ Power(LVPECL outputs)MAX = 34.2mW/Loaded Output pair. Refer to Section 1c.
If all outputs are loaded, the total power is 11 * 34.2mW = 376.2mW
▪ Power (LVCMOS output)MAX(Power dissipation due to loading 50 to VCCO / 2)
Output Current: IOUT = VCCOD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 30)] = 21.66mA
Power Dissipation on the ROUT: Power (ROUT) = ROUT * (IOUT)2 = 30 * (21.66mA)2 = 14.07mW
▪ Total PowerMAX = Power(core) + Power (LVPECL outputs) + Power (LVCMOS output)
= 1722.1mW + 376.2mW +14.07mW = 2112.37mW = 2.112W
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8V49NS0312 Datasheet
1b. Junction Temperature.
Junction temperature, TJ, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, TJ, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
The equation for TJ is as follows: TJ = TA + PD * JA:
TJ = Junction Temperature
TA = Ambient Temperature
PD = Power Dissipation (W) in desired operating configuration
JA = Junction-to-Ambient Thermal Resistance
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance must be used. Assuming no air flow and a
multi-layer board, the appropriate value is 15.6°C/W per Table 32.
Therefore, assuming TA = 85°C and all outputs switching, TJ will be:
85°C + 2.112W * 15.6°C/W = 117.95°C. This is below the limit of 125°C.
This calculation is only an example. TJ will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
1c. Power Dissipation due to output loading.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 20.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 20: LVPECL Driver Circuit and Termination
To calculate worst case power dissipation at the output(s), use the following equations which assume a 50 load, and a termination voltage of
VCCOX - 2V. These are typical calculations.
▪ For logic high, VOUT = VOH_MAX = VCCOX_MAX - 0.8V
(VCCOX_MAX - VOH_MAX) = 0.8V
▪ For logic low, VOUT = VOL_MAX = VCCOX_MAX - 1.5V
(VCCOX_MAX - VOL_MAX) = 1.5V
Pd_H is the power dissipation when the output drives high.
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Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCOX_MAX – 2V))/RL] * (VCCOX_MAX – VOH_MAX) = [(2V – (VCCOX_MAX – VOH_MAX))/RL] * (VCCOX_MAX– VOH_MAX) =
[(2V – 0.8V)/50] * 0.8V = 19.2mW
Pd_L = [(VOL_MAX – (VCCOX_MAX – 2V))/RL] * (VCCOX_MAX – VOL_MAX) = [(2V – (VCCOX_MAX – VOL_MAX))/RL] * (VCCOX_MAX – VOL_MAX) =
[(2V – 1.5V)/50] * 1.5V = 15mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 34.2mW
Example 2. LVDS, 350mV Output Swing
This section provides information on power dissipation and junction temperature when the device differential outputs are configured for LVDS
levels, 350mV output swing. Equations and example calculations are also provided.
Table 31: Power Calculations Configuration #2
Output
Output Style
Output Swing
QA0
LVDS
350mV
QA1
LVDS
350mV
QA2
LVDS
350mV
QA3
LVDS
350mV
QB0
LVDS
350mV
QB1
LVDS
350mV
QB2
LVDS
350mV
QB3
LVDS
350mV
QC0
LVDS
350mV
QC1
LVDS
350mV
QD0
LVDS
350mV
QD1
LVCMOS
N/A
2a. Power Dissipation.
The total power dissipation is the sum of the core power plus the power dissipation due to output loading.
The following is the power dissipation for VCCX = VCCA_X = VCCOX = 3.3V + 5% = 3.465V, which gives worst case results.
▪ PowerMAX = VCCX_MAX * ICCX_MAX + VCCA_X_MAX * ICCA_X_MAX + VCCOX_MAX * ICCOX_MAX
= 3.465V * 100mA + 3.465V * 167mA + 3.465V (103mA + 105mA + 67mA + 69mA)
= 346.5mW + 578.66mW + 1191.96mW = 2117.12mW = 2.117W
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8V49NS0312 Datasheet
2b. Junction Temperature.
Junction temperature, TJ, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, TJ, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
The equation for TJ is as follows: TJ = TA + PD * JA:
TJ = Junction Temperature
TA = Ambient Temperature
PD = Power Dissipation (W) in desired operating configuration
JA = Junction-to-Ambient Thermal Resistance
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance must be used. Assuming no air flow and a
multi-layer board, the appropriate value is 15.6°C/W per Table 32.
Therefore, assuming TA = 85°C and all outputs switching, TJ will be:
85°C + 2.117W * 15.6°C/W = 118.03°C. This is below the limit of 125°C.
This calculation is only an example. TJ will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Reliability Information
Table 32: Thermal Resistance Table for 64-pin VFQFN Package
Symbol
Thermal Parameter
Condition
Value
Unit
JAa
Junction-to-Ambient
No air flow
15.6
°C/W
JC
Junction-to-Case
15.3
°C/W
JB
Junction-to-Board
0.6
°C/W
a. Theta JA (JA) values calculated using an 8-layer PCB (114.3mm x 101.6mm), with 2oz. (70µm) copper plating on all 8 layers, with ePad
connected to 4 ground planes.
Transistor Count
The transistor count for the 8V49NS0312 is: 143,063
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/document/psc/64-vfqfpn-package-outline-drawing-90-x-90-x-09-mm-body-05mm-pitch-epad-60-x-60-mm-nlg64p5
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8V49NS0312 Datasheet
Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8V49NS0312NLGI
IDT8V49NS0312NLGI
64-VFQFPN, Lead-Free
Tray
-40°C to +85°C
8V49NS0312NLGI8
IDT8V49NS0312NLGI
64-VFQFPN, Lead-Free
Tape & Reel
-40°C to +85°C
Revision History
Revision Date
Description of Change
April 24, 2019
▪ Updated Overdriving the XTAL Interface
▪ Updated Termination for 3.3V LVPECL Outputs
▪ Updated the Package Outline Drawings; however, no mechanical changes
November 14, 2017
▪ Updated the QD fractional output divider’s maximum frequency to 138MHz to meet period jitter compliance
(see Table 28)
▪ Updated the Package Outline Drawings; however, no mechanical changes
▪ Completed other minor changes
September 2, 2016
Page 32, Table 27 Crystal Characteristics - added additional spec to Equivalent Series Resistance row.
August 1, 2016
Page 50, Power Dissipation due to output loading. - typographical error
replaced “-” with “=”: For logic low, VOUT = VOL_MAX = VCCOX_MAX - 1.5V, (VCCOX_MAX - VOL_MAX) = 1.5V.
July 11, 2016
Initial release.
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual
property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
©2019 Integrated Device Technology, Inc.
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April 24, 2019
64-VFQFPN, Package Outline Drawing
9.0 x 9.0 x 0.9 mm Body, 0.5mm Pitch, Epad 6.0 x 6.0 mm
NLG64P5, PSC-4147-05, Rev 04, Page 1
64-VFQFPN, Package Outline Drawing
9.0 x 9.0 x 0.9 mm Body, 0.5mm Pitch, Epad 6.0 x 6.0 mm
NLG64P5 , PSC-4147-05, Rev 04, Page 2
Package Revision History
Description
Date Created
Rev No.
Feb 16, 2018
Rev 03
New Format
April 19, 2018
Rev 04
Add Chamfer on Corner Leads
IMPORTANT NOTICE AND DISCLAIMER
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(Rev.1.0 Mar 2020)
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