Jitter Attenuator & FemtoClock® Multiplier
IDT8V89308I
DATA SHEET
General Description
Features
The IDT8V89308I is a PLL based synchronous multiplier specifically
designed for applications utilizing Broadcom PHYs and Switches.
This high performance device is optimized for Ethernet / SONET /
PDH frequency translation and clock jitter attenuation. The device
contains two internal frequency multiplication stages that are
cascaded in series. The first stage is a low bandwidth PLL that is
optimized to provide reference clock jitter attenuation. The second
stage is a FemtoClock® frequency multiplier that provides the low
jitter, high frequency Ethernet output clock that easily meets Gigabit
and 10 Gigabit Ethernet jitter requirements. Pre-divider and output
divider multiplication ratios are selected using device selection
control pins. The multiplication ratios are optimized to support most
common clock rates used in Ethernet, SONET, PDH applications.
IDT8V89308I requires the use of an external, inexpensive
fundamental mode crystal and uses external passive loop filter
components which allows configuration of the PLL loop bandwidth
and damping characteristics. The device is packaged in a
space-saving 32-VFQFN package and supports industrial
temperature range.
•
Two LVPECL output pairs
Each output supports independent frequency selection at 25MHz,
125MHz and 156.25MHz
•
One differential input supports the following input types: LVPECL,
LVDS
•
•
Accepts input frequencies 8kHz, 25MHz,125MHz and 155.52MHz
•
FemtoClock frequency multiplier provides low jitter, high
frequency output
•
•
•
Absolute pull range: 50ppm
•
RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.223ps (typical), 0.30ps (maximum)
•
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.223ps (typical), 0.30ps (maximum)
•
•
•
3.3V supply voltage
First stage PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
FemtoClock VCO frequency: 625MHz
RMS phase jitter @ 25MHz, using a 25MHz crystal
(12kHz – 5MHz): 0.238ps (typical), 0.30ps (maximum)
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
VCC
nc
nc
XTAL_OUT
VCCX
XTAL_IN
Pin Assignment
32 31 30 29 28 27 26 25
LF1
1
24
VEE
LF0
2
23
nQB
ISET
3
22
QB
VEE
4
21
V CCO
nc
5
20
nQA
VCC
6
19
QA
RESERVED
7
18
VEE
17
ODASEL _0
9
10 11 12 13 14 15 16
VCC
8
VCCA
VEE
IDT8V89308I
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
NL Package
Top View
IDT8V89308ANLGI REVISION A JUNE 18, 2012
1
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JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
XTAL_IN
LF1
LF0
ISET
Loop
Filter
XTAL_OUT
Block Diagram
25MHz
PDSEL_[2:0]
Output Divider
Pullup
00 = 25 (default)
01 = 5
10 = 4
Input
Pre-Divider
CLK1
nCLK1
000 = 1
100 = 3125
110 = 15625
111 = 19440
Phase
Detector
2
XTAL
Oscillator
Charge
Pump
Feedback Divider
÷ 3125
Jitter Attenuation PLL
FemtoClock PLL
625MHz
Output Divider
00 = 25 (default)
01 = 5
10 = 4
2
IDT8V89308ANLGI REVISION A JUNE 18, 2012
2
Pulldown
Pulldown
QA
nQA
ODASEL_[1:0]
QB
nQB
ODBSEL_[1:0]
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JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
LF1, LF0
Analog
Input/Output
3
ISET
Analog
Input/Output
4, 8, 18, 24
VEE
Power
Negative supply pins.
6, 12, 27
VCC
Power
Core supply pins.
7
RESERVED
Reserved
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Input
13
VCCA
Power
14,
15
ODBSEL_1,
ODBSEL_0
Input
Pulldown
Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
16,
17
ODASEL_1,
ODASEL_0
Input
Pulldown
Frequency select pins for Bank A output. See Table 3B.
LVCMOS/LVTTL interface levels.
19, 20
QA, nQA
Output
Differential Bank A clock outputs. LVPECL interface levels.
21
VCCO
Power
Output supply pin.
22, 23
QB, nQB
Output
Differential Bank B clock outputs. LVPECL interface levels.
25
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
Pulldown
Non-inverting differential clock input.
26
CLK1
Input
30,
31
XTAL_OUT,
XTAL_IN
Input
32
VCCX
Power
5, 28, 29
nc
Unused
Loop filter connection node pins. LF0 is the output. LF1 is the input.
Charge pump current setting pin.
Reserved pin. Do not connect.
Pullup
Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A.
Analog supply pin.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Power supply pin for charge pump.
No connect.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
IDT8V89308ANLGI REVISION A JUNE 18, 2012
Test Conditions
3
Minimum
Typical
Maximum
Units
©2012 Integrated Device Technology, Inc.
JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Function Tables
Table 3A. Pre-Divider Selection Function Table
Table 3B. Output Divider Function Table
Inputs
Inputs
PDSEL_2
PDSEL_1
PDSEL_0
Pre-Divider Value
ODxSEL_1
ODxSEL_0
Output Divider Value
0
0
0
1
0
0
25 (default)
1
0
0
3125
0
1
5
1
1
0
15625
1
0
4
1
1
1
19440 (default)
Table 3C. Frequency Function Table
Input
Frequency
(MHz)
Pre-Divider
Value
Crystal
Frequency
(MHz)
FemtoClock
Feedback
Divider Value
FemtoClock VCO
Frequency (MHz)
Output Divider
Value
Output Frequency
(MHz)
0.008
1
25
25
625
25
25
0.008
1
25
25
625
5
125
0.008
1
25
25
625
4
156.25
25
3125
25
25
625
25
25
25
3125
25
25
625
5
125
25
3125
25
25
625
4
156.25
125
15625
25
25
625
25
25
125
15625
25
25
625
5
125
125
15625
25
25
625
4
156.25
155.52
19440
25
25
625
25
25
155.52
19440
25
25
625
5
125
155.52
19440
25
25
625
4
156.25
IDT8V89308ANLGI REVISION A JUNE 18, 2012
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JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
3.63V
Inputs, VI
XTAL_IN
Other Inputs
0V to VCC
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
33.1C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
VCC – 0.20
3.3
VCC
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
VCCX
Charge Pump Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
200
mA
ICCA
Analog Supply Current
20
mA
Maximum
Units
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input
High Current
IIL
Input
Low Current
Test Conditions
Minimum
Typical
ODASEL_[1:0],
ODBSEL_[1:0]
VCC = VIN = 3.465V
150
µA
PDSEL_[2:0]
VCC = VIN = 3.465V
10
µA
ODASEL_[1:0],
ODBSEL_[1:0]
VCC = 3.465V, VIN = 0V
-10
µA
PDSEL_[2:0]
VCC = 3.465, VIN = 0V
-150
µA
IDT8V89308ANLGI REVISION A JUNE 18, 2012
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JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Table 4C. Differential DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
VCMR
Common Mode Input Voltage; NOTE 1
VEE
VCC – 0.85
V
CLK1, nCLK1
Minimum
Typical
VCC = VIN = 3.465V
Maximum
Units
150
µA
CLK1
VCC = 3.465V, VIN = 0V
-10
µA
nCLK1
VCC = 3.465V, VIN = 0V
-150
µA
Common mode voltage is defined as the crossing point.
Table 4D. LVPECL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Minimum
Typical
Maximum
Units
VCCO – 1.10
VCCO – 0.75
V
VCCO – 2.0
VCCO – 1.6
V
0.6
1.0
V
NOTE 1: Outputs terminated with 50 to VCCO – 2V. See Parameter Measurement Information section, 3.3V Output Load Test Circuit.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
fIN
Input Frequency
Test Conditions
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter, (Random),
NOTE 1
fOUT = 25MHz, 25MHz crystal,
Integration Range: 12kHz – 5MHz
tjit(Ø)
RMS Phase Jitter, (Random),
NOTE 1
tjit(Ø)
RMS Phase Jitter, (Random),
NOTE 1
tjit(pk-pk)
Peak-to-Peak Jitter
tsk(o)
Output Skew; NOTE 2, 3
t R / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
XO & FemtoClock PLL Lock
Time; NOTE 4
Minimum
Maximum
Units
0.008
Typical
155.52
MHz
25
156.25
MHz
0.238
0.3
ps
fOUT = 125MHz, 25MHz crystal,
Integration Range: 12kHz – 20MHz
0.223
0.3
ps
fOUT = 156.25MHz, 25MHz crystal,
Integration Range: 12kHz – 20MHz
0.223
0.3
ps
25
ps
25
ps
140
400
ps
48
52
%
1e-12 BER
20% to 80%
6
S
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized using input frequency of 8kHz, QA/nQA and QB/nQB at the same frequency using 3rd order loop filter of 10Hz
bandwidth. Refer to application schematics.
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Lock Time measured from power-up to stable output frequency.
IDT8V89308ANLGI REVISION A JUNE 18, 2012
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IDT8V89308I Data Sheet
Noise Power dBc
Hz
Typical Phase Noise (25MHz)
Offset Frequency (Hz)
Noise Power dBc
Hz
Typical Phase Noise (125MHz)
Offset Frequency (Hz)
IDT8V89308ANLGI REVISION A JUNE 18, 2012
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IDT8V89308I Data Sheet
Noise Power dBc
Hz
Typical Phase Noise (156.25MHz)
Offset Frequency (Hz)
IDT8V89308ANLGI REVISION A JUNE 18, 2012
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IDT8V89308I Data Sheet
Parameter Measurement Information
2V
2V
2V
VCC,
VCCO
VCC
SCOPE
VCCX
nCLK[0:1]
Qx
VCCA
V
Cross Points
PP
CLK[0:1]
V
nQx
CMR
VEE
VEE
-1.3V±0.165V
Differential Input Level
3.3V LVPECL Output Load AC Test Circuit
Phase Noise Plot
Noise Power
nQx
Qx
nQy
Qy
tsk(o)
Offset Frequency
f1
f2
RMS Phase Jitter =
1
* Area Under Curve Defined by the Offset Frequency Markers
2* *ƒ
Output Skew
RMS Phase Jitter
nQA, nQB
nQA, nQB
80%
QA, QB
80%
t PW
VSW I N G
QA, QB
t
20%
20%
tR
tF
odc =
PERIOD
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
IDT8V89308ANLGI REVISION A JUNE 18, 2012
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JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Parameter Measurement Information, continued
XO & FemtoClock PLL Lock Time
IDT8V89308ANLGI REVISION A JUNE 18, 2012
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JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
IDT8V89308ANLGI REVISION A JUNE 18, 2012
11
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JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 2A to 2C show interface examples for the CLK
/nCLK input with built-in 50 terminations driven by the most
common driver types. The input interfaces suggested here are
examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125Ω
Zo = 50Ω
CLK
R4
125Ω
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVPECL
R1
50Ω
Zo = 50Ω
R2
50Ω
nCLK
LVPECL
R1
84Ω
R2
84Ω
Differential
Input
R2
50Ω
Figure 2A. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
Zo = 50Ω
CLK
R1
100Ω
Zo = 50Ω
LVDS
nCLK
Receiver
Figure 2C. CLK/nCLK Input Driven by a 3.3V LVDS Driver
IDT8V89308ANLGI REVISION A JUNE 18, 2012
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JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125Ω
3.3V
3.3V
Zo = 50Ω
3.3V
R4
125Ω
3.3V
3.3V
+
Zo = 50Ω
+
_
LVPECL
Input
Zo = 50Ω
R1
50Ω
_
LVPECL
R2
50Ω
R1
84Ω
VCC - 2V
RTT =
1
* Zo
((VOH + VOL) / (VCC – 2)) – 2
R2
84Ω
RTT
Figure 3A. 3.3V LVPECL Output Termination
IDT8V89308ANLGI REVISION A JUNE 18, 2012
Input
Zo = 50Ω
Figure 3B. 3.3V LVPECL Output Termination
13
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IDT8V89308I Data Sheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
IDT8V89308ANLGI REVISION A JUNE 18, 2012
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IDT8V89308I Data Sheet
Table 6. Crystal Characteristics
Symbol
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
fN
Frequency
25
fT
Frequency Tolerance
±20
±30
ppm
fS
Frequency Stability
±20
±30
ppm
Operating Temperature Range
-40
MHz
85
0
12
pF
C
CL
Load Capacitance
10
CO
Shunt Capacitance
4
CO / C1
Pullability Ratio
FL_3OVT
3rd Overtone FL
200
ppm
3rd Overtone FL Spurs
200
ppm
FL_3OVT_spur
s
ESR
220
Equivalent Series Resistance
pF
240
50
Drive Level
Aging @ 25 0C
1
mW
±3 per year
ppm
Application Schematic Example
Figure 5 (next page) shows an example of IDT8V89308I application
schematic. In this example, the device is operated at VCC = VCCX =
VCCA = VCCO = 3.3V. A 3-pole filter is used for additional spur
reduction. As with any high speed analog circuitry, the power supply
pins are vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The 8V89308I
provides separate power supplies to isolate any high switching noise
from coupling into the internal PLL.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB.
IDT8V89308ANLGI REVISION A JUNE 18, 2012
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set.
15
©2012 Integrated Device Technology, Inc.
JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Logic Control Input Examples
V CC
V CC
R1
125
Set Logic
Input to
'1'
RU1
1K
R2
125
Set Logic
Input to
'0'
VCC
RU2
N ot Install
To Logic
Input
pins
Zo = 50
CLK
To Logic
Input
pins
RD1
N ot I nst al l
RD2
1K
nC LK
Zo = 50
LV PEC L Driver
R3
84
R4
84
3. 3V
FB1
XTAL_OU T
C2
25MHz
C1
TUNE
3.3V
m uR ata, B LM18BB221SN 1
C4
C3
10uF
1uF
R5
133
1uF
X1, 10pF
R6
133
Zo = 50 Ohm
+
XTA L_I N
C5
TUNE
V CC
muRat a, BLM18BB 221SN 1
C7
V CC X
C9
10u
C10
0. 1u
C6
0. 1uF
U1
Loop Filter
R 10
LF 0
Cs
1uF
1
2
3
4
5
6
7
8
LF1
2.2M
Rs
400k
Cp
2.2nF
VC CO
C11
3.3nF
LF 1
LF 0
IS ET
VEE
NC
VCC
RE SER VED
VEE
V EE
nQB
QB
VCCO
nQA
QA
V EE
ODA SEL_0
R7
82.5
0.1u
C8
1uF
32
31
30
29
28
27
26
25
10
FB2
V CC X
XTAL_I N
XT AL_OU T
NC
NC
V CC
C LK 1
nCLK 1
R9
Zo = 50 Ohm
3. 3V
R8
82. 5
LVPECL
Termination
VCC = VCCO= 3.3V
24
23
22
21
20
19
18
17
nQB
QB
nQA
QA
Zo = 50 Ohm
+
OD ASE L_0
Zo = 50 Ohm
P DS EL_2
PD SEL_1
PD SE L_0
VC C
VC CA
OD BSE L_1
ODB SEL_0
OD ASE L_1
C12
0. 1u
P D SEL_2
PD SEL_1
P DS EL_0
F B3
muR at a, BLM18BB 221SN1
C14
C 13
0. 1uF
10uF
OD BS EL_1
OD BSEL_0
OD AS EL_1
3. 3V
R 12
50
9
10
11
12
13
14
15
16
R11
10K
3. 3V
LVPECL
Optional
Y-Termination
VC C A
F B4
R 14
50
VC C
V CC
muRat a, BLM18BB221SN1
C 17
0. 1uF
R 15
10
R13
50
C18
10uF
C19
0. 1u
C 15
0. 1u
C 16
10u
Figure 5. IDT8V89308I Application Schematic
IDT8V89308ANLGI REVISION A JUNE 18, 2012
16
©2012 Integrated Device Technology, Inc.
JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8V89308I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the IDT8V89308I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 200mA = 693mW
•
Power (outputs)MAX = 31.55mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 31.55mW = 63.1mW
Total Power_MAX (3.465V, with all outputs switching) = 693mW + 63.1mW = 756.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.756W * 33.1°C/W = 110°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT8V89308ANLGI REVISION A JUNE 18, 2012
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
17
©2012 Integrated Device Technology, Inc.
JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.75V
(VCCO_MAX – VOH_MAX) = 0.75V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.6V
(VCCO_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.75V)/50] * 0.75V = 18.75mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.80mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW
IDT8V89308ANLGI REVISION A JUNE 18, 2012
18
©2012 Integrated Device Technology, Inc.
JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
Transistor Count
The transistor count for IDT8V89308I is: 22,280
IDT8V89308ANLGI REVISION A JUNE 18, 2012
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©2012 Integrated Device Technology, Inc.
JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
32 Lead VFQFN Package Outline and Package Dimensions
IDT8V89308ANLGI REVISION A JUNE 18, 2012
20
©2012 Integrated Device Technology, Inc.
JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
8V89308ANLGI
8V89308ANLGI8
Marking
IDT8V89308ANLGI
IDT8V89308ANLGI
Package
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
Shipping Packaging
Tray
2500 Tape & Reel
Temperature
-40C to 85C
-40C to 85C
NOTE: Parts that are ordered with an "G" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
IDT8V89308ANLGI REVISION A JUNE 18, 2012
21
©2012 Integrated Device Technology, Inc.
JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
Revision History Sheet
Rev
A
Table
Page
21
Description of Change
Date
Deleted page 21, “Option 2 of NL/NLG32 package outline.” Only Option 1 is
applicable to this device.
IDT8V89308ANLGI REVISION A JUNE 18, 2012
22
6/18/2012
©2012 Integrated Device Technology, Inc.
JITTER ATTENUATOR & FEMTOCLOCK® MULTIPLIER
IDT8V89308I Data Sheet
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