Clock Generator for Cavium
Processors
8V41N012A
Datasheet
Description
Features
The 8V41N012A is a PLL-based clock generator specifically
designed for Cavium Networks Octeon II processors. This
high-performance device is optimized to generate the processor
core reference clock, the PCI-Express, sRIO, XAUI, SerDes
reference clocks, and the clocks for both the Gigabit Ethernet
MAC and PHY. The output frequencies are generated from a
25MHz external input source or an external 25MHz parallel
resonant crystal.
▪ Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for PCI Express, sRIO, and GbE, HCSL interface levels
▪ One single-ended QG LVCMOS/LVTTL clock output at 125MHz
▪ One single-ended QF LVCMOS/LVTTL clock output at 50MHz
▪ Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz
▪ Selectable external crystal or differential (single-ended)
input source
▪ Crystal oscillator interface designed for 25MHz, parallel
resonant crystal
▪ Differential CLK, nCLK input pair that can accept: LVPECL,
LVDS, LVHSTL, and HCSL input levels
▪ Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
▪ Supply Modes, (125MHz QG output and 25MHz QREFx
outputs):
The industrial temperature range of the 8V41N012A supports
telecommunication, networking, and storage requirements.
• Core / Output
• 3.3V / 3.3V
• 3.3V / 2.5V
▪ Supply Modes, (HCSL outputs, and 50MHz QF output):
• Core / Output
• 3.3V / 3.3V
▪ -40°C to 85°C ambient operating temperature
▪ 10 x 10 mm 72-VFQFPN, lead-free (RoHS 6) packaging
©2019 Integrated Device Technology, Inc
1
October 11, 2019
8V41N012A Datasheet
Block Diagram
nMR
Pulldown
Pullup
OE_A
QA0
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
nQA0
QA1
Pullup
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
FSEL_D[1:0]
FSEL_E[1:0]
Pulldown
2
Pulldown
2
Pulldown
2
Pulldown
2
Pulldown
2
nQA1
OE_B
QB0
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
Clock
Output
Control
Logic
nQB0
QB1
nQB1
Pullup
OE_C
QC0
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
nQC0
QC1
nQC1
Pullup
PLL_SEL
REF_SEL
OE_D
QD0
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
Pullup
Pullup
nQD0
QD1
nQD1
Pullup
OE_E
XTAL_IN
1
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
0
50MHz
OSC
1
XTAL_OUT
CLK
nCLK
FemtoClock NG
VCO
Pulldown
QE0
nQE0
QE1
nQE1
0
PU/PD
QF
Pullup
OE_G
I_REF
125MHz
QG
Pullup
OE_REF
QREF0
QREF1
©2019 Integrated Device Technology, Inc
2
October 11, 2019
8V41N012A Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Function Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Phase Noise at 156.25MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Wiring the Differential Input to Accept Single-Ended Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Differential Clock Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overdriving the XTAL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Recommended Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VFQFPN EPAD Thermal Release Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Recommendations for Unused Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PCI Express Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Schematic Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reliability Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
©2019 Integrated Device Technology, Inc
3
October 11, 2019
8V41N012A Datasheet
VDDO_QE
IREF
OE_D
GND
nQD1
QD1
nQD0
QD0
VDDO_QD
VDD
OE_C
GND
nQC1
QC1
nQC0
QC0
VDDO_QC
OE_B
Pin Assignments
QE0
nQE0
QE1
nQE1
GND
OE_E
FSEL_C0
FSEL_C1
GND
VDDA
FSEL_D0
FSEL_D1
VDD
nMR
8V41N012A
GND
nQB1
QB1
nQB0
QB0
VDDO_QB
OE_A
GND
nQA1
QA1
nQA0
QA0
VDDO_QA
GND
VDD
GND
QF
VDDO_QF
OE_REF
VDDO_QREF
QREF0
QREF1
GND
FSEL_E0
FSEL_E1
REF_SEL
VDD
XTAL_IN
XTAL_OUT
PLL_SEL
FSEL_A0
FSEL_A1
CLK
n CLK
FSEL_B0
FSEL_B1
VDDO_QG
QG
GND
OE_G
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
55
36
56
35
57
34
58
33
59
32
60
31
61
30
62
29
63
28
64
27
65
26
66
25
67
24
68
23
69
22
70
21
71
20
72
19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
10 x 10 mm 72-VFQFPN
Note: Exposed pad must always be connected to GND.
Note: Pin 1 is located at bottom left corner as shown.
Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Type
1
OE_REF
Input
2
VDDO_QREF
Power
QREF0, QREF1 output supply pin (LVCMOS/LVTTL). 3.3V or 2.5V supply.
3,
4
QREF0,
QREF1
Output
Single-ended REF outputs. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
5, 21, 23,
29, 36, 43,
51, 59, 63,
71
GND
Power
Power supply ground.
6,
7
FSEL_E0
FSEL_E1
Input
©2019 Integrated Device Technology, Inc
Description
Pullup
Pulldown
Active HIGH output enable for QREF0 and QREF1 outputs. LVCMOS/LVTTL
interface levels.
0 = QREF0, QREF1 outputs disabled/high impedance
1 = QREF0, QREF1 outputs enabled (default)
Selects the QEx, nQEx output frequency. LVCMOS/LVTTL interface levels.
00 = 100MHz (default)
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
4
October 11, 2019
8V41N012A Datasheet
Table 1. Pin Descriptions (Continued)
Number
Name
Type
Description
8
REF_SEL
Input
9, 22, 45,
67
VDD
Power
Core supply pins.
10,
11
XTAL_IN
XTAL_OUT
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
12
PLL_SEL
Input
Pullup
13,
14
FSEL_A0
FSEL_A1
Input
Pulldown
Selects the QAx, nQAx output frequency. LVCMOS/LVTTL interface levels.
00 = 100MHz (default)
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
15
CLK
Input
Pulldown
Non-inverting differential clock input.
16
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VDD/2.
17,
18
FSEL_B0
FSEL_B1
Input
Pulldown
Selects the QBx, nQBx output frequency. LVCMOS/LVTTL interface levels.
00 = 100MHz (default)
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
19
VDDO_QF
Power
QF output supply pin (LVCMOS/LVTTL). 3.3V supply.
20
QF
Output
Single-ended output. 3.3V LVCMOS/LVTTL interface levels.
24
VDDO_QA
Power
Bank A (HCSL) output supply pin. 3.3 V supply.
25, 26
QA0, nQA0
Output
Bank A differential output pair. HCSL interface levels.
27, 28
QA1, nQA1
Output
Bank A differential output pair. HCSL interface levels.
30
OE_A
Input
31
VDDO_QB
Power
Pullup
Pullup
Input source control pin. LVCMOS/LVTTL interface levels.
0 = CLK, nCLK
1 = XTAL (default)
PLL bypass control pin. LVCMOS/LVTTL interface levels.
0 = Bypass mode
1 = PLL mode (default)
Active HIGH output enable for Bank A outputs. LVCMOS/LVTTL interface levels.
0 = Bank A outputs disabled/high impedance
1 = Bank A outputs enabled (default)
Bank B (HCSL) output supply pin. 3.3V supply.
Continued on next page
32, 33
QB0, nQB0
Output
Bank B differential output pair. HCSL interface levels.
34, 35
QB1, nQB1
Output
Bank B differential output pair. HCSL interface levels.
37
OE_B
Input
38
VDDO_QC
Power
©2019 Integrated Device Technology, Inc
Pullup
Active HIGH output enable for Bank B outputs. LVCMOS/LVTTL interface levels.
0 = Bank B outputs disabled/high impedance
1 = Bank B outputs enabled (default)
Bank C (HCSL) output supply pin. 3.3V supply.
5
October 11, 2019
8V41N012A Datasheet
Table 1. Pin Descriptions (Continued)
Number
Name
Type
39, 40
QC0, nQC0
Output
Bank C differential output pair. HCSL interface levels.
41, 42
QC1, nQC1
Output
Bank C differential output pair. HCSL interface levels.
44
OE_C
Input
46
VDDO_QD
Power
Bank D (HCSL) output supply pin. 3.3V supply.
47, 48
QD0, nQD0
Output
Bank D differential output pair. HCSL interface levels.
49, 50
QD1, nQD1
Output
Bank D differential output pair. HCSL interface levels.
52
OE_D
Input
53
IREF
Input
External fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode.
54
VDDO_QE
Power
Bank E (HCSL) output supply pin. 3.3V supply.
55, 56
QE0, nQE0
Output
Bank E differential output pair. HCSL interface levels.
57, 58
QE1, nQE1
Output
Bank E differential output pair. HCSL interface levels.
60
OE_E
Input
Pullup
61,
62
FSEL_C0
FSEL_C1
Input
Pulldown
64
VDDA
Power
65,
66
FSEL_D0
FSEL_D1
Input
Pulldown
Selects the QDx, nQDx output frequency. LVCMOS/LVTTL interface levels.
00 = 100MHz (default)
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
68
nMR
Input
Pulldown
Active LOW Master Reset. LVCMOS/LVTTL interface levels.
0 = Reset. The internal dividers are reset causing the true outputs Qx to go low
and the inverted outputs nQx to go high. (default)
1 = Active. The internal dividers and the outputs are active.
69
VDDO_QG
Power
©2019 Integrated Device Technology, Inc
Description
Pullup
Pullup
Active HIGH output enable for Bank C outputs. LVCMOS/LVTTL interface levels.
0 = Bank C outputs disabled/high impedance
1 = Bank C outputs enabled (default)
Active HIGH output enable for Bank D outputs. LVCMOS/LVTTL interface levels.
0 = Bank D outputs disabled/high impedance
1 = Bank D outputs active (default)
Active HIGH output enable for Bank E outputs. LVCMOS/LVTTL interface levels.
0 = Bank E outputs disabled/high impedance
1 = Bank E outputs enabled (default)
Selects the QCx, nQCx output frequency. LVCMOS/LVTTL interface levels.
00 = 100MHz (default)
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
Analog supply pin.
QG output supply pins (LVCMOS/LVTTL). 3.3V or 2.5V supply.
6
October 11, 2019
8V41N012A Datasheet
Table 1. Pin Descriptions (Continued)
Number
Name
Type
70
QG
Output
72
OE_G
Input
Description
Bank G single-ended output. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
Pullup
EPAD
Active HIGH output enable for Bank G output. LVCMOS/LVTTL interface levels.
0 = Bank G outputs disabled/high impedance
1 = Bank G outputs enabled (default)
Connect to GND.
Pin Characteristics
Table 2. Pin Characteristics[a]
Symbol
Parameter
Input
Capacitance
CIN
Test Conditions
Minimum
Typical
Maximum
Units
CLK, nCLK
2.5
pF
Control Pins
6
pF
RPULLUP
Input Pullup Resistor
50
k
RPULLDOWN
Input Pulldown Resistor
50
k
ROUT
Output
Impedance
QF, QG,
QREF[1:0]
VDDO_QF = VDDO_QG = VDDO_QREF
= 3.465V
15
W
QG,
QREF[1:0]
VDDO_QREF, VDDO_QG = 2.625V
19
W
[a] Pullup and Pulldown refer to internal input resistors. For typical values, see Table 2.
Function Tables
Table 3. FSEL_X Control Input Function Table[a][b]
Input
Output Frequency
FSEL_X[1:0]
Q[Ax:Ex], nQ[Ax:Ex]
00 (default)
100MHz
01
125MHz
10
156.25MHz
11
312.50MHz
[a] FSEL_X denotes FSEL_A, _B, _C, _D, _E.
[b] Any two outputs operated at the same frequency will be synchronous.
©2019 Integrated Device Technology, Inc
7
October 11, 2019
8V41N012A Datasheet
Table 4. PLL_SEL Control Input Function Table
Input
PLL_SEL
Operation
0
PLL Bypass
1 (default)
PLL Mode
Table 5. REF_SEL Control Input Function Table
Input
REF_SEL
Clock Source
0
CLK, nCLK
1 (default)
XTAL_IN, XTAL_OUT
Table 6. OE_[A:E] Control Input Function Table
Input
Outputs
OE_[A:E]
Q[Ax:Ex], nQ[Ax:Ex]
0
High-Impedance
1 (default)
Enabled
Table 7. OE_G Control Input Function Table
Input
Outputs
OE_G
QG
0
High-Impedance
1 (default)
Enabled
Table 8. OE_REF Control Input Function Table
Input
Output
OE_REF
QREF[1:0]
0
High-Impedance
1 (default)
Enabled
©2019 Integrated Device Technology, Inc
8
October 11, 2019
8V41N012A Datasheet
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Table 9. Absolute Maximum Ratings
Item
Rating
Supply Voltage, V DD
3.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to 2V
-0.5V to V DD + 0.5V
Outputs, VO
-0.5V to V DDO_QX + 0.5V
Package Thermal Impedance, JA
26.6°C/W (0 mps)
Storage Temperature, T STG
-65C to 150C
DC Electrical Characteristics
Table 10. Power Supply DC Characteristics (VDD = 3.3V ±5%, VDDO_Q[A:E] = VDDO_Q[F:G] = VDDO_QREF =
3.3V ±5%, TA = -40°C to 85°C)[a]
Symbol
[b]
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
VDD - 0.81
3.3
VDD
V
VDDO_QX
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
193
235
mA
IDDA
Analog Supply Current
36
45
mA
IDDO_QX
Output Supply Current
24
30
mA
No Load
[a] VDDO_QX denotes VDDO_Q[A:E], VDDO_Q[F:G], VDDO_QREF.
[b] IDDO_QX denotes I DDO_Q[A:E] + IDDO_Q[F:G] + IDDO_QREF.
Table 11. Power Supply DC Characteristics (VDD = VDDO_Q[A:E] = VDDO_QF = 3.3V ±5%,
VDDO_QG = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C)
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
2.6
3.3
VDD
V
VDDO_QG/
VDDO_QREF
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
193
235
mA
IDDA
Analog Supply Current
36
45
mA
IDDO_QG +
Output Supply Current
8
15
mA
No Load
IDDO_QREF
©2019 Integrated Device Technology, Inc
9
October 11, 2019
8V41N012A Datasheet
Table 12. LVCMOS/LVTTL DC Characteristics (VDD = VDDO_Q[A:E] = VDDO_QF = 3.3V ± 5%; VDDO_QG =
VDDO_QREF = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C)
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VIH
Input High Voltage
2.2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input
High
Current
Input
Low
Current
IIL
VOH
VOL
nMR, FSEL_A[1:0],
FSEL_B[1:0], FSEL_C[1:0],
FSEL_D[1:0], FSEL_E[1:0]
VDD = VIN = 3.465V
150
µA
REF_SEL, PLL_SEL,
OE_REF, OE_A, OE_B,
OE_C, OE_D, OE_E, OE_G
VDD = VIN = 3.465V
10
uA
nMR, FSEL_A[1:0],
FSEL_B[1:0], FSEL_C[1:0],
FSEL_D[1:0], FSEL_E[1:0]
VDD = 3.465V, VIN = 0V
-10
µA
REF_SEL, PLL_SEL,
OE_REF, OE_A, OE_B,
OE_C, OE_D, OE_E, OE_G
VDD = 3.465V, VIN = 0V
-150
uA
VDDO_QF = VDDO_QG,
VDDO_QREF = 3.465V
2.6
V
VDDO_QG, VDDO_QREF =
2.625V
1.8
V
Output High Voltage
Output Low Voltage
VDDO_QF = VDDO_QG,
VDDO_QREF = 3.465V or
VDDO_QG, VDDO_QREF =
2.625V
0.6
V
Maximum
Units
150
µA
Table 13. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C[a][b]
Symbol
Parameter
Test Conditions
Minimum
VDD = VIN = 3.465V
Typical
IIH
Input High Current
CLK, nCLK
IIL
Input Low Current
CLK
VDD = 3.465V, VIN = 0V
-5
µA
nCLK
VDD = 3.465V, VIN = 0V
-150
µA
VPP
Peak-to-Peak Input Voltage; NOTE 1
0.15
1.3
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.5
VDD – 0.85
V
[a] VIL should not be less than -0.3V.
[b] Common mode voltage is defined as VIH.
©2019 Integrated Device Technology, Inc
10
October 11, 2019
8V41N012A Datasheet
Table 14. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25
Equivalent Series Resistance (ESR)
MHz
50
Load Capacitance (CL)
12
Shunt Capacitance
W
pF
7
pF
Table 15. Input Frequency Characteristics (VDD = VDDO_Q[A:E] = VDDO_QF = 3.3V ± 5%; VDDO_QG =
VDDO_QREF = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C)
Symbol
FIN
Parameter
Input
Frequency
Test Conditions
Minimum
Typical
Maximum
Units
CLK, nCLK
25
MHz
XTAL_IN,
XTAL_OUT
25
MHz
AC Electrical Characteristics
Table 16. PCI Express Jitter Specifications (VDD = VDDO_Q[A:E] = 3.3V ± 5%, TA = -40°C to 85°C)
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
PCIe
Industry
Spec.
Units
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
8.07
13.7
86
ps
tREFCLK_HF_RMS
(PCIe Gen 2)
Phase Jitter
RMS; NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
0.95
2.17
3.10
ps
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter
RMS; NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
0.05
0.10
3.0
ps
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS; NOTE 3, 4
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.24
0.57
0.8
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is
86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting
the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and
3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
©2019 Integrated Device Technology, Inc
11
October 11, 2019
8V41N012A Datasheet
Table 17. HCSL AC Characteristics (VDD = VDDO_Q[A:E] = VDDO_QF = 3.3V ± 5%; VDDO_QG = VDDO_QREF = 3.3V
± 5% or 2.5V ± 5%, TA = -40°C to 85°C)
Symbol
fOUT
Parameter
Output Frequency
Test Conditions
Q[A:E],
nQ[A:E]
Minimum
Typical
Maximum
Units
FSEL_x[1:0] = 00
100
MHz
FSEL_x[1:0] = 01
125
MHz
FSEL_x[1:0] = 10
156.25
MHz
FSEL_x[1:0] = 11
312.5
MHz
VRB
Ring-Back Voltage Margin;
NOTE 1, 2
Q[A:E],
nQ[A:E]
-100
tSTABLE
Time before VRB is allowed;
NOTE 1, 2
Q[A:E],
nQ[A:E]
500
VMAX
Absolute Max Output Voltage;
NOTE 3, 4
Q[A:E],
nQ[A:E]
VMIN
Absolute Min Output Voltage;
NOTE 3, 5
Q[A:E],
nQ[A:E]
-300
VCROSS
Absolute Crossing Voltage;
NOTE 3, 6, 7
Q[A:E],
nQ[A:E]
175
VCROSS
Total Variation of VCROSS over
All Edges; NOTE 3, 6, 8
Q[A:E],
nQ[A:E]
tSLEW+
Rising Edge Rate; NOTE 1, 9
Q[A:E],
nQ[A:E]
tSLEW-
Falling Edge Rate; NOTE 1, 9
odc
tjit(Ø)
100
mV
ps
1150
mV
mV
550
mV
140
mV
0.6
4.0
V/ns
Q[A:E],
nQ[A:E]
0.6
4.0
V/ns
Output Duty Cycle
Q[A:E],
nQ[A:E]
45
50
55
%
RMS Phase Jitter, (Random);
NOTE 10
Q[A:E],
nQ[A:E]
100MHz, Integration
Range:
(12kHz to 20MHz)
0.32
0.45
ps
125MHz, Integration
Range:
(12kHz to 20MHz)
0.31
0.45
ps
156.25MHz, Integration
Range:
(12kHz to 20MHz)
0.30
0.45
ps
312.5MHz, Integration
Range:
(12kHz to 20MHz)
0.29
0.45
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at fOUT and in PLL mode unless noted otherwise.
NOTE 1: Measurement taken from differential waveform.
NOTE 2: tSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV range. See Parameter Measurement Information Section.
NOTE 3: Measurement taken from single-ended waveform.
NOTE 4: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
©2019 Integrated Device Technology, Inc
12
October 11, 2019
8V41N012A Datasheet
NOTE 5: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 6: Measured at the crossing point where the instantaneous voltage value of the rising edge of Q[Ax:Ex] equals the falling edge of
nQ[Ax:Ex].
NOTE 7: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
NOTE 8: Defined as the total variation of all crossing voltages of rising Q[Ax:Ex] and falling nQ[Ax:Ex]. This is the maximum allowed variance in
Vcross for any particular system.
NOTE 9: Measured from -150mV to +150mV on the differential waveform (derived from Q[Ax:Ex] minus nQ[Ax:Ex]). The signal must be
monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 10: Measurements taken with 25MHz XTAL as input source and spur off.
Table 18. LVCMOS AC Characteristics (VDD = VDDO_Q[A:E] = VDDO_QF = 3.3V ± 5%; VDDO_QG = VDDO_QREF =
3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C)
Symbol
fOUT
Parameter
Output Frequency
Test Conditions
Maximum
Units
50
MHz
QG
125
MHz
QREF[1:0]
25
MHz
Output Rise/Fall Time
QF, QG,
QREF[1:0]
odc
Output Duty Cycle
QF, QG,
QREF[1:0]
RMS Phase Jitter,
(Random); NOTE 1
Typical
QF
tr / tf
tjit(Ø)
Minimum
20% to 80%
180
46
760
ps
50
54
%
QF
50MHz, Integration Range:
(12kHz to 20MHz)
0.36
0.48
ps
QG
125MHz, Integration Range:
(12kHz to 20MHz)
0.32
0.43
ps
QREF[1:0]
25MHz, Integration Range:
(12kHz to 5MHz)
0.32
0.40
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at fOUT and in PLL mode unless noted otherwise.
NOTE 1: Measurements taken with 25MHz XTAL as input source and spur off.
©2019 Integrated Device Technology, Inc
13
October 11, 2019
8V41N012A Datasheet
Noise Power (dBc/Hz)
Typical Phase Noise at 156.25MHz
Offset Frequency (Hz)
©2019 Integrated Device Technology, Inc
14
October 11, 2019
8V41N012A Datasheet
Parameter Measurement Information
Figure 1. 3.3V Core/3.3V LVCMOS Output Load Test Circuit
9
9
6&23(
9''
9''2B4>) *@
9''2B45() 9
''$
4[
*1'
9
Figure 2. 3.3V Core/3.3V HCSL Output Load Test Circuit 1
3.3V±5%
3.3V±5%
VDD,
VDDO_Q[A:E]
VDDA
This load condition is used for V MAX, VMIN, VRB, tSTABLE,
VCROSS, VCROSS and tSLEW± measurements.
Figure 3. Differential Input Level
VDD
nCLK
V
PP
Cross Points
V
CMR
CLK
GND
©2019 Integrated Device Technology, Inc
15
October 11, 2019
8V41N012A Datasheet
Figure 4. 3.3V Core/2.5V LVCMOS Output Load Test Circuit
9
9
9
9''
9''2B4*
9''2B45()
SCOPE
Qx
9''$
GND
9
Figure 5. 3.3V Core/3.3V HCSL Output Load Test Circuit 2
3.3V±5%
3.3V±5%
SCOPE
VDD,
VDDO_Q[A:E]
50Ω
VDDA
50Ω
IREF
GND
475Ω
0V
0V
This load condition is used for tjit and odc measurements.
Figure 6. RMS Phase Jitter
©2019 Integrated Device Technology, Inc
16
October 11, 2019
8V41N012A Datasheet
Figure 7. LVCMOS Output Duty Cycle/Pulse Width
QF, QG,
QREF[1:0]
Figure 8. Differential Measurement Points for Rise/Fall Time Edge Rate
Figure 9. Single-ended Measurement Points for Delta Cross Point
Figure 10. LVCMOS Output Rise/Fall Time
80%
QF, QG,
QREF[1:0]
80%
20%
20%
tR
tF
Figure 11. Single-ended Measurement Points for Absolute Cross Point/Swing
©2019 Integrated Device Technology, Inc
17
October 11, 2019
8V41N012A Datasheet
Figure 12. Differential Measurement Points for Ringback
Figure 13. Differential Measurement Points for Duty Cycle/Period
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V 1in the center of the input voltage
swing. For example, if the input clock is driven from a single-ended 2.5V LVCMOS driver and the DC offset (or swing center) of this signal
is 1.25V, the R1 and R2 values should be adjusted to set the V1 at 1.25V. The values below are for when both the single ended swing and
VDD are at the same voltage.
Figure 14. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
©2019 Integrated Device Technology, Inc
18
October 11, 2019
8V41N012A Datasheet
This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First,
R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of
the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise
rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is
recommended that the amplitude be reduced while maintaining an edge rate faster than 1V/ns. The datasheet specifies a lower
differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however
VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be
used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are
characterized and guaranteed by using a differential signal.
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figure 15 to Figure 19 show interface examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 15, the input termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination recommendation.
Figure 15. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver
3.3V
1.8V
Zo = 50
CLK
Zo = 50
nCLK
LVHSTL
IDT
LVHSTL Driver
R1
50
R2
50
Differential
Input
Figure 16. CLK/nCLK Input Driven by a 3.3V LVPECL Driver
Figure 17. CLK/nCLK Input Driven by a 3.3V LVDS Driver
©2019 Integrated Device Technology, Inc
19
October 11, 2019
8V41N012A Datasheet
Figure 18. CLK/nCLK Input Driven by a 3.3V LVPECL Driver
Figure 19. CLK/nCLK Input Driven by a 3.3V HCSL Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
Differential
Input
*R4
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise. Figure 20 shows an example of the interface diagram for a high speed
3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs)
equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be
done in one of two ways.
First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can
also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a
slower and weaker LVCMOS driver. Figure 21 shows an example of the interface diagram for an LVPECL driver. This is a standard
LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be
placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet
specifications are characterized and guaranteed by using a quartz crystal as the input.
Figure 20. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
Zo = Ro + Rs
R2
100
.1uf
LVCMOS Driver
©2019 Integrated Device Technology, Inc
20
October 11, 2019
8V41N012A Datasheet
Figure 21. General Diagram for LVPECL Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
R1
50
LVPECL Driver
R2
50
R3
50
Recommended Termination
Figure 22 is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output types. All traces should be 50Ω impedance single-ended or 100Ω
differential.
Figure 22. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
0.5" Max
Rs
22 to 33 +/-5%
0-0.2"
1-14"
0.5 - 3.5"
L1
L2
L4
L5
L1
L2
L4
L5
PCI Expres s
PCI Expres s
Driver
Connector
0-0.2"
Rt
L3
L3
PCI Expres s
Add-in Card
49.9 +/- 5%
Figure 23 is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will
be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0Ω to 33Ω. All traces should be 50Ω impedance single-ended or 100Ω differential.
©2019 Integrated Device Technology, Inc
21
October 11, 2019
8V41N012A Datasheet
Figure 23. Recommended Termination (where a point-to-point connection can be used)
0.5" Max
L1
L1
Rs
0 to 33
0-18"
0-0.2"
L2
L3
L2
L3
0 to 33
PCI Expres s
Rt
Driver
49.9 +/- 5%
VFQFPN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 24. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed
on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis
and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is
also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug
and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern.
Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 24. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
©2019 Integrated Device Technology, Inc
22
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
October 11, 2019
8V41N012A Datasheet
Recommendations for Unused Input and Output Pins
Inputs
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k
resistor can be used.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
Outputs
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. There should be no trace attached.
Differential Outputs
All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
PCI Express Application Information
PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most
frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is:
Ht s = H3 s H1 s – H2 s
The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is:
Y s = X s H3 s H1 s – H2 s
In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
Figure 25. PCI Express Common Clock Architecture
©2019 Integrated Device Technology, Inc
23
October 11, 2019
8V41N012A Datasheet
For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for
a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak.
Figure 26. PCIe Gen 1 Magnitude of Transfer Function
For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in RMS. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
Figure 27. PCIe Gen 2A Magnitude of Transfer Function
©2019 Integrated Device Technology, Inc
24
October 11, 2019
8V41N012A Datasheet
Figure 28. PCIe Gen 2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function
parameters are different from Gen 1 and the jitter result is reported in RMS.
Figure 29. PCIe Gen 3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference
Clock Requirements.
©2019 Integrated Device Technology, Inc
25
October 11, 2019
8V41N012A Datasheet
Schematic Example
Figure 30 shows an example of 8V41N012A application schematic. In this example, the device is operated at VDD = VDDA = V DDO_Qx =
3.3V. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and
functional tables in the datasheet to ensure that the logic control inputs are properly set.
A 12pF parallel resonant 25MHz crystal is used. For this device, the crystal load capacitors are required for proper operation. The load
capacitance, C1 = C2 = 2pF, are recommended for frequency accuracy. Depending on the variation of the parasitic stray capacity of the
printed circuit board traces between the crystal and the Xtal_In and Xtal_Out pins, the values of C1 and C2 might require a slight
adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used, but this will require
adjusting C1 and C2. When designing the circuit board, return the capacitors to ground though a single point contact close to the
package. Two Fox crystal options are shown in the schematic for design flexibility.
The ePAD provides a low thermal impedance connection between the internal device and the PCB. It also provides an electrical
connection to the die and must be connected to ground.
As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 8V41N012A provides separate power supplies to isolate any high switching noise from coupling
into the internal PLL.
In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the 0.1µF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the PCB.
Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all devices.
©2019 Integrated Device Technology, Inc
26
October 11, 2019
8V41N012A Datasheet
Figure 30. 8V41N012A Schematic Example
3.3V
FB2
2
Place each 0.1uF bypass cap directly adjacent
to its corresponding VDD or VDDA pin.
C11
10uF
1
C10
0.1uF
BLM18BB221SN1
VDD
C14
0.1uF
C21
0.1uF
C15
0.1uF
3.3V
VDD
R5
5
FB1
2
FSEL_A0
FSEL_A1
13
14
FSEL_B0
FSEL_B1
17
18
FSEL_C0
FSEL_C1
61
62
FSEL_D0
FSEL_D1
65
66
FSEL_E0
FSEL_E1
6
7
67
VDDA
VDDO_QA
VDDO_QB
FSEL_B0
FSEL_B1
FSEL_C0
FSEL_C1
VDDO_QC
VDDO_QD
VDDO_QE
FSEL_D0
FSEL_D1
FSEL_E0
FSEL_E1
VDDO_QF
VDDO_QG
VDDO_QREF
FOX
603-25-173crystal
crystal
IDT 603-25-173
8
12
68
OE_A
OE_B
OE_C
OE_D
OE_E
OE_G
OE_REF
30
37
44
52
60
72
1
4
3
10
XTAL_OUT
11
QA0
nQA0
QA1
nQA1
XTAL_IN
QB1
nQB1
QC0
nQC0
XTAL_OUT
C2
2pF
QC1
nQC1
QD0
nQD0
Zo = 50 Ohm
15
CLK
CLK
QD1
nQD1
Zo = 50 Ohm
16
nCLK
R1
50
+3.3V PECL Driver
QE0
nQE0
nCLK
QE1
nQE1
R2
50
QF
VDD
Set Logic
Input to '1'
RU1
1k
VDD
Set Logic
Input to '0'
46
C4
0.1uF
54
C5
0.1uF
19
C6
0.1uF
69
C7
0.1uF
C8
0.1uF
2
QREF0
QREF1
25
26
QA0
nQA0
27
28
QA1
nQA1
32
33
QB0
nQB0
34
35
QB1
nQB1
C20
0.1uF
R7
R6
39
40
QC0
nQC0
41
42
QC1
nQC1
47
48
QD0
nQD0
49
50
QD1
nQD1
55
56
QE0
nQE0
57
58
QE1
nQE1
20
QF
70
QG
3
QREF0
4
QREF1
0" to 18"
Zo = 50
33
+
33
Zo = 50
-
Optional
HCSL_Receiver
R12
50
R13
33
1" to 14"
Zo = 50
0.5" to 3.5"
Zo = 50
+
33
Zo = 50
R11
50
R9
50
PCI Express
Point-to-Point
Connection
HCSL Termination
R10
ePAD
Logic Control Input Examples
C3
0.1uF
Zo = 50
R8
50
HCSL_Receiver
PCI Express Add-In Card
R14
Zo = 50
33
73
R4
475
IREF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R3
50
QG
5
21
23
29
36
43
51
59
63
71
53
C16
0.1uF
38
Place each 0.1uF bypass cap directly
adjacent to the corresponding VDDO pin.
OE_A
OE_B
OE_C
OE_D
OE_E
OE_G
OE_REF
QB0
nQB0
25 MHz
(12pF)
C18
0.1uF
31
C19
0.1uF
X1
2
C17
10uF
10uF
24
REF_SEL
PLL_SEL
nMR
XTAL_IN
1
C1
2pF
REF_SEL
PLL_SEL
nMR
C13
0.1uF
1
BLM18BB221SN1
C9
64
VDD
45
22
FSEL_A0
FSEL_A1
VDD
U1
VDD
C12
0.1uF
VDD
9
VDDA
CMOS Source Termination
LVCMOS Receiver
RU2
Not Install
R15
RD1
Not Install
Zo = 50
To Logic
Input
pins
To Logic
Input
pins
33
RD2
1k
LVCMOS Receiver
©2019 Integrated Device Technology, Inc
27
October 11, 2019
8V41N012A Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 8V41N012A. Equations and example calculations
are also provided.
1. Power Dissipation.
The total power dissipation for the 8V41N012A is the sum of the core power plus the analog power plus the power dissipated due to
loading.
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
▪ Power (core)MAX = VDD_MAX * (IDD + IDDA)= 3.465V * (235mA + 45mA) = 970.2mW
▪ Power (HCSL)MAX = (3.465V – 17mA * 50) 17mA = 44.5mW per output
▪ Total Power (HCSL)MAX = 44.5mW * 10 = 445mW
LVCMOS Driver Power Dissipation
▪ Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO_Qx / 2
Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.65mA
▪ Power Dissipation on the ROUT per LVCMOS output
Power (LVCMOS) = ROUT * (IOUT)2 = 15 * (26.65mA)2 = 10.65mW per output
▪ Total Power Dissipation on the ROUT
Total Power (ROUT) = 10.65mW * 4 = 42.6mW
▪ Total Power Dissipation
▪ Total Power
= Power (core) + Total Power (HCSL) + Total Power (ROUT)
= 970.2mW + 445mW + 42.6mW
= 1457.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that
the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 26.6°C/W per Table 19.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.458W * 26.6°C/W = 123.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the
type of board (multi-layer).
©2019 Integrated Device Technology, Inc
28
October 11, 2019
8V41N012A Datasheet
Table 19. Thermal Resistance JA for 72 Lead VFQFPN, Forced Convection
JA vs. Air Flow
0
1
2
26.6°C/W
20°C/W
17.9°C/W
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 31.
Figure 31. HCSL Driver Circuit and Termination
VDDO
IOUT = 17mA
➤
VOUT
RREF =
475
± 1%
RL
50
IC
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when VDD_MAX.
Power= (VDD_MAX – VOUT) * IOUT
since VOUT = IOUT * RL
Power= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44.5mW
©2019 Integrated Device Technology, Inc
29
October 11, 2019
8V41N012A Datasheet
Reliability Information
Table 20. JA vs. Air Flow Table for a 72 Lead VFQFPN
JA vs. Air Flow
0
1
2
26.6°C/W
20°C/W
17.9°C/W
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Transistor Count
The transistor count for 8V41N012A is: 176,555.
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information
is the most current data available.
www.idt.com/document/psc/72-vfqfpn-package-outline-drawing-100-x-100-x-090-mm-body-epad-590-x-590-mm-punch-050mm-pitch
Marking Diagram
▪ Line 1 is the part number.
▪ Line 2 indicates the package type.
▪ Line 3 indicates the following:
• “#” denotes stepping.
• “YY” is the last two digits of the year and “WW” is a work week number
that the part was assembled.
• “$” denotes the mark code.
Ordering Information
Orderable Part Number
Marking
Package
Shipping Packaging
Temperature
8V41N012ANLGI
8V41N012ANLGI
10 x 10 mm 72-VFQFPN,
Lead-Free
Tray
-40C to 85C
8V41N012ANLGI8
8V41N012ANLGI
10 x 10 mm 72-VFQFPN,
Lead-Free
Tape and Reel
-40C to 85C
©2019 Integrated Device Technology, Inc
30
October 11, 2019
8V41N012A Datasheet
Revision History
Revision Date
Description of Change
October 11, 2019
▪ Updated the package diagrams; however, no technical changes
▪ Changed the document status to production
October 12, 2018
Initial release.
Corporate Headquarters
Sales
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
Tech Support
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc All rights reserved.
©2019 Integrated Device Technology, Inc
31
October 11, 2019
72-VFQFPN, Package Outline Drawing
10.0 x 10.0 x 0.90 mm Body, Epad 5.90 x 5.90 mm Punch 0.50mm Pitch
NLG72D1, PSC-4208-05, Rev 01, Page 1
© Integrated Device Technology, Inc.
72-VFQFPN, Package Outline Drawing
10.0 x 10.0 x 0.90 mm Body, Epad 5.90 x 5.90 mm Punch 0.50mm Pitch
NLG72D1, PSC-4208-05, Rev 01, Page 2
© Integrated Device Technology, Inc.
72-VFQFPN, Package Outline Drawing
10.0 x 10.0 x 0.90 mm Body, Epad 5.90 x 5.90 mm Punch 0.50mm Pitch
NLG72D1, PSC-4208-05 Rev 01, Page 3
Package Revision History
Date Created
© Integrated Device Technology, Inc.
Description
Rev No.
Sept 5, 2019
Rev 01
Update to New Format
Feb 2, 2016
Rev 00
Initial Release
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.
工商网监
湘ICP备2023018690号
