8S89871ANLGI8

IDT8S89871I 1:2 Differential-to-LVPECL Buffer/Divider Datasheet Description Features The IDT8S89871I is a high speed Differential-to-LVPECL Buffer/Divider. The IDT8S89871I has a selectable ÷2, ÷4, ÷8, ÷16 output dividers. The clock input has internal termination resistors, allowing it to interface with several differential signal types while minimizing the number of required external components. • • • • Three LVPECL output pairs The QA output provides an extra copy of the input frequency, while QB is a divided down output of the input frequency. Both output banks are phase matched and maintain a matched delay independent of the divider setting. • • • • • • • Output frequency: 2.5GHz The device is packaged in a small, 3 x 3 mm VFQFN package, making it ideal for use on space-constrained boards. Frequency divide select options: ÷2, ÷4, ÷8, ÷16 (Bank B) Pass-through output (Bank A) IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML Bank skew: 40ps (maximum), Bank B Part-to-part skew: 230ps (maximum) Additive phase jitter, RMS: 0.15ps (typical) Voltage supply range: 2.375V to 3.6V -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram IDT8S89871I 16-Lead VFQFN 3mm x 3mm x 0.925mm package body NL Package Top View ©2017 Integrated Device Technology, Inc. 1 November 28, 2017 IDT8S89871I Datasheet Table 1. Pin Descriptions Number Name 1, 2 QB0, nQB0 Output Type Description Differential output pair. LVPECL interface levels. 3, 4 QB1, nQB1 Output Differential output pair. LVPECL interface levels. 5, 6 QA, nQA Output Differential output pair. LVPECL interface levels. 7, 14 VCC Power Power supply pins. 8 nRESET Input Pullup QB [1:0] output reset. Input threshold is VCC/2. Includes a 37k pull-up resistor. LVTTL/LVCMOS interface levels. See Table 3. Inverting differential LVPECL clock input. RIN = 50 termination to VT. 9 nIN Input 10 VREF_AC Output 11 VT Input Termination input. 12 IN Input Non-inverting LVPECL differential clock input. RIN = 50 termination to VT. 13 VEE Power 15, 16 S1, S0 Input Reference voltage for AC-coupled applications. Negative supply pin. Pullup Select pins. LVCMOS/LVTTL interface levels. See Table 3. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter RPULLUP Input Pullup Resistor ©2017 Integrated Device Technology, Inc. Test Conditions Minimum Typical 37 2 Maximum Units k November 28, 2017 IDT8S89871I Datasheet Function Table Table 3. Control Input and Divider Truth Table Inputs Outputs nRESET S1 S0 QA Output QB Output 1 (default) 0 0 Reference Clock Reference Clock ÷2 1 0 1 Reference Clock Reference Clock ÷4 1 1 0 Reference Clock Reference Clock ÷8 1 1 (default) 1 (default) Reference Clock Reference Clock ÷16 0 X X Reference Clock Q = LOW, nQ = HIGH; Clock Disabled Figure 1. nRESET Timing Diagram ©2017 Integrated Device Technology, Inc. 3 November 28, 2017 IDT8S89871I Datasheet Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Input Current, IN, nIN ±50mA VT Current, IVT ±100mA VREF_AC Input Sink/Source, IREF_AC ±2mA Operating Temperature Range, TA -40°C to +85°C Package Thermal Impedance, JA, (Junction-to-Ambient) 74.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 0.3V or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VCC Power Supply Voltage ICC Power Supply Current Minimum Typical Maximum Units 2.375 3.3 3.6 V 57 mA Outputs Unterminated Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 0.3V or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current S[1:0], nRESET VCC = VIN = 3.6V or 2.625V IIL Input Low Current S[1:0], nRESET VCC = 3.6V or 2.625V, VIN = 0V ©2017 Integrated Device Technology, Inc. 4 Minimum Maximum Units 2.2 VCC + 0.3 V 0 0.8 V 10 μA -150 Typical μA November 28, 2017 IDT8S89871I Datasheet Table 4C. Differential DC Characteristics, VCC = 3.3V ± 0.3V or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units RIN Input Resistance IN, nIN IN to VT 40 50 60  VIH Input High Voltage IN, nIN 0.15 VCC + 0.3 V VIL Input Low Voltage IN, nIN 0 VIH – 0.15 V VIN Input Voltage Swing; NOTE 1 0.15 VCC V VDIFF_IN Differential Input Voltage Swing 0.3 IIN Input Current; NOTE 2, 3 VREF_AC Bias Voltage V IN, nIN VCC – 1.46 VCC – 1.38 45 mA VCC – 1.31 V NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing diagram. NOTE 2: Guaranteed by design. NOTE 3: Because of the internal termination RIN, the input current IIN will be determined by the voltages applied at IN, nIN and VT. Observe the voltages applied to those pins so the input current does not exceed the maximum limit. Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 0.3V or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VOUT VDIFF_OUT Test Conditions Minimum Typical Maximum Units VCC – 1.175 VCC – 0.82 V VCC – 2.0 VCC – 1.575 V Output Voltage Swing 0.6 1.0 V Differential Output Voltage Swing 1.2 2.0 V NOTE: Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50 to VCC – 2V. ©2017 Integrated Device Technology, Inc. 5 November 28, 2017 IDT8S89871I Datasheet AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V ± 0.3V or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency fIN Input Frequency tPD Propagation Delay; (Differential); NOTE 1 tsk(o) Output Skew; NOTE 2, 5 tsk(b) Bank Skew; NOTE 3, 5 tsk(pp) Part-to-Part Skew; NOTE 4, 5 tjit Buffer Additive Jitter; RMS; refer to Additive Phase Jitter Section; tRR Reset Recovery Time tR / tF Output Rise/Fall Time Test Conditions Minimum Typical Maximum Units Output Swing 450mV 2.5 GHz ÷2, ÷4, ÷8 3.2 GHz ÷1, ÷16 2.5 GHz Input Swing: