9DBV0641AKLF

9DBV0641 6-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 100ohms DATASHEET Description Features/Benefits The 9DBV0641 is a member of Renesas’ 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Zo = 100 for direct connection to 100 transmission lines. The device has 6 output enables for clock management and 3 selectable SMBus addresses. • Direct connection to 100 transmission lines; saves 24 Recommended Application • • • • 1.8V PCIe Gen1–5 Zero Delay/Fanout Buffer (ZDB/FOB) • • Output Features • Six 1–200 MHz Low-Power (LP) HCSL DIF pairs with Zo = 100 • Key Specifications • • • • • DIF cycle-to-cycle jitter < 50ps DIF output-to-output skew < 50ps PCIe Gen5 CC additive phase jitter < 40fs RMS 12kHz–20MHz additive phase jitter = 156fs RMS at 156.25MHz (typical) • • • • • Block Diagram vOE(5:0)# 6 DIF5 CLK_IN CLK_IN# SSCompatible PLL vSADR ^vHIBW_BYPM_LOBW# ^CKPWRGD_PD# SDATA_3.3 SCLK_3.3 9DBV0641 R31DS0077EU0400 AUGUST 2, 2021 resistors compared to standard PCIe devices 55mW typical power consumption in PLL mode; minimal power consumption Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings OE# pins; support DIF power management HCSL compatible differential input; can be driven by common clock sources Spread Spectrum tolerant; allows reduction of EMI Programmable Slew rate for each output; allows tuning for various line lengths Programmable output amplitude; allows tuning for various application environments Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application Outputs blocked until PLL is locked; clean system start-up Configuration can be accomplished with strapping pins; SMBus interface not required for device control 3.3V tolerant SMBus interface works with legacy controllers Space saving 5 × 5mm 40-VFQFPN; minimal board space 3 selectable SMBus addresses; multiple devices can easily share an SMBus segment DIF4 DIF3 DIF2 DIF1 CONTROL LOGIC DIF0 1 ©2021 Renesas Electronics Corporation 9DBV0641 DATASHEET VDD1.8 VDDIO DIF4 DIF4# vOE4# DIF5 DIF5# vOE5# VDDIO ^CKPWRGD_PD# Pin Configuration 40 39 38 37 36 35 34 33 32 31 vSADR_tri ^vHIBW_BYPM_LOBW# FB_DNC FB_DNC# VDDR1.8 CLK_IN CLK_IN# GNDDIG SCLK_3.3 SDATA_3.3 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 9DBV0641 Paddle is GND NC vOE3# DIF3# DIF3 VDDIO VDDA1.8 vOE2# DIF2# DIF2 vOE1# NC DIF1# DIF1 VDDIO DIF0# VDD1.8 DIF0 vOE0# VDDIO VDDDIG1.8 11 12 13 14 15 16 17 18 19 20 40-pin VFQFPN ^ prefix indicates internal Pull-Up Resistor v prefix indicates Internal Pull-Dow n Resistor 5mm x 5mm 0.4mm pin pitch SMBus Address Selection Table State of SADR on first application of CKPWRGD_PD# SADR 0 M 1 Address 1101011 1101100 1101101 + Read/Write bit x x x Power Management Table SMBus DIFx OEx# Pin True O/P Comp. O/P OEx bit 0 X X X Low Low 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 Running 1 1 Low Low 1. If Bypass mode is selected, the PLL will be off, and outputs will follow this table. CKPWRGD_PD# CLK_IN 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS PLL Off On1 On1 On1 2 R31DS0077EU0400 AUGUST 2, 2021 9DBV0641 DATASHEET Power Connections Pin Number VDD VDDIO 5 41 11 16, 31 GND 8 12,17,26,32, 39 25 41 41 Description Input receiver analog Digital Power DIF outputs, Logic PLL Analog Frequency Select Table FSEL Byte3 [1:0] 00 01 10 11 CLK_IN (MHz) 100.00 50.00 125.00 Reserved DIFx (MHz) CLK_IN CLK_IN CLK_IN Reserved PLL Operating Mode HiBW_BypM_LoBW# 0 M 1 MODE PLL Lo BW Bypass PLL Hi BW R31DS0077EU0400 AUGUST 2, 2021 Byte1 [7:6] Readback 00 01 11 Byte1 [4:3] Control 00 01 11 3 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0641 DATASHEET Pin Descriptions PIN # PIN NAME 1 vSADR_tri 2 ^vHIBW_BYPM_LOBW# 3 FB_DNC 4 FB_DNC# 5 VDDR1.8 6 7 8 9 10 11 12 CLK_IN CLK_IN# GNDDIG SCLK_3.3 SDATA_3.3 VDDDIG1.8 VDDIO 13 vOE0# 14 15 16 17 18 19 20 DIF0 DIF0# VDD1.8 VDDIO DIF1 DIF1# NC 21 vOE1# 22 23 DIF2 DIF2# 24 vOE2# 25 26 27 28 VDDA1.8 VDDIO DIF3 DIF3# 29 vOE3# 30 31 32 33 34 NC VDD1.8 VDDIO DIF4 DIF4# 35 vOE4# 36 37 DIF5 DIF5# 38 vOE5# 39 VDDIO 40 ^CKPWRGD_PD# 41 ePAD PIN TYPE DESCRIPTION LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table. IN LATCHED Trilevel input to select High BW, Bypass or Low BW mode. IN See PLL Operating Mode Table for Details. True clock of differential feedback. The feedback output and feedback input are connected DNC internally on this pin. Do not connect anything to this pin. Complement clock of differential feedback. The feedback output and feedback input are DNC connected internally on this pin. Do not connect anything to this pin. 1.8V power for differential input clock (receiver). This VDD should be treated as an Analog PWR power rail and filtered appropriately. IN True Input for differential reference clock. IN Complementary Input for differential reference clock. GND Ground pin for digital circuitry IN Clock pin of SMBus circuitry, 3.3V tolerant. I/O Data pin for SMBus circuitry, 3.3V tolerant. PWR 1.8V digital power (dirty power) PWR Power supply for differential outputs Active low input for enabling DIF pair 0. This pin has an internal pull-down. IN 1 =disable outputs, 0 = enable outputs OUT Differential true clock output OUT Differential Complementary clock output PWR Power supply, nominal 1.8V PWR Power supply for differential outputs OUT Differential true clock output OUT Differential Complementary clock output N/A No Connection. Active low input for enabling DIF pair 1. This pin has an internal pull-down. IN 1 =disable outputs, 0 = enable outputs OUT Differential true clock output OUT Differential Complementary clock output Active low input for enabling DIF pair 2. This pin has an internal pull-down. IN 1 =disable outputs, 0 = enable outputs PWR 1.8V power for the PLL core. PWR Power supply for differential outputs OUT Differential true clock output OUT Differential Complementary clock output Active low input for enabling DIF pair 3. This pin has an internal pull-down. IN 1 =disable outputs, 0 = enable outputs N/A No Connection. PWR Power supply, nominal 1.8V PWR Power supply for differential outputs OUT Differential true clock output OUT Differential Complementary clock output Active low input for enabling DIF pair 4. This pin has an internal pull-down. IN 1 =disable outputs, 0 = enable outputs OUT Differential true clock output OUT Differential Complementary clock output Active low input for enabling DIF pair 5. This pin has an internal pull-down. IN 1 =disable outputs, 0 = enable outputs PWR Power supply for differential outputs Input notifies device to sample latched inputs and start up on first high assertion. Low enters IN Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. GND Connect paddle to ground. 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 4 R31DS0077EU0400 AUGUST 2, 2021 9DBV0641 DATASHEET Test Loads Low-Power HCSL Differential Output Test Load 5 inches Rs  Zo=100W 2pF Rs 2pF Device Alternate Terminations The 9DBV family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with “Universal” Low-Power HCSL Outputs” for details. R31DS0077EU0400 AUGUST 2, 2021 5 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0641 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DBV0641. These ratings, which are standard values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL Supply Voltage Input Voltage Input High Voltage, SMBus Storage Temperature Junction Temperature Input ESD protection VDDx V IN VIHSMB Ts Tj ESD prot CONDITIONS MIN -0.5 -0.5 TYP SMBus clock and data pins -65 Human Body Model MAX 2.5 VDD+0.5 3.6 150 125 2000 UNITS NOTES V V V °C °C V 1,2 1,3 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. 3 Not to exceed 2.5V. Electrical Characteristics–Clock Input Parameters TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions. See Test Loads for Loading Conditions. PARAMETER SYMBOL Input High Voltage - DIF_IN V IHDIF Input Low Voltage - DIF_IN V ILDIF Input Common Mode Voltage - DIF_IN Input Amplitude - DIF_IN Input Slew Rate - DIF_IN Input Leakage Current CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) MIN TYP MAX UNITS NOTES 300 750 1150 mV 1 V SS - 300 0 300 mV 1 V COM Common Mode Input Voltage 200 725 mV 1 V SWING dv/dt IIN Peak to Peak value (VIHDIF - V ILDIF ) Measured differentially V IN = V DD , V IN = GND 300 0.35 -5 1450 8 5 mV V/ns uA 1 1,2 Input Duty Cycle dtin Measurement from differential waveform 45 55 % 1 Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 0 150 ps 1 1 2 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through +/-75mV window centered around differential zero. 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 6 R31DS0077EU0400 AUGUST 2, 2021 9DBV0641 DATASHEET Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating Conditions TA = TAMB, Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX Supply Voltage Output Supply Voltage VDDx VDDIO Supply voltage for core and analog Supply voltage for Low Power HCSL Outputs 1.7 0.95 1.8 1.05-1.8 1.9 1.9 V V Ambient Operating Temperature Input High Voltage Input Mid Voltage Input Low Voltage TAMB Commmercial range Industrial range Single-ended inputs, except SMBus Single-ended tri-level inputs ('_tri' suffix) Single-ended inputs, except SMBus Single-ended inputs, VIN = GND, VIN = VDD Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors Bypass mode 100MHz PLL mode 125MHz PLL mode 50MHz PLL mode 0 -40 0.75 V DD 0.4 VDD -0.3 -5 25 25 70 85 VDD + 0.3 0.6 VDD 0.25 V DD 5 °C °C V V V uA 200 uA 1.5 1.5 MHz MHz MHz MHz nH pF pF pF 1 1 1,6 1 1 ms 1,2 30 33 kHz 0 66 kHz 1 3 clocks 1,3 300 us 1,3 VILSMB VIHSMB VOLSMB I PULLUP VDDSMB tRSMB t FSMB Logic Inputs, except DIF_IN DIF_IN differential clock inputs Output pin capacitance From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable Frequency for PCIe Applications (Triangular Modulation) Allowable Frequency for non-PCIe Applications (Triangular Modulation) DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of single-ended control inputs Rise time of single-ended control inputs VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V @ IPULLUP @ VOL Bus Voltage (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 200 140 175 65 7 5 2.7 6 5 5 0.8 3.6 0.4 2 2 4 5 3.6 1000 300 ns ns V V V mA V ns ns fMAXSMB Maximum SMBus operating frequency 400 kHz 7 Input Current Input Frequency Pin Inductance VIH VIM VIL I IN I INP Fibyp Fipll Fipll Fipll Lpin CIN Capacitance CINDIF_IN COUT Clk Stabilization TSTAB Input SS Modulation Frequency PCIe Input SS Modulation Frequency non-PCIe fMODINPCIe f MODIN OE# Latency t LATOE# Tdrive_PD# tDRVPD Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency tF tR -200 1 50 62.5 25 2.1 4 1.7 100.00 125.00 50.00 UNITS NOTES 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are >200 mV 4 For VDDSMB < 3.3V, VILSMB = 0.65VDDSMB 6 DIF_IN input 2 7 The differential input clock must be running for the SMBus to be active R31DS0077EU0400 AUGUST 2, 2021 7 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0641 DATASHEET Electrical Characteristics–Low Power HCSL Outputs TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP Scope averaging on, fast setting Scope averaging on, slow setting Slew rate matching, Scope averaging on 1.7 1.1 Slew rate matching dV/dt dV/dt  dV/dt 2.9 2.1 7 4 3.4 20 Voltage High VHIGH 660 791 850 Voltage Low VLOW Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) -150 16 150 Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs 800 -3 1548 414 13 1150 -300 300 250 Slew rate Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off Δ-Vcross Guaranteed by design and characterization, not 100% tested in production. 2 Measured from differential waveform MAX UNITS NOTES 550 140 V/ns V/ns % mV 1,2,3 1,2,3 1,2,4 7 7 mV mV mV mV 7 7 1,2 1,5 1,6 1 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. 7 At default SMBus settings. Electrical Characteristics–Current Consumption TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions PARAMETER Operating Supply Current Powerdown Current 1 2 SYMBOL CONDITIONS IDDA VDDA+VDDR, PLL Mode, @100MHz I DD VDD, All outputs active @100MHz I DDO VDDIO, All outputs active @100MHz VDDA+VDDR, CKPWRGD_PD#=0 I DDAPD I DDPD I DDOPD MIN TYP MAX UNITS NOTES 11 15 mA 1 6 10 mA 1 30 0.6 0.8 0.1 mA 1 mA mA mA 1, 2 1, 2 1, 2 24 0.4 0.5 0.0003 VDD, CKPWRGD_PD#=0 VDDIO, CKPWRGD_PD#=0 Guaranteed by design and characterization, not 100% tested in production. Input clock stopped. 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 8 R31DS0077EU0400 AUGUST 2, 2021 9DBV0641 DATASHEET Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES 1.8 0.8 2.7 1.4 1.3 3.8 2 2 45 50.1 55 MHz MHz dB % 1,5 1,5 1 1 PLL Bandwidth BW PLL Jitter Peaking Duty Cycle t JPEAK t DC -3dB point in High BW Mode -3dB point in Low BW Mode Peak Pass band Gain Measured differentially, PLL Mode Duty Cycle Distortion t DCD Measured differentially, Bypass Mode @100MHz -1 0 1 % 1,3 Jitter, Cycle to cycle t jcyc-cyc Bypass Mode, VT = 50% PLL Mode VT = 50% VT = 50% PLL mode Additive Jitter in Bypass Mode 3000 0 Skew, Output to Output t pdBYP t pdPLL tsk3 3600 -4 39 14 0.1 4500 200 50 50 5 ps ps ps ps ps 1 1,4 1,4 1,2 1,2 Skew, Input to Output 1 Guaranteed by design and characterization, not 100% tested in production. Measured from differential waveform 3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 4 All outputs at default slew rate 5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN. 2 Electrical Characteristics–Phase Jitter Parameters — 12kHz to 20MHz TAMB = over the specified operating range. Supply Voltages per normal operation conditions. See Test Loads for loading conditions. Parameter Symbol Conditions Minimum Typical Maximum 12k-20M Additive Phase Jitter, Fan-out Buffer M ode, tjph12k-20MFOB 156 Fan-out Buffer M ode SSC OFF, 156.25M Hz Notes: 1. Applies to all differential outputs, guaranteed by design and characterization. See Test Loads for measurement setup details. 2. 12kHz to 20M Hz brick wall filter. 2 Specification Limit Units Notes n/a fs (rms) 1, 2, 3 2 3. For RM S values additive jitter is calculated by solving for b where [b = sqrt(c - a )], a is rms input jitter and c is rms total jitter. R31DS0077EU0400 AUGUST 2, 2021 9 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0641 DATASHEET Electrical Characteristics–Additive PCIe Phase Jitter for Fanout Buffer Mode[7] T AMB = over the specified operating range. Supply Voltages per normal operation conditions. See Test Loads for loading conditions. Parameter Symbol Conditions Minimum Typical Maximum Limit tjphPCIeG1-CC PCIe Gen 1 (2.5 GT/s) 1.7 3.0 86 PCIe Gen 2 Hi Band (5.0 GT/s) 0.033 0.049 3 PCIe Gen 2 Lo Band (5.0 GT/s) 0.122 0.199 3.1 tjphPCIeG3-CC PCIe Gen 3 (8.0 GT/s) 0.059 0.098 1 tjphPCIeG4-CC PCIe Gen 4 (16.0 GT/s) 0.059 0.098 0.5 tjphPCIeG5-CC PCIe Gen 5 (32.0 GT/s) 0.023 0.038 0.15 tjphPCIeG1-SRIS PCIe Gen 1 (2.5 GT/s) 0.175 0.038 n/a tjphPCIeG2-SRIS PCIe Gen 2 (5.0 GT/s) 0.156 0.275 n/a tjphPCIeG3-SRIS PCIe Gen 3 (8.0 GT/s) 0.041 0.247 n/a tjphPCIeG4-SRIS PCIe Gen 4 (16.0 GT/s) 0.043 0.064 n/a tjphPCIeG5-SRIS PCIe Gen 5 (32.0 GT/s) 0.036 0.066 n/a tjphPCIeG2-CC Additive PCIe Phase Jitter, Fan-out Buffer Mode (Common Clocked Architecture) Additive PCIe Phase Jitter, Fan-out Buffer Mode (SRIS Architecture) Units ps (p-p) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) Notes 1, 2 1, 2 1, 2 1, 2 1, 2, 3, 4 1, 2, 3, 5 1, 2, 6 1, 2, 6 1, 2, 6 1, 2, 6 1, 2, 6 Notes: 1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. The total Ref Clk jitter limits for each data rate are listed for convenience. The worst case results for each data rate are summarized in this table. If oscilloscope data is used, equipment noise is removed from all results. 2. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately Jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200 M Hz (at 300 M Hz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data rate, the RM S jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results the RTO result must be used. 3. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2 M Hz taking care to minimize removal of any non-SSC content. 4. Note that 0.7 ps RM S is to be used in channel simulations to account for additional noise in a real system. 5. Note that 0.25 ps RM S is to be used in channel simulations to account for additional noise in a real system. 6. The PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, however, it does not provide specification limits, hence the n/a in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RM S values, twice as good is equivalent to dividing the CC value by 2. And additional consideration is the value for which to divide by  2. The conservative approach is to divide the ref clock jitter limit, and the case can be made for dividing the channel simulation values by 2, if the ref clock is close to the Tx clock input. An example for Gen4 is as follows. A "rule-of-thumb" SRIS limit would be either 0.5ps RM S/2 = 0.35ps RM S if the clock chip is far from the clock input, or 0.7ps RM S/ 2 = 0.5ps RM S if the clock chip is near the clock input.. 7. Additive jitter for RM S values is calculated by solving for b where b √ 𝑐2 𝑎2 , and a is rms input jitter and c is rms output jitter. 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 10 R31DS0077EU0400 AUGUST 2, 2021 9DBV0641 DATASHEET Additive Phase Jitter: 125M (12kHz to 20MHz) RMS additive jitter: 251fs R31DS0077EU0400 AUGUST 2, 2021 11 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0641 DATASHEET General SMBus Serial Interface Information How to Write • • • • • • • • • • How to Read Controller (host) sends a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) sends the byte count = X Renesas clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 Renesas clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write Operation Controller (Host) Renesas (Slave/Receiver) T • • • • • • • • • • • • • • starT bit ACK Beginning Byte = N ACK Data Byte Count = X ACK X Byte O ACK WR starT bit Beginning Byte = N ACK RT RD ACK stoP bit ReaD ACK ACK Byte N + X - 1 Repeat starT Slave Address ACK O WRite ACK O O O O P Renesas Controller (Host) Slave Address WRite Beginning Byte N Index Block Read Operation T Slave Address WR Controller (host) will send a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address Renesas clock will acknowledge Renesas clock will send the data byte count = X Renesas clock sends Byte N+X-1 Renesas clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Data Byte Count=X Beginning Byte N O Note: Read/Write address is latched on SADR pin. 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS X Byte O O N Not acknowledge P stoP bit 12 O O O Byte N + X - 1 R31DS0077EU0400 AUGUST 2, 2021 9DBV0641 DATASHEET SMBus Table: Output Enable Register 1 Byte 0 Name Control Function Type 0 DIF OE5 Output Enable RW Low/Low Bit 7 DIF OE4 Output Enable RW Low/Low Bit 6 Reserved Bit 5 DIF OE3 Output Enable RW Low/Low Bit 4 DIF OE2 Output Enable RW Low/Low Bit 3 DIF OE1 Output Enable RW Low/Low Bit 2 Reserved Bit 1 DIF OE0 Output Enable RW Low/Low Bit 0 1. A low on these bits will override the OE# pin and force the differential output Low/Low 1 Enabled Enabled Enabled Enabled Enabled Enabled SMBus Table: PLL Operating Mode and Output Amplitude Control Register Byte 1 Name Control Function Type 0 1 PLLMODERB1 PLL Mode Readback Bit 1 Bit 7 R See PLL Operating Mode Table PLLMODERB0 PLL Mode Readback Bit 0 Bit 6 R Enable SW control of PLL Values in B1[7:6] Values in B1[4:3] PLLMODE_SWCNTRL RW Bit 5 Mode: set PLL Mode set PLL Mode PLLMODE1 PLL Mode Control Bit 1 Bit 4 RW 1 See PLL Operating Mode Table PLLMODE0 PLL Mode Control Bit 0 Bit 3 RW 1 Reserved Bit 2 AMPLITUDE 1 RW 00 = 0.6V 01 = 0.7V Bit 1 Controls Output Amplitude AMPLITUDE 0 RW 10= 0.8V 11 = 0.9V Bit 0 1. B1[5] must be set to a 1 for these bits to have any effect on the part. SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function SLEWRATESEL DIF5 Adjust Slew Rate of DIF5 Bit 7 SLEWRATESEL DIF4 Adjust Slew Rate of DIF4 Bit 6 Reserved Bit 5 SLEWRATESEL DIF3 Adjust Slew Rate of DIF3 Bit 4 SLEWRATESEL DIF2 Adjust Slew Rate of DIF2 Bit 3 SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 Bit 2 Reserved Bit 1 SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 Bit 0 SMBus Table: Frequency Select Control Register Byte 3 Name Control Function Reserved Bit 7 Reserved Bit 6 Enable SW selection of FREQ_SEL_EN Bit 5 frequency FSEL1 Freq. Select Bit 1 Bit 4 FSEL0 Freq. Select Bit 0 Bit 3 Reserved Bit 2 Reserved Bit 1 SLEWRATESEL FB Adjust Slew Rate of FB Bit 0 1. B3[5] must be set to a 1 for these bits to have any effect on the part. Type RW RW 0 Slow setting Slow setting 1 Fast setting Fast setting RW RW RW Slow setting Slow setting Slow setting Fast setting Fast setting Fast setting RW Slow setting Fast setting Type 0 1 RW SW frequency change disabled SW frequency change enabled RW 1 RW 1 RW See Frequency Select Table Slow setting Fast setting Default 1 1 1 1 1 1 1 1 Default Latch Latch 0 0 0 1 1 0 Default 1 1 1 1 1 1 1 1 Default 1 1 0 0 0 1 1 1 Byte 4 is Reserved and reads back 'hFF R31DS0077EU0400 AUGUST 2, 2021 13 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0641 DATASHEET SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function RID3 Bit 7 RID2 Bit 6 Revision ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R 0 SMBus Table: Device Type/Device ID Byte 6 Name Device Type1 Bit 7 Device Type0 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 Bit 0 Type R R R R R R R R 0 SMBus Table: Byte Count Register Byte 7 Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Device Type Device ID Control Function Reserved Reserved Reserved Byte Count Programming 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS Type RW RW RW RW RW 1 A rev = 0000 0001 = IDT 1 00 = FG, 01 = DB 10 = DM, 11= DB fanout only 000110 binary or 06 hex 0 Default 0 0 0 0 0 0 0 1 Default 0 1 0 0 0 1 1 0 Default 0 0 0 0 1 Writing to this register will configure how 0 many bytes will be read back, default is 0 = 8 bytes. 0 14 1 R31DS0077EU0400 AUGUST 2, 2021 9DBV0641 DATASHEET Marking Diagrams ICS BV0641AL YYWW COO LOT ICS V0641AIL YYWW COO LOT Notes: 1. “LOT” is the lot sequence number. 2. “COO” denotes country of origin. 3. “YYWW” is the last two digits of the year and week that the part was assembled. 4. Line 2: truncated part number 5. “L” denotes RoHS compliant package. 6. “I” denotes industrial temperature range device. Thermal Characteristics 1 PARAMETER SYMBOL Thermal Resistance θJC θJb θJA0 θJA1 θJA3 θJA5 TYP VALUE Junction to Case 42 Junction to Base 2.4 Junction to Air, still air 39 NDG40 Junction to Air, 1 m/s air flow 33 Junction to Air, 3 m/s air flow 28 Junction to Air, 5 m/s air flow 27 CONDITIONS PKG UNITS NOTES °C/W °C/W °C/W °C/W °C/W °C/W 1 1 1 1 1 1 ePad soldered to board Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 40-VFQFPN (NDG40P2) Ordering Information Part / Order Number Shipping Packaging 9DBV0641AKLF Trays 9DBV0641AKLFT Tape and Reel 9DBV0641AKILF Trays 9DBV0641AKILFT Tape and Reel Package 40-pin VFQFPN 40-pin VFQFPN 40-pin VFQFPN 40-pin VFQFPN Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). R31DS0077EU0400 AUGUST 2, 2021 15 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 9DBV0641 DATASHEET Revision History Revision Date September 8, 2014 September 10, 2014 November 7, 2014 August 2, 2021 Description Move from Advance to Preliminary 1. Updated front page text for consistency. 2. Updated block diagram for consistency. 3. Updated electrical tables with characterization data. 4. Updated SMBus nomenclature - bits did NOT change. 5. Changed IDD spec from 8mA to 10mA MAX. 1. Widened input frequency ranges for PLL modes. 1. Updated document title. 2. Updated Recommended Applications. 3. Updated Key Specifications. 4. Updated Package Outline Drawings section. 5. Updated Phase Jitter tables. 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 16 R31DS0077EU0400 AUGUST 2, 2021 40-VFQFPN, Package Outline Drawing 5.00 x 5.00 x 0.90 mm Body, 3.50 x 3.50 mm Epad, 0.40mm Pitch NDG40P2, PSC-4292-02, Rev 01, Page 1 © Renesas Electronics Corporation 40-VFQFPN, Package Outline Drawing 5.00 x 5.00 x 0.90 mm Body, 3.50 x 3.50 mm Epad, 0.40mm Pitch NDG40P2, PSC-4292-02, Rev 01, Page 2 Package Revision History Date Created © Renesas Electronics Corporation Description Rev No. Feb 25, 2021 01 Update Template to Marketing Version May 17, 2016 00 Initial release IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.