9DBV05x1/9DBV07x1/
9DBV09x1
Datasheet
5 to 9-Output 1.8V Low-Power
Buffers for PCIe Gen1–5
Description
Features
The 9DBV05x1/9DBV07x1/9DBV09x1 fanout buffers are
low-power, high-performance fanout buffers in Renesas' Full
Featured PCIe family. The buffers have 5, 7 or 9 outputs with each
output having an OE# to support the PCIe CLKREQ# function.
The devices have 3 selectable SMBus addresses.
▪ 5–9 Low-Power HCSL (LP-HCSL) outputs
PCIe Clocking Architectures
▪ Easy AC-coupling to other logic families, see application note
▪ Common Clocked (CC)
▪ Independent Reference (IR) with and without spread spectrum
▪
▪
▪
▪
▪
• 100Ω outputs eliminate 4 resistors per output pair
(9DBVxx41)
• 33Ω outputs eliminate 2 resistors per output pair allowing
use in both 85Ω and 100Ω systems (9DBVxx31)
AN-891
(SRIS, SRNS)
Typical Applications
▪
▪
▪
▪
▪
Servers/High-performance Computing
nVME Storage
Networking
Accelerators
Industrial Control
Spread spectrum compatible
OE# pins support PCIe CLKREQ# function
3 selectable SMBus addresses
3.3V tolerant SMBus interface
SMBus-selectable features allow optimization to customer
requirements:
• Individual slew rate control for each output
• Differential output amplitude
• Device contains default configuration; SMBus interface not
required for device operation
▪ -40°C to +85°C operating temperature range
▪ Packages: See Ordering Information for more details
Key Specifications
▪ PCIe Gen5 CC additive phase jitter < 40fs RMS
▪ 12kHz–20MHz additive phase jitter = 165fs RMS at 156.25MHz
(typical)
▪ Output-to-output skew < 50ps
▪ Power consumption as low as 41mW (typical)
▪ 1MHz to 200MHz operating frequency
Block Diagram
VDDDIG1.8
VDDR1.8
VDDIO
7 and 9 output parts
only
CLK_IN#
DIFn#
CLK_IN
DIFn
vSADR_tri
SMBus
Engine
SMBCLK
5, 7 or 9
outputs
Factory
Configuration
SMBDAT
DIF0#
^CKPWRGD_PD#
vOE[n:0]#
DIF0
n+1
Control Logic
GNDR
©2020 Renesas Electronics Corporation
Resis tors are integrated on
9DBVxx4x
EPAD/GND
1
GNDDIG
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PCIe Clocking Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
9DBV05x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
9DBV07x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
9DBV09x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9DBV05x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9DBV07x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9DBV09x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
©2020 Renesas Electronics Corporation
2
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Pin Assignments
9DBV05x1 Pin Assignment
GND
VDDO1.8
DIF3
vOE3#
DIF3#
GND
vSADR_tri
^CKPWRGD_PD#
Figure 1. Pin Assignment for 5 × 5 mm 32-VFQFPN Package – Top View
32 31 30 29 28 27 26 25
vOE4# 1
DIF4 2
DIF4# 3
9DBV05x1
Connect EPAD to
GND
VDDR1.8 4
CLK_IN 5
CLK_IN# 6
GNDR 7
GNDDIG 8
24 vOE2#
23 DIF2#
22 DIF2
21 VDDO1.8
20 GND
19 DIF1#
18 DIF1
17 vOE1#
GND
VDDO1.8
DIF0#
vOE0#
DIF0
SCLK_3.3
SDATA_3.3
VDDDIG1.8
9 10 11 12 13 14 15 16
32-VFQFPN, 5 x 5 mm, 0.5mm pitch
^ prefix indicates internal 120kOhm pull-up resistor
^v prefix indicates internal 120kOhm pull-up and pull-down resistor
(biased to VDD/2)
v prefix indicates internal 120kOhm pull-down resistor
©2020 Renesas Electronics Corporation
3
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
9DBV07x1 Pin Assignment
VDDO1.8
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDDIO
^CKPWRGD_PD#
Figure 2. Pin Assignment for 5 × 5 mm 40-VFQFPN Package – Top View
40 39 38 37 36 35 34 33 32 31
vSADR_tri
vOE6#
DIF6
DIF6#
VDDR1.8
CLK_IN
CLK_IN#
GNDDIG
SCLK_3.3
SDATA_3.3
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
9DBV07x1
Connect EPAD to GND
NC
vOE3#
DIF3#
DIF3
VDDIO
VDDO1.8
vOE2#
DIF2#
DIF2
vOE1#
NC
DIF1#
DIF1
VDDIO
VDDO1.8
DIF0#
DIF0
vOE0#
VDDIO
VDDDIG1.8
11 12 13 14 15 16 17 18 19 20
40-VFQFPN, 5 x 5 mm 0.4mm pitch
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
©2020 Renesas Electronics Corporation
4
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
9DBV09x1 Pin Assignment
vOE5#
VDDIO
GND
DIF6
DIF6#
vOE6#
DIF7
DIF7#
37
vOE7#
48 47 46 45 44 43 42 41 40 39 38
VDDIO
VDDO1.8
^CKPWRGD_PD#
Figure 3. Pin Assignment for 6 × 6 mm 48-VFQFPN Package – Top View
vSADR_tri 1
36 DIF5#
vOE8# 2
35 DIF5
DIF8 3
34 vOE4#
DIF8# 4
33 DIF4#
VDDR1.8 5
32 DIF4
9DBV09x1
Connect EPAD to ground
CLK_IN 6
CLK_IN# 7
31 VDDIO
30 VDDO1.8
GNDR 8
29 GND
GNDDIG 9
28 vOE3#
SCLK_3.3 10
27 DIF3#
SDATA_3.3 11
26 DIF3
VDDDIG1.8 12
25 vOE2#
24
DIF2#
DIF2
GND
VDDIO
VDDO1.8
DIF1#
DIF1
vOE1#
DIF0#
DIF0
vOE0#
VDDIO
13 14 15 16 17 18 19 20 21 22 23
48-VFQFPN, 6 x 6 mm, 0.4mm pitch
v prefix indicates internal 120kOhm pull-down resistor
^ prefix indicates internal 120kOhm pull-up resistor
^v prefix indicates internal 120kOhm pull-up and pull-down resistor (biased to VDD/2)
©2020 Renesas Electronics Corporation
5
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
Description
9DBV09xx 9DBV07xx 9DBV05xx
Pin No.
Pin No.
Pin No.
Name
Type
^CKPWRGD_PD#
Input
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions
exit Power Down Mode. This pin has internal pull-up resistor.
48
40
31
CLK_IN
Input
True input for differential reference clock.
6
6
5
CLK_IN#
Input
Complementary input for differential reference clock.
7
7
6
DIF0
Output
Differential true clock output.
15
14
13
DIF0#
Output
Differential complementary clock output.
16
15
14
DIF1
Output
Differential true clock output.
18
18
18
DIF1#
Output
Differential complementary clock output.
19
19
19
DIF2
Output
Differential true clock output.
23
22
22
DIF2#
Output
Differential complementary clock output.
24
23
23
DIF3
Output
Differential true clock output.
26
27
27
DIF3#
Output
Differential complementary clock output.
27
28
28
DIF4
Output
Differential true clock output.
32
33
2
DIF4#
Output
Differential complementary clock output.
33
34
3
DIF5
Output
Differential true clock output.
35
36
—
DIF5#
Output
Differential complementary clock output.
36
37
—
DIF6
Output
Differential true clock output.
41
3
—
DIF6#
Output
Differential complementary clock output.
42
4
—
DIF7
Output
Differential true clock output.
44
—
—
DIF7#
Output
Differential complementary clock output.
45
—
—
DIF8
Output
Differential true clock output.
3
—
—
DIF8#
Output
Differential complementary clock output.
4
—
—
EPAD
GND
Connect epad to ground.
49
41
33
GND
GND
Ground pin.
22, 29, 40
41
15, 20, 26,
30
GNDDIG
GND
Ground pin for digital circuitry.
9
41
8
GNDR
GND
Analog ground pin for the differential input (receiver).
8
41
7
No connect.
—
20,30
—
Input
Clock pin of SMBus circuitry, 3.3V tolerant.
10
30
10
SDATA_3.3
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
11
9
11
VDDDIG1.8
Power
1.8V digital power (dirty power).
12
11
9
VDDIO
Power
Power supply for differential outputs.
13, 21, 31, 12, 17, 26,
39, 47
32, 39
VDDO1.8
Power
Power supply for outputs. Nominally 1.8V.
20, 30, 38 16, 25, 31 16, 21, 25
NC
SCLK_3.3
—
©2020 Renesas Electronics Corporation
6
—
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 1. Pin Descriptions (Cont.)
Name
9DBV09xx 9DBV07xx 9DBV05xx
Pin No.
Pin No.
Pin No.
Type
Description
VDDR1.8
Power
Power supply for differential input clock (receiver). This VDD should be
treated as an analog power rail and filtered appropriately. Nominally 1.8V.
5
5
4
vOE0#
Input
Active low input for enabling output 0. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
14
13
12
vOE1#
Input
Active low input for enabling output 1. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
17
21
17
vOE2#
Input
Active low input for enabling output 2. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
25
24
24
vOE3#
Input
Active low input for enabling output 3. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
28
29
29
vOE4#
Input
Active low input for enabling output 4. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
34
35
1
vOE5#
Input
Active low input for enabling output 5. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
37
38
—
vOE6#
Input
Active low input for enabling output 6. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
43
2
—
vOE7#
Input
Active low input for enabling output 7. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
46
—
—
vOE8#
Input
Active low input for enabling output 8. This pin has an internal pull-down.
1 = disable output, 0 = enable output.
2
—
—
1
1
32
vSADR_tri
Latched Tri-level latch to select SMBus Address. It has an internal pull-down
In
resistor. See SMBus Address Selection table.
©2020 Renesas Electronics Corporation
7
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV05x1/9DBV07x1/9DBV09x1. These ratings, which are
standard values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Supply Voltage
VDDx
Input Voltage
VIN
Input High Voltage, SMBus
VIHSMB
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD Protection
ESD prot
1
2
3
Conditions
Applies to VDD, VDDA and VDDIO.
Minimum
Typical
Maximum
Units
Notes
-0.5
2.5
V
1,2
-0.5
VDD + 0.5
V
1,3
3.6
V
1
150
°C
1
125
°C
1
V
1
SMBus clock and data pins.
-65
Human Body Model
2000
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
Not to exceed 2.5V.
Thermal Characteristics
Table 3. Thermal Characteristics
Parameter
9DBV09x1
Thermal
Resistance
9DBV07x1
Thermal
Resistance
Symbol
Conditions
Package
Typical Values
Units
Notes
θJC
Junction to case.
33
°C/W
1
θJb
Junction to base.
2
°C/W
1
θJA0
Junction to air, still air.
37
°C/W
1
θJA1
Junction to air, 1 m/s air flow.
30
°C/W
1
θJA3
Junction to air, 3 m/s air flow.
27
°C/W
1
θJA5
Junction to air, 5 m/s air flow.
26
°C/W
1
θJC
Junction to case.
42
°C/W
1
θJb
Junction to base.
2
°C/W
1
θJA0
Junction to air, still air.
39
°C/W
1
θJA1
Junction to air, 1 m/s air flow.
33
°C/W
1
θJA3
Junction to air, 3 m/s air flow.
28
°C/W
1
θJA5
Junction to air, 5 m/s air flow.
27
°C/W
1
©2020 Renesas Electronics Corporation
NDG48
NDG40
8
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 3. Thermal Characteristics (Cont.)
Parameter
Symbol
9DBV05x1
Thermal
Resistance
1
Conditions
Package
Typical Values
Units
Notes
θJC
Junction to case.
42
°C/W
1
θJb
Junction to base.
2
°C/W
1
θJA0
Junction to air, still air.
39
°C/W
1
θJA1
Junction to air, 1 m/s air flow.
33
°C/W
1
θJA3
Junction to air, 3 m/s air flow.
28
°C/W
1
θJA5
Junction to air, 5 m/s air flow.
27
°C/W
1
NLG32
EPAD soldered to ground.
Electrical Characteristics
TA = TCOM or TIND. Supply voltages per normal operation conditions; see Test Loads for loading conditions.
Table 4. Clock Input Parameters
Parameter
Symbol
2
Minimum Typical Maximum
VCROSS Crossover voltage.
150
Input Swing – DIF_IN
VSWING
Differential value.
300
Input Slew Rate – DIF_IN
dv/dt
Measured differentially.
0.4
Input Leakage Current
IIN
VIN = VDD , VIN = GND.
Input Duty Cycle
dtin
Input Jitter – Cycle to Cycle
JDIFIn
Input Crossover Voltage – DIF_IN
1
Conditions
900
Units Notes
mV
1
mV
1
8
V/ns
1,2
-5
5
μA
Measurement from differential waveform.
40
60
%
1
Differential measurement.
0
125
ps
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through ±75mV window centered around differential zero.
Table 5. Input/Supply/Common Parameters–Normal Operating Conditions
Parameter
Symbol
Supply Voltage
VDDx
Supply voltage for core and analog.
Output Supply Voltage
VDDIO
Supply voltage for DIF outputs, if present.
Ambient Operating
Temperature
TAMB
Input High Voltage
VIH
Single-ended inputs, except SMBus
Input Mid Voltage
VIM
Single-ended tri-level inputs ('_tri' suffix).
Input Low Voltage
VIL
Single-ended inputs, except SMBus.
IIN
Single-ended inputs, VIN = GND, VIN = VDD.
IINP
Single-ended inputs.
VIN = 0 V; inputs with internal pull-up resistors.
VIN = VDD; inputs with internal pull-down
resistors.
Input Current
©2020 Renesas Electronics Corporation
Conditions
Commercial range (TCOM).
Industrial range (TIND).
9
Minimum
Typical
Maximum Units Notes
1.7
1.8
1.9
V
0.9975
1.05 - 1.8
1.9
V
0
25
70
°C
-40
25
85
°C
0.75 VDD
VDD + 0.3
V
0.4 VDD
0.6 VDD
V
-0.3
0.25 VDD
V
-5
5
μA
-200
200
μA
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 5. Input/Supply/Common Parameters–Normal Operating Conditions (Cont.)
Parameter
Symbol
Input Frequency
FIN
Pin Inductance
Lpin
CIN
Capacitance
Conditions
Minimum
1
Logic inputs, except DIF_IN.
CINDIF_IN DIF_IN differential clock inputs.
Typical
Maximum Units Notes
200
MHz
7
nH
1
1.5
5
pF
1
1.5
2.7
pF
1, 6
COUT
Output pin capacitance.
6
pF
1
Clk Stabilization
TSTAB
From VDD power-up and after input clock
stabilization or deassertion of PD# to 1st clock.
1
ms
1, 2
Input SS Modulation
Frequency PCIe
fMODINPCIe
Input SS Modulation
Frequency non-PCIe
Allowable frequency for PCIe applications
(Triangular modulation).
30
33
kHz
fMODIN
Allowable frequency for non-PCIe applications
(Triangular modulation).
0
66
kHz
OE# Latency
tLATOE#
DIF start after OE# assertion.
DIF stop after OE# deassertion.
1
3
clocks
1,3
Tdrive_PD#
tDRVPD
DIF output enable after PD# deassertion.
300
μs
1,3
Tfall
tF
Fall time of single-ended control inputs.
5
ns
2
Trise
tR
Rise time of single-ended control inputs.
5
ns
2
SMBus Input Low Voltage
VILSMB
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V.
0.8
V
4
SMBus Input High Voltage
VIHSMB
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V.
3.3
V
5
SMBus Output Low Voltage
VOLSMB
At I PULLUP.
0.4
V
SMBus Sink Current
IPULLUP
At V OL.
Nominal Bus Voltage
VDDSMB
SCLK/SDATA Rise Time
tRSMB
SCLK/SDATA Fall Time
SMBus Operating Frequency
1
2
3
4
5
6
7
2.1
4
1.7
mA
3.6
V
(Max VIL - 0.15V) to (Min VIH + 0.15V).
1000
ns
1
tFSMB
(Min VIH + 0.15V) to (Max VIL - 0.15V).
300
ns
1
fSMB
SMBus operating frequency.
400
kHz
7
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
Time from deassertion until outputs are > 200mV.
For VDDSMB < 3.3V, VILSMB < = 0.35VDDSMB.
For VDDSMB < 3.3V, VILSMB < = 0.65VDDSMB.
DIF_IN input.
The differential input clock must be running for the SMBus to be active.
©2020 Renesas Electronics Corporation
10
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 6. Current Consumption – 9DBV09x1
Parameter
Operating Supply
Current
Power Down
Current
1
Symbol
Typical
Maximum
Units
VDDR at 100MHz.
3
5
mA
VDDIG, all outputs at 100MHz.
6
10
mA
VDDO1.8 + V DDIO, all outputs at 100MHz.
35
40
mA
IDDRPD
VDDR, CKPWRGD_PD# = 0.
0.4
1
mA
1
IDDDIGPD
VDDIG, CKPWRGD_PD# = 0.
0.6
1
mA
1
0.002
0.1
mA
1
Typical
Maximum
Units
Notes
VDDR at 100MHz.
3
5
mA
VDDIG, all outputs at 100MHz.
5
8
mA
VDDO1.8 + V DDIO, all outputs at 100MHz.
26
32
mA
IDDRPD
VDDR, CKPWRGD_PD# = 0.
0.4
1
mA
1
IDDDIGPD
VDDIG, CKPWRGD_PD# = 0.
0.5
1
mA
1
0.0005
0.10
mA
1
Typical
Maximum
Units
Notes
2
3
mA
VDDIG, all outputs at 100MHz.
0.2
0.5
mA
VDDO1.8, all outputs at 100MHz.
23
27
mA
IDDR
IDDDIG
IDDO
IDDOPD
Conditions
Minimum
VDDO1.8 + V DDIO, CKPWRGD_PD# = 0.
Notes
Input clock stopped.
Table 7. Current Consumption – 9DBV07x1
Parameter
Operating Supply
Current
Power Down
Current
1
Symbol
IDDR
IDDDIG
IDDO
IDDOPD
Conditions
Minimum
VDDO1.8 + V DDIO, CKPWRGD_PD# = 0.
Input clock stopped.
Table 8. Current Consumption – 9DBV05x1
Parameter
Operating Supply
Current
Power Down
Current
1
Symbol
IDDR
IDDDIG
IDDO
Conditions
Minimum
VDDR at 100MHz.
IDDRPD
VDDR, CKPWRGD_PD# = 0.
0.001
0.1
mA
1
IDDDIGPD
VDDIG, CKPWRGD_PD# = 0.
0.2
0.3
mA
1
VDDO1.8, CKPWRGD_PD# = 0.
0.4
0.8
mA
1
IDDOPD
Input clock stopped.
©2020 Renesas Electronics Corporation
11
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 9. Output Duty Cycle, Jitter, Skew and PLL Characteristics
Parameter
Symbol
Duty Cycle Distortion
tDCD
Skew, Input to Output
tpdBYP
VT = 50%.
Skew, Output to Output
tsk3
Jitter, Cycle to Cycle
tjcyc-cyc
1
2
3
4
Conditions
Minimum Typical Maximum Units
Measured differentially at 100MHz.
Notes
-1
0
1
%
1,3
1800
2421
3000
ps
1
VT = 50%.
29
60
ps
1, 4
Additive jitter.
1.1
5
ps
1,2
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform.
Duty cycle distortion is the difference in duty cycle between the output and the input clock
All outputs at default slew rate.
Table 10. LP-HCSL Outputs
Parameter
Slew Rate
Symbol
dV/dt
Conditions
Minimum
Typical
Maximum
Scope averaging on, fast slew
rate setting.
1.6
2.9
4.3
Scope averaging on, slow slew
rate setting.
1.2
Slew Rate Matching
ΔdV/dt
Single-ended measurement.
Maximum Voltage
Vmax
Minimum Voltage
Vmin
Measurement on single-ended
signal using absolute value
(scope averaging off).
Crossing Voltage (abs)
Crossing Voltage (var)
1
2
Δ-Vcross
V/ns
1,2,3
V/ns
1,2,3
%
1,4,7
1–4
2.0
3.3
6
18
20
694
804
976.8
660–1150
-108
-18
303
405
507
250–550
mV
1,5,7
12
50
140
mV
1,6,7
Scope averaging off.
-300
mV
7,8
7,8
Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33Ω for Zo = 50Ω (100Ω differential trace
impedance)
Measured from differential waveform.
3 Slew
4
Vcross_abs Scope averaging off.
Specification
Units Notes
Limits
rate is measured through the Vswing voltage range centered around differential 0 V. This results in a ±150mV window around differential 0V.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use
for the edge rate calculations.
5 Vcross
6
7
8
is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock
rising and Clock# falling).
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed.
The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
At default SMBus settings. 660mV VHIGH is the minimum when VDDIO is >= 1.05V ±5%. If VDDIO is < 1.05V ±5%, the minimum VHIGH will be
VDDIOmin - 250mV. For example, for VDDIO = 0.9V ±5%, VHIGHmin will be 860mV - 250mV = 610mV.
Includes previously separate values of +300mV overshoot and -300mV of undershoot.
©2020 Renesas Electronics Corporation
12
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 11. Additive PCIe Phase Jitter for Fanout Buffer Mode
Parameter
Symbol
tjphPCIeG1-CC
Conditions
Minimum Typical Maximum Limits
Notes
1.7
3.0
86
ps (p-p)
1,2
PCIe Gen 2 Hi Band (5.0 GT/s)
0.033
0.049
3
ps (RMS)
1,2
PCIe Gen 2 Lo Band (5.0 GT/s)
0.122
0.199
3.1
ps (RMS)
1,2
tjphPCIeG3-CC
PCIe Gen 3 (8.0 GT/s)
0.059
0.098
1
ps (RMS)
1,2
tjphPCIeG4-CC
PCIe Gen 4 (16.0 GT/s)
0.059
0.098
0.5
ps (RMS) 1,2,3,4
tjphPCIeG5-CC
PCIe Gen 5 (32.0 GT/s)
0.023
0.038
0.15
ps (RMS) 1,2,3,5
0.175
0.275
ps (RMS)
1,2,6
Additive PCIe Phase Jitter, tjphPCIeG2-SRIS PCIe Gen 2 (5.0 GT/s)
Fanout Buffer Mode7
tjphPCIeG3-SRIS PCIe Gen 3 (8.0 GT/s)
(SRIS Architecture)
tjphPCIeG4-SRIS PCIe Gen 4 (16.0 GT/s)
0.156
0.247
ps (RMS)
1,2,6
0.041
0.064
ps (RMS)
1,2,6
0.043
0.066
ps (RMS)
1,2,6
tjphPCIeG5-SRIS PCIe Gen 5 (32.0 GT/s)
0.036
0.059
ps (RMS)
1,2,6
Additive PCIe Phase Jitter,
Fanout Buffer Mode7
(Common Clocked
Architecture)
tjphPCIeG2-CC
PCIe Gen 1 (2.5 GT/s)
Units
tjphPCIeG1-SRIS PCIe Gen 1 (2.5 GT/s)
N/A
1 The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section
2
3
4
5
6
7
of the data sheet for the exact measurement setup. The total Ref Clk jitter limits for each data rate are listed for convenience. The worst case results
for each data rate are summarized in this table. If oscilloscope data is used, equipment noise is removed from all results.
Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate
of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for
RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding
the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency.
For PNA measurements for the 2.5 GT/s data rate, the RMS jitter is converted to peak-to-peak jitter using a multiplication factor of 8.83. In the case
where real-time oscilloscope and PNA measurements have both been done and produce different results, the RTO result must be used.
SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2 MHz taking care to minimize removal of any non-SSC
content.
Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
The PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, however, it does not provide
specification limits, hence the n/a in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must be
twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by √2. An
additional consideration is the value for which to divide by √2. The conservative approach is to divide the ref clock jitter limit, and the case can be
made for dividing the channel simulation values by √2, if the ref clock is close to the Tx clock input. An example for Gen4 is as follows. A
“rule-of-thumb” SRIS limit would be either 0.5ps RMS/√2 = 0.35ps RMS if the clock chip is far from the clock input, or 0.7ps RMS/√2 = 0.5ps RMS
if the clock chip is near the clock input.
Additive jitter for RMS values is calculated by solving for “b” where b = √(c2 - a2) and “a” is rms input jitter and “c” is rms output jitter.
©2020 Renesas Electronics Corporation
13
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 12. Phase Jitter Parameters – 12kHz to 20MHz
Parameter
Symbol
Conditions
12kHz–20MHz
Additive Phase Jitter,
Fanout Buffer Mode
tjph12k-20MFOB
Fanout Buffer Mode,
SSC OFF, 100MHz
1
2
3
Minimum
Typical
Maximum
Specification
Limits
156
N/A
Units
Notes
fs (RMS) 1,2,3
Applies to all differential outputs, guaranteed by design and characterization. See Test Loads for measurement setup details.
12kHz to 20MHz brick wall filter.
For RMS values, additive jitter is calculated by solving for “b” where b = √(c2 - a2), “a” is rms input jitter and “c” is rms total jitter.
Power Management
Table 13. Power Management
CKPWRGD_PD#
CLK_IN
SMBus EN bit
OE[x]# Pin
DIF[x]
0
X
X
X
Low/Low
1
Running
0
X
Low/Low
1
Running
1
0
Low/Low
1
Running
1
1
Running
Test Loads
Figure 4. Test Load for AC/DC Measurements
CL
CK+
CKIN+
Clock Source
L
CK+
Zo (differential)
DUT
CK-
CKIN-
Test
Points for High
Impedance
Probe
CK-
CL
Table 14. Parameters for AC/DC Measurements
Clock Source
Device Under Test (DUT)
Rs (Ω)
Differential Zo (Ω)
L (cm)
CL (pF)
SMA100B
9DBVxx3x
33 External
100
12.7
2
SMA100B
9DBVxx3x
24 External
85
12.7
2
SMA100B
9DBVxx4x
Internal
100
12.7
2
©2020 Renesas Electronics Corporation
14
Parameters Measured
AC/DC parameters
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Figure 5. Test Load for Phase Jitter Measurements using Phase Noise Analyzer
PNA
Coax
Cables
L
CK+
CKIN+
Clock Source
CK+
Zo (differential)
DUT
CK-
CKIN-
Balun
0.1uF
CK-
50
SMA
Connectors
Table 15. Parameters for Phase Jitter Measurements using Phase Noise Analyzer
Clock Source
Device Under Test (DUT)
Rs (Ω)
Differential Zo (Ω)
L (cm)
CL (pF)
SMA100B
9DBVxx3x
33 External
100
12.7
2
SMA100B
9DBVxx3x
24 External
85
12.7
2
SMA100B
9DBVxx4x
Internal
100
12.7
2
©2020 Renesas Electronics Corporation
15
Parameters Measured
PCIe
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
General SMBus Serial Interface Information
How to Write
How to Read
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
Controller (host) sends a start bit
Controller (host) sends the write address
Renesas clock will acknowledge
Controller (host) sends the beginning byte location = N
Renesas clock will acknowledge
Controller (host) sends the byte count = X
Renesas clock will acknowledge
Controller (host) starts sending Byte N through Byte N+X-1
Renesas clock will acknowledge each byte one at a time
Controller (host) sends a stop bit
Index Block Write Operation
Controller (Host)
T
Renesas (Slave/Receiver)
Controller (host) will send a start bit
Controller (host) sends the write address
Renesas clock will acknowledge
Controller (host) sends the beginning byte location = N
Renesas clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
Renesas clock will acknowledge
Renesas clock will send the data byte count = X
Renesas clock sends Byte N+X-1
Renesas clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
▪ Controller (host) will need to acknowledge each byte
▪ Controller (host) will send a not acknowledge bit
▪ Controller (host) will send a stop bit
starT bit
Slave Address
WR
WRite
ACK
Index Block Read Operation
Beginning Byte = N
ACK
T
Data Byte Count = X
ACK
WR
Beginning Byte N
Renesas
ACK
ACK
X Byte
O
O
O
Controller (Host)
starT bit
Slave Address
WRite
Beginning Byte = N
ACK
O
O
O
RT
RD
Byte N + X - 1
Repeat starT
Slave Address
ReaD
ACK
ACK
P
stoP bit
Data Byte Count=X
ACK
Beginning Byte N
O
O
O
X Byte
ACK
O
O
O
Byte N + X - 1
N
P
©2020 Renesas Electronics Corporation
16
Not acknowledge
stoP bit
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 16. SMBus Address Selection
State of SADR_tri on first application of CKPWRGD_PD#
SADR
Address
+ Read/Write Bit
0
1101011
X
M
1101100
X
1
1101101
X
Table 17. Byte 0: Output Enable Register 1
Byte 0
Bit7
Bit6
Bit5
Bit4
Bit3
Control
Function
Output Enable
Type
R/W
0
Low/Low
1
OE# Pin Control
Bit2
Bit1
Bit0
9DBV09xx
Name
DIF7_en
DIF6_en
DIF5_en
DIF4_en
DIF3_en
DIF2_en
DIF1_en
DIF0_en
9DBV09xx
Default
1
1
1
1
1
1
1
1
9DBV07xx
Name
DIF5_en
DIF4_en
Reserved
DIF3_en
DIF2_en
DIF1_en
Reserved
DIF0_en
9DBV07xx
Default
1
1
1
1
1
1
1
1
9DBV05xx
Name
Reserved
DIF3_en
DIF2_en
Reserved
DIF1_en
Reserved
DIF0_en
Reserved
9DBV05xx
Default
1
1
1
1
1
1
1
1
©2020 Renesas Electronics Corporation
17
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 18. Byte 1: Output and Amplitude Control Register
Byte 1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Control
Function
Output _enable
Type
RW
RW
RW
0
Low/Low
00 = 0.6V
01 = 0.7V
1
OE# Pin Control
10= 0.8V
11 = 0.9V
9DBV09xx
Name
DIF8_en
Amplitude(1)
Default is 1
Amplitude(0)
Default is 0
Bit2
Bit1
Bit0
9DBV09xx
Default
9DBV07xx
Name
Reserved
Default is 0
Reserved
Default is 1
1
Controls Output Amplitude
Reserved
Default is 1
Reserved
Default is 1
Reserved
Default is 0
DIF6_en
9DBV07xx
Default
1
9DBV05xx
Name
DIF4_en
9DBV05xx
Default
1
Table 19. Byte 2: Slew Rate Control Register
Byte 2
Bit7
Bit6
Bit5
Bit4
Bit3
Control
Function
Slew Rate Adjustment
Type
RW
0
Slow Setting
1
Fast Setting
9DBV09xx
Name
Slewrate DIF7
Slewrate DIF6
Slewrate DIF5
Slewrate DIF4
Slewrate DIF3
Slewrate DIF2
Slewrate DIF1
Slewrate DIF0
9DBV09xx
Default
1
1
1
1
1
1
1
1
9DBV07xx
Name
Slewrate DIF5
Slewrate DIF4
Reserved
Slewrate DIF3
Slewrate DIF2
Slewrate DIF1
Reserved
Slewrate DIF0
9DBV07xx
Default
1
1
1
1
1
1
1
1
9DBV05xx
Name
Reserved
Slewrate DIF3
Slewrate DIF2
Reserved
Slewrate DIF1
Reserved
Slewrate DIF0
Reserved
9DBV05xx
Default
1
1
1
1
1
1
1
1
©2020 Renesas Electronics Corporation
18
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 20. Byte 3: Slew Rate Control Register
Byte 3
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Control
Function
Slew Rate
Adjustment
Type
RW
0
Slow Setting
1
Fast Setting
9DBV09xx
Name
Slewrate DIF8
9DBV09xx
Default
9DBV07xx
Name
Reserved
Default is 1
Reserved
Default is 1
Reserved
Default is 0
Reserved
Default is 0
Reserved
Default is 0
Reserved
Default is 1
Reserved
Default is 1
1
Slewrate DIF6
9DBV07xx
Default
1
9DBV05xx
Name
Slewrate DIF4
9DBV05xx
Default
1
Byte 4: Reserved Register – default is 0hFF
Table 21. Byte 5: Revision and Vendor ID Register
Byte 5
Bit7
Bit6
Control
Function
Type
Bit5
Bit4
Bit3
Bit2
Revision ID
R
R
R
R
A rev = 0010
1
Bit0
R
R
Vendor ID
R
0
Bit1
R
IDT/Renesas = 0001
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Default
0
0
0
0
0
0
0
1
©2020 Renesas Electronics Corporation
19
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Table 22. Byte 6: Device ID Register
Byte 6
Bit7
Control
Function
Type
0
1
Name
Bit6
Bit5
Bit4
Bit3
Device Type
R
Bit1
Bit0
R
R
R
DevID 2
DevID 1
DevID 0
Bit2
Bit1
Device ID
R
R
R
R
00 = FG, 01 = ZDB
10 = Mux, 11 = Fanout Buffer
Device Type 1
Bit2
Device Type 0
Device ID
DevID 5
DevID 4
DevID 3
9DBV09xx
0hC9
9DBV07xx
0hC7
9DBV05xx
0hC5
Table 23. Byte 7: Byte Count Register
Byte 7
Bit7
Bit6
Bit5
Control
Function
Type
0
Bit4
Bit3
Writing to this register configures how many bytes will be read back on a block read.
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
Default value is 0b01000
1
Name
Default
Bit0
0
0
©2020 Renesas Electronics Corporation
0
BC4
BC3
BC2
BC1
BC0
0
1
0
0
0
20
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information
is the most current data available.
9DBV05x1:
www.idt.com/document/psc/32-vfqfpn-package-outline-drawing-50-x-50-x-090-mm-body-epad-315-x-315-mm-nlg32p1
9DBV07x1:
www.idt.com/document/psc/ndndg40-package-outline-50-x-50-mm-bodyepad-350mm-sq-040-mm-pitch-qfn
9DBV09x1:
www.idt.com/document/psc/48-vfqfpn-package-outline-drawing-60-x-60-x-090-mm-body-epad-41-x-41-mm-040mm-pitch-ndg48p1
Marking Diagrams
9DBV05x1
▪ Lines 1 and 2: truncated part number (“I”
denotes industrial temperature range)
▪ Line 3: “YYWW” is the last two digits of the
year and the work week the part was
assembled.
▪ Line 4: “COO” denotes country of origin.
▪ Line 5: “LOT” denotes the lot number.
©2020 Renesas Electronics Corporation
21
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
9DBV07x1
▪ Lines 1 and 2: truncated part number (“I”
denotes industrial temperature range)
▪ Line 3: “YYWW” is the last two digits of the
year and the work week the part was
assembled.
▪ Line 4: “COO” denotes country of origin.
▪ Line 5: “LOT” denotes the lot number.
9DBV09x1
▪ Lines 1 and 2: truncated part number (“I”
denotes industrial temperature range)
▪ Line 3: “YYWW” is the last two digits of the
year and the work week the part was
assembled.
▪ Line 4: “COO” denotes country of origin.
▪ Line 5: “LOT” denotes the lot number.
©2020 Renesas Electronics Corporation
22
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Ordering Information
Table 24. Ordering Information
Number of
Output
Clock Outputs Impedance
Orderable Part
Number
Temperature
Range
Package
Part Number Suffix and Shipping Method
9DBV0531AKILF
33
9DBV0531AKILFT
5
100
9DBV0541AKILF
5 × 5 × 0.5 mm
32-VFQFPN
9DBV0541AKILFT
9DBV0731AKILF
33
9DBV0731AKILFT
7
100
9DBV0741AKILF
None = Trays
5 × 5 × 0.4 mm
40-VFQFPN
-40°C to +85°C
“T” = Tape and Reel, Pin 1 Orientation: EIA-481C
(see Table 25 for more details)
9DBV0741AKILFT
9DBV0931AKILF
33
9DBV0931AKILFT
9
100
9DBV0941AKILF
6 × 6 × 0.4 mm
48-VFQFPN
9DBV0941AKILFT
9DBV0531AKLF
33
9DBV0531AKLFT
5
100
9DBV0541AKLF
5 × 5 × 0.5 mm
32-VFQFPN
9DBV0541AKLFT
9DBV0731AKLF
33
9DBV0731AKLFT
7
100
9DBV0741AKLF
None = Trays
5 × 5 × 0.4 mm
40-VFQFPN
0°C to +70°C
9DBV0741AKLFT
“T” = Tape and Reel, Pin 1 Orientation: EIA-481C
(see Table 25 for more details)
9DBV0931AKLF
33
9DBV0931AKLFT
9
100
9DBV0941AKLF
6 × 6 × 0.4 mm
48-VFQFPN
9DBV0941AKLFT
“A” is the device revision designator (will not correlate with the datasheet revision).
“LF” denotes Pb-free configuration, RoHS compliant; “T” denotes the orderable suffix for Tape and Reel.
Table 25. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
Correct Pin 1 ORIENTATION
T
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Quadrant 1 (EIA-481-C)
USER DIRECTION OF FEED
©2020 Renesas Electronics Corporation
23
June 30, 2020
9DBV05x1/9DBV07x1/9DBV09x1 Datasheet
Revision History
Revision Date
June 30, 2020
Description of Change
▪ Merged duplicate pin names in table 1 into single rows and combined pin numbers into a single row for the
duplicate pin names. Rows merged were VDDIO, VDDO1.8, and GND.
▪ Removed duplicate table subtitle “TA = TCOM or TIND. Supply voltages per normal operation conditions;
see Test Loads for loading conditions” from Tables 10, 11 and 12. This phrase is at the beginning of
the Electrical Characteristics section and applies to all electrical tables.
▪ Corrected PCIe SRIS maximum values in Table 11. They were shifted down by one cell.
February 13, 2020
▪ Corrected 9DBV05xx pin number typos in pin description table.
▪ Rebranded datasheet.
October 22, 2019
Combined 9DBV0531_0541, 9DBV0731_741, and 9DBV0931_941 datasheets into one single document.
March 10, 2017
Last revision date of the 9DBV0531 datasheet.
May 30, 2017
Last revision date of the 9DBV0541 datasheet.
March 10, 2017
Last revision date of the 9DBV0731 datasheet.
March 10, 2017
Last revision date of the 9DBV0741 datasheet.
March 14, 2017
Last revision date of the 9DBV0931 datasheet.
March 14, 2017
Last revision date of the 9DBV0941 datasheet.
©2020 Renesas Electronics Corporation
24
June 30, 2020
32-VFQFPN, Package Outline Drawing
5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm.
NLG32P1, PSC-4171-01, Rev 02, Page 1
32-VFQFPN, Package Outline Drawing
5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm.
NLG32P1, PSC-4171-01, Rev 02, Page 2
Package Revision History
Description
Date Created
Rev No.
April 12, 2018
Rev 02
New Format
Feb 8, 2016
Rev 01
Added "k: Value
48-VFQFPN Package Outline Drawing
6.0 x 6.0 x 0.90 mm Body, Epad 4.1x 4.1 mm, 0.40mm Pitch
NDG48P1, PSC-4212-01, Rev 01, Page 1
© Integrated Device Technology, Inc.
48-VFQFPN Package Outline Drawing
6.0 x 6.0 x 0.90 mm Body, Epad 4.1 x 4.1 mm, 0.40mm Pitch
NDG48P1, PSC-4212-01, Rev 01, Page 2
Package Revision History
© Integrated Device Technology, Inc.
Description
Date Created
Rev No.
Aug16, 2018
Rev 01 New Format Change QFN to VFQFPN, Recalculate Land Pattern
May 6, 2016
Rev 00 Add Chamfer
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.
工商网监
湘ICP备2023018690号
