2:12 DB1200ZL Derivative for
PCIe Gen1-4 and UPI
9ZML1233E / 9ZML1253E
Datasheet
Description
Features
The 9ZML1233E / 9ZML1253E are second generation enhanced
performance DB1200ZL derivatives. The parts are pin-compatible
upgrades to the 9ZML1232B, while offering much improved phase
jitter performance. A fixed external feedback maintains low drift for
critical QPI/UPI applications, while each input channel has software
adjustable input-to-output delay to ease transport delay
management for today's more complex server topologies. The
9ZML1233E and 9ZML1253E have an SMBus Write Lockout pin for
increased device and system security.
▪ SMBus write lock feature; increases system security
▪ 2 software-configurable input-to-output delay lines; manage
transport delay for complex topologies
▪ LP-HCSL outputs; eliminate 24 resistors, save 41mm2 of area
(1233E)
▪ LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save
82mm2 of area (1253E)
▪ 12 OE# pins; hardware control of each output
▪ 3 selectable SMBus addresses; multiple devices can share same
SMBus segment
▪ Selectable PLL bandwidths; minimizes jitter peaking in cascaded
PLL topologies
▪ Hardware/SMBus control of PLL bandwidth and bypass; change
mode without power cycle
▪ Spread spectrum compatible; tracks spreading input clock for EMI
reduction
▪ 100MHz PLL Mode; UPI support
▪ 10 x 10 mm 72-VFQFPN package; small board footprint
PCIe Clocking Architectures
Supported
▪ Common Clocked (CC)
▪ Independent Reference (IR) with and without spread spectrum
Typical Applications
▪
▪
▪
▪
Servers
Storage
Networking
SSDs
Key Specifications
▪
▪
▪
▪
▪
▪
▪
Output Features
▪ 12 Low-Power (LP) HCSL output pairs (1233E)
▪ 12 Low-Power (LP) HCSL output pairs with 85Ω Zout (1253E)
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50ps
Input-to-output delay: 0ps default
Input-to-output delay variation < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: UPI > 9.6GB/s < 0.1ps rms
Phase jitter: IF-UPI < 1.0ps rms
Block Diagram
I2O
Delay
^SEL_A_B#
DIF_INA
DIF_INA
FBOUT_NC
Low Phase Noise
Z-PLL
(SS-Compatible)
FBOUT_NC
DIF_11
DIF_11
Bypass path
12
outputs
DIF_INB
DIF_INB
CKPWRGD_PD#
vSMB_A0_tri
vSMB_WRTLOCK
SMBDAT
SMBCLK
CONTROL
^vHIBW_BYPM_LOBW#
DIF_0
NOTE: Internal series resistors are only
present on the 9ZML1253
DIF_0
^OE(11:0)#
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9ZML1233E / 9ZML1253E Datasheet
^OE8#
^OE9#
NC
GND
DIF_8
DIF_8#
DIF_9
DIF_9#
GND
VDD
DIF_10
DIF_10#
DIF_11
DIF_11#
NC
GND
^OE10#
^OE11#
Pin Assignments
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
54 ^OE7#
53 ^OE6#
VDDA 1
GNDA 2
52 VDDIO
51 GND
50 DIF_7#
^SEL_A_B# 3
^vHIBW_BYPM_LOBW# 4
CKPWRGD_PD# 5
49 DIF_7
48 DIF_6#
DIF_INB 6
DIF_INB# 7
GND 8
47 DIF_6
46 GND
9ZML1233
9ZML1253
Connect EPAD to GND
VDDR 9
DIF_INA 10
DIF_INA# 11
45 VDD
44 DIF_5#
43 DIF_5
42 DIF_4#
vSADR0_tri 12
SMBDAT 13
41 DIF_4
40 VDDIO
SMBCLK 14
vSMB_WRTLOCK 15
39 GND
38 ^OE5#
NC 16
FBOUT_NC# 17
37 ^OE4#
FBOUT_NC 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
^OE3#
^OE2#
GND
NC
DIF_3#
DIF_3
DIF_2#
DIF_2
VDD
GND
DIF_1#
DIF_1
DIF_0#
DIF_0
GND
NC
^OE1#
^OE0#
^ prefix indicates internal 120kohm pull-up
v prefix indicates internal 120kohm pull-down
10 x 10 mm 72-VFQFPN 0.5mm pin pitch
Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Type
Description
1
VDDA
Power
Power supply for PLL core.
2
GNDA
GND
Ground pin for the PLL core.
Input
Input to select differential input clock A or differential input clock B. This input has an
internal 120kΩ pull-up resistor.
3
^SEL_A_B#
0 = input B selected, 1 = input A selected.
Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2
Latched
(Bypass Mode) with internal pull-up/pull-down resistors. See PLL Operating Mode
In
table for details.
4
^vHIBW_BYPM_LOBW#
5
CKPWRGD_PD#
Input
3.3V input notifies device to sample latched inputs and start up on first high assertion,
or exit Power Down Mode on subsequent assertions. Low enters Power Down Mode.
6
DIF_INB
Input
True input of differential clock.
7
DIF_INB#
Input
Complement input of differential clock.
8
GND
GND
Ground pin.
9
VDDR
Power
Power supply for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately. Nominally 3.3V.
10
DIF_INA
Input
True input of differential clock.
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9ZML1233E / 9ZML1253E Datasheet
Table 1. Pin Descriptions (Cont.)
Number
11
Name
DIF_INA#
Type
Description
Input
Complement input of differential clock.
Input
SMBus address bit. This is a tri-level input that works in conjunction with other SADR
pins, if present, to decode SMBus Addresses. It has an internal 120kΩ pull-down
resistor. See the SMBus Addressing table.
12
vSADR0_tri
13
SMBDAT
I/O
Data pin of SMBUS circuitry.
14
SMBCLK
Input
Clock pin of SMBUS circuitry.
Input
This pin prevents SMBus writes when asserted. SMBus reads are not affected. This
pin has an internal 120kΩ pull-down.
0 = SMBus writes allows, 1 = SMBus writes blocked.
15
vSMB_WRTLOCK
16
NC
—
No connection.
17
FBOUT_NC#
Output
Complementary half of differential feedback output. This pin should NOT be connected
to anything outside the chip. It exists to provide delay path matching to get 0
propagation delay.
18
FBOUT_NC
Output
True half of differential feedback output. This pin should NOT be connected to anything
outside the chip. It exists to provide delay path matching to get 0 propagation delay.
19
^OE0#
Input
Active low input for enabling output 0. This pin has an internal 120kΩ pull-up resistor.
1 = disable outputs, 0 = enable outputs.
20
^OE1#
Input
21
NC
22
GND
GND
23
DIF_0
Output
HCSL true clock output.
24
DIF_0#
Output
HCSL complementary clock output.
25
DIF_1
Output
HCSL true clock output.
26
DIF_1#
Output
HCSL complementary clock output.
27
GND
GND
Ground pin.
28
VDD
Power
Power supply, nominally 3.3V.
29
DIF_2
Output
HCSL true clock output.
30
DIF_2#
Output
HCSL complementary clock output.
31
DIF_3
Output
HCSL true clock output.
32
DIF_3#
Output
HCSL complementary clock output.
33
NC
34
GND
GND
35
^OE2#
Input
36
^OE3#
Input
—
—
©2017 Integrated Device Technology, Inc.
Active low input for enabling output 1. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
No connection.
Ground pin.
No connection.
Ground pin.
Active low input for enabling output 2. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 3. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
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December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Table 1. Pin Descriptions (Cont.)
Number
Name
Type
Description
Active low input for enabling output 4. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
37
^OE4#
Input
38
^OE5#
Input
39
GND
GND
Ground pin.
40
VDDIO
Power
Power supply for differential outputs.
41
DIF_4
Output
HCSL true clock output.
42
DIF_4#
Output
HCSL complementary clock output.
43
DIF_5
Output
HCSL true clock output.
44
DIF_5#
Output
HCSL complementary clock output.
45
VDD
PWR
Power supply, nominally 3.3V.
46
GND
GND
Ground pin.
47
DIF_6
Output
HCSL true clock output.
48
DIF_6#
Output
HCSL complementary clock output.
49
DIF_7
Output
HCSL true clock output.
50
DIF_7#
Output
HCSL complementary clock output.
51
GND
GND
Ground pin.
52
VDDIO
Power
Power supply for differential outputs.
53
^OE6#
Input
54
^OE7#
Input
55
^OE8#
Input
56
^OE9#
Input
57
NC
58
GND
GND
59
DIF_8
Output
HCSL true clock output.
60
DIF_8#
Output
HCSL complementary clock output.
61
DIF_9
Output
HCSL true clock output.
62
DIF_9#
Output
HCSL complementary clock output.
63
GND
GND
Ground pin.
64
VDD
Power
Power supply, nominally 3.3V.
65
DIF_10
Output
HCSL true clock output.
—
©2017 Integrated Device Technology, Inc.
Active low input for enabling output 5. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 6. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 7. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 8. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Active low input for enabling output 9. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
No connection.
Ground pin.
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December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Table 1. Pin Descriptions (Cont.)
Number
Name
Type
Description
66
DIF_10#
Output
HCSL complementary clock output.
67
DIF_11
Output
HCSL true clock output.
68
DIF_11#
Output
HCSL complementary clock output.
69
NC
70
GND
GND
Ground pin.
71
^OE10#
Input
Active low input for enabling output 10. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
72
^OE11#
Input
73
EPAD
GND
—
No connection.
Active low input for enabling output 11. This pin has an internal pull-up resistor.
1 = disable outputs, 0 = enable outputs.
Connect to ground.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZML1233E / 9ZML1253E. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Supply Voltage
VDDx
Input Low Voltage
VIL
Input High Voltage
VIH
Except for SMBus interface.
VDD + 0.5
Input High Voltage
VIHSMB
SMBus clock and data pins.
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD Protection
ESD prot
Conditions
Minimum
Typical
Maximum
Units
Notes
4.6
V
1,2
V
1
V
1,3
5.5
V
1
150
°
C
1
125
°C
1
V
1
GND-0.5
-65
Human Body Model.
2000
1 Guaranteed
by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 4.6V.
2
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9ZML1233E / 9ZML1253E Datasheet
Electrical Characteristics
Over specified temperature and voltage ranges unless otherwise indicated; see Test Loads for loading conditions.
Table 3. SMBus Parameters
Parameter
Symbol
Conditions
SMBus Input Low Voltage
VILSMB
SMBus Input High Voltage
VIHSMB
SMBus Output Low Voltage
VOLSMB
At IPULLUP.
SMBus Sink Current
IPULLUP
At VOL.
Nominal Bus Voltage
VDDSMB
SCLK/SDATA Rise Time
tRSMB
SCLK/SDATA Fall Time
SMBus Operating Frequency
Minimum
Typical
2.1
Maximum
Units
0.8
V
VDDSMB
V
0.4
V
4
Notes
mA
2.7
3.6
V
1
(Max VIL - 0.15V) to (Min VIH + 0.15V).
1000
ns
1
tFSMB
(Min VIH + 0.15V) to (Max VIL - 0.15V).
300
ns
1
fMAXMB
Maximum SMBus operating frequency.
400
kHz
5
Maximum
Units
Notes
900
mV
1
mV
1
1,2
1
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are > 200mV.
4 DIF_IN input.
5 The differential input clock must be running for the SMBus to be active.
2
Table 4. DIF_IN Clock Input Parameters
1
2
Parameter
Symbol
Conditions
Minimum
Typical
Input Crossover Voltage
VCROSS
Cross over voltage.
150
Input Swing – DIF_IN
VSWING
Differential value.
300
Input Slew Rate – DIF_IN
dv/dt
Measured differentially.
0.35
8
V/ns
Input Leakage Current
IIN
VIN = VDD , VIN = GND.
-5
5
μA
Input Duty Cycle
dtin
Measurement from differential
waveform.
45
55
%
1
Input Jitter –Cycle to Cycle
JDIFIn
Differential measurement.
0
125
ps
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through ±75mV window centered around differential zero.
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9ZML1233E / 9ZML1253E Datasheet
Table 5. Input/Supply/Common Parameters
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
Units
Notes
VDDx
Supply voltage for core and analog.
3.135
3.3
3.465
V
VDDIO
Supply voltage for differential outputs.
3.135
3.3
3.465
V
Ambient Operating
Temperature
TAMB
Industrial range.
-40
85
°C
Input High Voltage
VIH
Single-ended inputs, except SMBus, tri-level
inputs.
2
VDD + 0.3
V
Input Low Voltage
VIL
Single-ended inputs, except SMBus, tri-level
inputs.
GND - 0.3
0.8
V
Input High Voltage
VIH
Tri-level inputs (“_tri” suffix).
2.2
VDD + 0.3
V
Input Mid Voltage
VIM
Tri-level inputs (“_tri” suffix).
1.2
1.8
V
Input Low Voltage
VIL
Tri-level inputs (“_tri” suffix).
GND - 0.3
0.8
V
IIN
Single-ended inputs, VIN = GND, VIN = VDDx.
-5
5
μA
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors.
VIN = VDD; Inputs with internal pull-down
resistors.
-100
100
μA
1
400
MHz
102
MHz
5
7
nH
1
Supply Voltage
Input Current
Input Frequency
Pin Inductance
FIBYP
VDD = 3.3V, Bypass Mode.
FIPLL
VDD = 3.3V, 100MHz PLL Mode.
100.00
Lpin
CIN
Capacitance
98.5
VDD/2
CINDIF_IN
Logic Inputs, except DIF_IN.
1.5
5
pF
1
DIF_IN differential clock inputs.
1.5
2.7
pF
1,4
6
pF
1
1.2
1.8
ms
1,2
COUT
Output pin capacitance.
Clk Stabilization
tSTAB
From VDD power-up and after input clock
stabilization or deassertion of PD# to 1st clock.
Input SS
Modulation
Frequency PCIe
fMODINPCIe
OE# Latency
Allowable frequency for PCIe applications
(triangular modulation).
30
31.6
33
kHz
tLATOE#
DIF start after OE# assertion.
DIF stop after OE# deassertion.
4
5
10
clocks
1,2,3
Tdrive_PD#
tDRVPD
DIF output enable after PD# deassertion.
85
300
μs
1,3
Tfall
tF
Fall time of control inputs.
5
ns
2
Trise
tR
Rise time of control inputs.
5
ns
2
1
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are > 200mV, PLL Mode.
4 DIF_IN input.
5 This parameter reflects the operating range after locking to a 100MHz input.
2
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9ZML1233E / 9ZML1253E Datasheet
Table 6. Current Consumption
Parameter
Operating Supply
Current
Power Down
Current
Symbol
Minimum
Typical
Maximum
Units
Notes
IDDx
All other VDD pins, all outputs at 100MHz,
CL = 2pF; Zo = 85Ω.
22
30
mA
IDDA+R
VDDA + VDDR pins, all outputs at 100MHz,
CL = 2pF; Zo = 85Ω.
56
65
mA
IDDO
VDDIO pins, all outputs at 100MHz, CL = 2pF;
Zo = 85Ω.
84
100
mA
IDDx
All other VDD pins, all outputs Low/Low.
0.9
2
mA
1
IDDA+R
VDDA + VDDR pins, all outputs Low/Low.
4.3
6
mA
1
VDDIO pins, all outputs Low/Low.
0.1
0.2
mA
1
IDDO
1
Conditions
1
Includes VDDR if applicable.
Table 7. Skew and Differential Jitter Parameters
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
Units
Notes
CLK_IN, DIF[x:0]
tSKEW_PLL
Input-to-output skew in PLL Mode at 100MHz,
nominal temperature and voltage.
-100
-4
100
ps
1,2,4,
5,6,8
CLK_IN, DIF[x:0]
tPD_BYP
Input-to-output skew in Bypass Mode at
100MHz, nominal temperature and voltage.
2.2
2.9
3.6
ns
1,2,3,
8
CLK_IN, DIF[x:0]
tDSPO_PLL
Input-to-output skew variation in PLL Mode at
100MHz, across voltage and temperature.
-50
0.0
50
ps
1,2,3,
8
Input-to-output skew variation in Bypass Mode
at 100MHz, across voltage and temperature,
TAMB = 0 to 70°C, default slew rate.
-250
0.0
250
ps
1,2,3,
8
Input-to-output skew variation in Bypass Mode
at 100MHz, across voltage and temperature,
TAMB = -40 to 85°C, default slew rate.
-350
0.0
350
ps
1,2,3,
8
30
50
ps
1,2,3,
8
CLK_IN, DIF[x:0]
tDSPO_BYP
DIF[x:0]
tSKEW_ALL
Output-to-output skew across all outputs,
common to PLL and Bypass Mode, at 100MHz,
default slew rate.
PLL Jitter Peaking
jpeak-hibw
LOBW#_BYPASS_HIBW = 1.
0
1.3
2.5
dB
7,8
PLL Jitter Peaking
jpeak-lobw
LOBW#_BYPASS_HIBW = 0.
0
1.3
2
dB
7,8
PLL Bandwidth
pllHIBW
LOBW#_BYPASS_HIBW = 1.
2
2.6
4
MHz
8,9
PLL Bandwidth
pllLOBW
LOBW#_BYPASS_HIBW = 0.
0.7
1.0
1.4
MHz
8,9
Duty Cycle
tDC
Measured differentially, PLL Mode.
45
50
55
%
1
Duty Cycle
Distortion
tDCD
Measured differentially, Bypass Mode at
100MHz.
-1
-0.2
0
%
1,10
Jitter, Cycle to Cycle
tjcyc-cyc
PLL Mode.
13
50
ps
1,11
Additive jitter in Bypass Mode.
0.2
5
ps
1,11
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9ZML1233E / 9ZML1253E Datasheet
1
Measured into fixed 2pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3 All Bypass Mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it.
4 This parameter is deterministic for a given device.
5 Measured with scope averaging on to find mean value.
6 This value is programmable.
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8 Guaranteed by design and characterization, not 100% tested in production.
9 Measured at 3db down or half power point.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in Bypass
Mode.
11 Measured from differential waveform.
2
Table 8. DIF HCSL/LP-HCSL Outputs
Parameter
Symbol
Slew Rate
dV/dt
Scope averaging on.
Slew Rate Matching
ΔdV/dt
Slew rate matching, scope
averaging on.
Maximum Voltage
VMAX
Minimum Voltage
VMIN
Crossing Voltage (abs)
Crossing Voltage (var)
Conditions
Measurement on
single-ended signal using
absolute value (scope
averaging off).
VCROSS_ABS Scope averaging off.
Δ-VCROSS
Scope averaging off.
Minimum
Typical
Maximum
Industry
Limits
Units
Notes
2.0
2.8
4.0
0.6 – 4.0
V/ns
1,2,3
4
15
20
%
1,2,4,
7
660
794
870
1150
-111
-49
302
367
453
250 – 550
mV
1,5,7
32
74
140
mV
1,6,7
-300
7,8
mV
7,8
1
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform.
3 Slew rate is measured through the V
SWING voltage range centered around differential 0 V. This results in a ±150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5V
CROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all V
CROSS measurements in any particular system. Note that this is a subset of VCROSS_MIN/MAX (VCROSS
absolute) allowed. The intent is to limit VCROSS induced modulation by setting Δ-VCROSS to be smaller than VCROSS absolute.
7 At default SMBus settings.
8 If driving a receiver with input terminations, the V
MAX and VMIN values will be halved.
2
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9ZML1233E / 9ZML1253E Datasheet
Table 9. Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures
Parameter
Industry
Limits
Units
Notes
30
86
ps
(p-p)
1, 2,
3, 6
0.25
0.7
3
ps
(rms)
1, 2, 6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
1.00
1.5
3.1
ps
(rms)
1, 2, 6
tjphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
0.24
0.35
1
ps
(rms)
1, 2, 6
tjphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
0.24
0.35
0.5
ps
(rms)
1, 2, 6
tjphPCIeG1-CC
PCIe Gen 1.
0.0
0.05
ps
(p-p)
1, 2,
3, 4, 6
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
0.00
0.05
ps
(rms)
1, 2,
3, 4, 6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
0.00
0.05
ps
(rms)
1, 2,
3, 4, 6
tjphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
0.00
0.05
ps
(rms)
1, 2,
3, 4, 6
tjphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
0.00
0.05
ps
(rms)
1, 2,
3, 4, 6
Symbol
Conditions
tjphPCIeG1-CC
PCIe Gen 1.
13
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
tjphPCIeG2-CC
Phase Jitter,
PLL Mode
tjphPCIeG2-CC
Additive
Phase Jitter,
Bypass Mode
©2017 Integrated Device Technology, Inc.
Minimum
10
Typical Maximum
Not
Applicable
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Table 10. Filtered Phase Jitter Parameters - PCIe Independent Reference (IR) Architectures
Parameter
Phase Jitter,
PLL Mode
Additive
Phase Jitter,
Bypass Mode
Industry
Limits
Units
Notes
1.2
2
ps
(rms)
1, 2, 5
0.64
0.68
0.7
ps
(rms)
1, 2, 5
PCIe Gen 2
(PLL BW of 16MHz, CDR = 5MHz).
0.00
0.02
ps
(rms)
2, 4, 5
PCIe Gen 3
(PLL BW of 2–4MHz, CDR =
10MHz).
0.00
ps
(rms)
2, 4, 5
Symbol
Conditions
Minimum
Typical Maximum
tjphPCIeG2-SRIS
PCIe Gen 2
(PLL BW of 16MHz, CDR = 5MHz).
0.8
tjphPCIeG3-SRIS
PCIe Gen 3
(PLL BW of 2–4MHz, CDR =
10MHz).
tjphPCIeG2-SRIS
tjphPCIeG3-SRIS
0.02
Not
Applicable
Notes for PCIe Filtered Phase Jitter tables:
1
Applies to all differential outputs when driven by 9SQL495x or equivalent, guaranteed by design and characterization.
Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent with spread on and off.
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1–12.
4
For RMS values, additive jitter is calculated by solving the following equation for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and
“c” is rms total jitter.
5
IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock
architectures. According to the PCIe Base Specification Rev4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter
limits are not defined for the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to
populate this table. There are no accepted filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates.
2
Table 11. Filtered Phase Jitter Parameters – QPI/UPI
Parameter
Phase Jitter,
PLL Mode
Typical
Maximum
Industry
Limits
QPI & UPI
(100MHz or 133MHz, 4.8Gb/s,
6.4Gb/s 12UI).
0.15
0.3
0.5
ps
(rms)
1, 2
QPI & UPI
(100MHz, 8.0Gb/s, 12UI).
0.08
0.1
0.3
ps
(rms)
1, 2
QPI & UPI
(100MHz, > 9.6Gb/s, 12UI).
0.07
0.1
0.2
ps
(rms)
1, 2
IF-UPI.
0.1
0.17
0.15
0.2
1
ps
(rms)
1, 4,
5
Symbol
tjphQPI_UPI
Conditions
tjphIF-UPI
©2017 Integrated Device Technology, Inc.
Minimum
11
Units Notes
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Table 11. Filtered Phase Jitter Parameters – QPI/UPI (Cont.)
Parameter
Additive
Phase Jitter,
Bypass Mode
Symbol
Conditions
Typical
Maximum
QPI & UPI
(100MHz or 133MHz, 4.8Gb/s,
6.4Gb/s 12UI).
0.00
0.03
QPI & UPI
(100MHz, 8.0Gb/s, 12UI).
0.02
0.07
QPI & UPI
(100MHz, > 9.6Gb/s, 12UI).
0.02
IF-UPI.
0.06
tjphQPI_UPI
tjphIF-UPI
Minimum
Industry
Limits
Units Notes
ps
(rms)
1, 2,
3
ps
(rms)
1, 2,
3
0.06
ps
(rms)
1, 2,
3
0.08
ps
(rms)
1, 4
Not
Applicable
1
Applies to all differential outputs, guaranteed by design and characterization.
Calculated from Intel-supplied clock jitter tool, when driven by 9SQL495x or equivalent with spread on and off.
3 Additive jitter for RMS values is calculated by solving for b [b = sqrt(c2 - a2)] where “a” is rms input jitter and “c” is rms total jitter.
4
Calculated from phase noise analyzer when driven by Wenzel Associates source with Intel-specified brick-wall filter applied.
5 Top number is when the buffer is in Low BW mode, bottom number is when the buffer is in High BW mode.
2
Table 12. Unfiltered Phase Jitter Parameters – 12kHz to 20MHz
Parameter
Symbol
Conditions
Phase Jitter, PLL
Mode
tjph12k-20MHi
Phase Jitter, PLL
Mode
Additive Phase
Jitter, Bypass Mode
Minimum
Typical
Maximum
PLL High BW, SSC Off,
100MHz.
171
250
tjph12k-20MLo
PLL Low BW, SSC Off,
100MHz.
183
250
tjph12k-20MByp
Bypass Mode, SSC Off,
100MHz.
109
150
Industry
Limits
Not
applicable
Units
Notes
fs
(rms)
1,2
fs
(rms)
1,2
fs
(rms)
1,2,3
1
Applies to all outputs when driven by Wenzel clock source.
12kHz to 20MHz brick wall filter.
3 For RMS values, additive jitter is calculated by solving for b [a^2 + b^2 = c^2] where “a” is rms input jitter and “c” is rms total jitter.
2
Power Management
Inputs
Control Bits
Outputs
PLL State
CKPWRGD_PD#
DIF_IN
SMBus EN bit
DIF_x
FBOUT_NC
0
X
X
Low/Low
Low/Low
Off
1
Running
0
Low/Low
Running
On
1
Running
Running
On
©2017 Integrated Device Technology, Inc.
12
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Power Connections (9ZML12xxE)
Pin Number
VDD
VDDIO
GND
Description
1
2
Analog PLL
9
8
Analog input
22, 27, 34, 39, 46, 51, 58, 63, 70
DIF clocks
28, 45, 64
40, 52
Power Connections (for pin-compatibility with 9ZML12xxB)
Pin Number
VDD
VDDIO
GND
Description
1
2
Analog PLL
9
8
Analog input
16, 22, 27, 34, 39, 46, 51, 58,
63, 70
DIF clocks
28, 45, 64
21, 33, 40, 52, 57, 69
PLL Operating Mode
HIBW_BYPM_LOBW#
Byte0[7:6]
Low (PLL Low BW)
00
Mid (Bypass)
01
High (PLL High BW)
11
Note: PLL is off in Bypass Mode.
Skew Programming
Skew[2:0]
Skew Steps
Skew (ps)
000
0
0
001
1
-416.67
010
2
-833.33
011
3
-1250.00
100
4
-1666.67
101
5
-2083.33
110
6
-2500.00
111
7
-2916.67
©2017 Integrated Device Technology, Inc.
13
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Figure 1. Skew Diagram
DIF_INx
tSKEW_PLL
DIF_n
Test Loads
Low-Power HCSL Output Test Load
(standard PCIe source -terminated test load )
Rs
L
CL
Test
Points
Differential Zo
CL
Rs
Table 13: Parameters for Low-Power HCSL Output Test Load
Device
Rs (Ω)
Zo (Ω)
L (inches)
CL (pF)
9ZML123x
27
85
12
2
9ZML123x
33
100
12
2
9ZML125x *
Internal
85
12
2
9ZML125x *
7.5
100
12
2
* Contact factory for versions of this device with Zo=100Ω.
Alternate Terminations
The LP-HCSL can easily drive other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's “Universal”
Low-Power HCSL Outputs” for details.
©2017 Integrated Device Technology, Inc.
14
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Clock Periods
Table 14: Clock Periods – Differential Outputs with Spread Spectrum Disabled
Measurement Window
SSC On
Center
Frequency
MHz
DIF
100.00
1 Clock
-c2cjitter
AbsPer
Minimum
1μs
0.1s
-SSC
-ppm
Short-Term Long-Term
Average
Average
Minimum
Minimum
—
9.94900
9.99900
0.1s
0.1s
1μs
1 Clock
0 ppm
Period
Nominal
+ppm
Long-Term
Average
Maximum
+SSC
Short-Ter
m Average
Maximum
+c2cjitter
AbsPer
Maximum
10.00000
10.00100
—
10.05100
Units
Notes
ns
1,2,3
Units
Notes
ns
1,2,3
Table 15: Clock Periods – Differential Outputs with Spread Spectrum Enabled
Measurement Window
SSC On
Center
Frequency
MHz
DIF
99.75
1 Clock
1μs
0.1s
0.1s
0.1s
1μs
1 Clock
-c2cjitter
AbsPer
Minimum
-SSC
Short-Term
Average
Minimum
-ppm
Long-Term
Average
Minimum
0 ppm
Period
Nominal
+ppm
Long-Term
Average
Maximum
+SSC
Short-Ter
m Average
Maximum
+c2cjitter
AbsPer
Maximum
9.94906
9.99906
10.02406
10.02506
10.02607
10.05107
10.10107
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy
requirements (+/-100ppm). The buffer itself does not contribute to ppm error.
3 Driven by SRC output of main clock, 100MHz PLL Mode or Bypass Mode.
2
©2017 Integrated Device Technology, Inc.
15
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
General SMBus Serial Interface Information
How to Write
How to Read
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a stop bit
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was written to
Byte 8)
▪ Controller (host) will need to acknowledge each byte
▪ Controller (host) will send a not acknowledge bit
▪ Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T
IDT (Slave/Receiver)
starT bit
Slave Address
WR
WRite
Index Block Read Operation
ACK
Controller (Host)
T
starT bit
Slave Address
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
IDT (Slave/Receiver)
ACK
Beginning Byte N
Beginning Byte = N
ACK
X Byte
O
O
O
ACK
RT
Repeat starT
Slave Address
RD
ReaD
O
O
O
Byte N + X - 1
ACK
ACK
P
stoP bit
Data Byte Count=X
ACK
Beginning Byte N
9ZML1233E / 9ZML1253E SMBus Addressing
SMBus Address (Read/Write bit = 0)
0
D8
M
DA
1
DE
O
O
O
O
O
O
Byte N + X - 1
N
P
©2017 Integrated Device Technology, Inc.
X Byte
SMB_A0_tri
ACK
16
Not acknowledge
stoP bit
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
SMBus Table: PLL Mode and Frequency Select Register
Byte 0
Name
Control Function
Type
Bit 7
PLL Mode bit [1]
PLL Operating Mode Rd back 1
R
Bit 6
PLL Mode bit [0]
PLL Operating Mode Rd back 0
R
Bit 5
SEL_A_B#
Input Select Readback
R
Bit 4
0
1
Default
See PLL Operating Mode table
DIF_INB
DIF_INA
Reserved
Latch
Real
0
Bit 3
PLL_InSEL_SW_EN
Enable S/W control of PLL BW and
Input select
RW
Bit 2
PLL Mode bit [1]
PLL Operating Mode 1
RW
Bit 1
PLL Mode bit [0]
PLL Operating Mode 1
RW
Bit 0
Latch
Pin Control
SMBus Control
See PLL Operating Mode table1
Reserved
0
1
1
1
Note: Changing the PLL operating mode between HiBW or LoBW and Bypass mode or between Bypass mode and HiBW or LoBW
requires a system reset. Changing the PLL operating mode between HiBW and LoBw or between LoBW and HiBW does not require a
system reset.
SMBus Table: Output Disable Register
Byte 1
Name
Control Function
Type
0
Bit 7
DIF_7_En
Output Control overrides OE# pin
RW
1
Bit 6
DIF_6_En
Output Control overrides OE# pin
RW
1
Bit 5
DIF_5_En
Output Control overrides OE# pin
RW
1
Bit 4
DIF_4_En
Output Control overrides OE# pin
RW
Bit 3
DIF_3_En
Output Control overrides OE# pin
RW
Bit 2
DIF_2_En
Output Control overrides OE# pin
RW
1
Bit 1
DIF_1_En
Output Control overrides OE# pin
RW
1
Bit 0
DIF_0_En
Output Control overrides OE# pin
RW
1
Low/Low
1
Default
Pin Control
1
1
SMBus Table: Output Control Register
Byte 2
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
Reserved
0
Bit 3
DIF_11_En
Output Control overrides OE# pin
RW
Bit 2
DIF_10_En
Output Control overrides OE# pin
RW
Bit 1
DIF_9_En
Output Control overrides OE# pin
RW
Bit 0
DIF_8_En
Output Control overrides OE# pin
RW
©2017 Integrated Device Technology, Inc.
17
1
Low/Low
Pin Control
1
1
1
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
SMBus Table: Reserved Register
Byte 3
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
Reserved
0
Bit 3
Reserved
0
Bit 2
Reserved
0
Bit 1
Reserved
0
Bit 0
Reserved
0
SMBus Table: Reserved Register
Byte 4
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
Reserved
0
Bit 3
Reserved
0
Bit 2
Reserved
0
Bit 1
Reserved
0
Bit 0
Reserved
0
SMBus Table: Vendor & Revision ID Register
Byte 5
Name
Bit 7
RID3
Bit 6
RID2
Bit 5
RID1
Bit 4
RID0
R
Bit 3
VID3
R
—
—
0
Bit 2
VID2
R
—
—
0
Bit 1
VID1
R
—
—
0
Bit 0
VID0
R
—
—
1
©2017 Integrated Device Technology, Inc.
Control Function
Type
0
1
R
0
R
REVISION ID
18
1
E rev = 0100
R
VENDOR ID
Default
0
0
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
SMBus Table: Device ID
Byte 6
Name
Control Function
Type
0
1
Default
Bit 7
Device ID 7 (MSB)
R
1
Bit 6
Device ID 6
R
1
Bit 5
Device ID 5
R
1
Bit 4
Device ID 4
R
Bit 3
Device ID 3
R
Bit 2
Device ID 2
R
1
Bit 1
Device ID 1
R
0
Bit 0
Device ID 0
R
X
X
9ZML1233=ED
9ZML1253=FD
1
SMBus Table: Byte Count Register
Byte 7
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
BC4
Bit 3
BC3
RW
0
RW
Writing to this register configures how
many bytes will be read back.
RW
1
Default value is 8 hex, so 9 bytes (0 to
8) will be read back by default.
Bit 2
BC2
0
Bit 1
BC1
RW
0
Bit 0
BC0
RW
0
SMBus Table: Output Skew Register A (when Input Clock A is selected)
Byte 8
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
Reserved
0
Bit 3
Reserved
0
Bit 2
I2O_FB_ASkew2
Bit 1
I2O_FB_ASkew1
Bit 0
I2O_FB_ASkew0
RW
Channel A Output delay programming
(early)
RW
RW
Binary value of number of VCO periods
that outputs will be pulled earlier than
input.
0
0
0
Note: For example, at 2.4GHz, each VCO period is 416.7ps and there are 24 VCO periods in a 100MHz output. Each write to bits [2:0] will
pull the output a early by that number of VCO periods. Writing “110” 4 times would pull the output back in phase with the input. Writing
“001” twice will accomplish the same result as writing “010” once - pulling the output 2 VCO periods earlier.
©2017 Integrated Device Technology, Inc.
19
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
SMBus Table: Output Skew Register A (when Input Clock B is selected)
Byte 9
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
Reserved
0
Bit 3
Reserved
0
Bit 2
I2O_FB_BSkew2
Bit 1
I2O_FB_BSkew1
Bit 0
I2O_FB_BSkew0
RW
Channel B Output delay programming
(early)
RW
RW
Binary value of number of VCO periods
that outputs will be earlier than input.
Default is 0.
0
0
0
Note: For example, at 2.4GHz, each VCO period is 416.7ps and there are 24 VCO periods in a 100MHz output. Each write to bits [2:0] will
pull the output a early by that number of VCO periods. Writing “110” 4 times would pull the output back in phase with the input. Writing
“001” twice will accomplish the same result as writing “010” once - pulling the output 2 VCO periods earlier.
©2017 Integrated Device Technology, Inc.
20
December 1, 2017
Package Drawings
Figure 2. 10 × 10 mm 72-VFQFPN – page 1
©2017 Integrated Device Technology, Inc.
21
9ZML1233E / 9ZML1253E Datasheet
December 1, 2017
Figure 3. 10 × 10 mm 72-VFQFPN – page 2
©2017 Integrated Device Technology, Inc.
22
9ZML1233E / 9ZML1253E Datasheet
December 1, 2017
Figure 4. 10 × 10 mm 72-VFQFPN – page 3
©2017 Integrated Device Technology, Inc.
23
9ZML1233E / 9ZML1253E Datasheet
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Ordering Information
Orderable Part Number
Package
Carrier Type
Temperature
9ZML1233EKILF
10 x 10 mm, 0.5mm pitch 72-VFQFPN
Tray
-40° to +85°C
9ZML1233EKILFT
10 x 10 mm, 0.5mm pitch 72-VFQFPN
Tape and Reel
-40° to +85°C
9ZML1253EKILF
10 x 10 mm, 0.5mm pitch 72-VFQFPN
Tray
-40° to +85°C
9ZML1253EKILFT
10 x 10 mm, 0.5mm pitch 72-VFQFPN
Tape and Reel
-40° to +85°C
“LF” designates PB-free configuration, RoHS compliant.
“E” is the device revision designator (will not correlate with the datasheet revision).
Marking Diagrams
1. “L” denotes RoHS compliant package.
ICS
9ZML1253EKIL
LOT
COO YYWW
ICS
9ZML1233EKIL
LOT
COO YYWW
2. “LOT” denotes the lot number.
3. “COO” denotes country of origin.
4. “YYWW” denotes the last two digits of the year and week the part
was assembled.
Revision History
Revision Date
Description of Change
December 1, 2017
Removed “5V tolerant” reference in pins 13 and 14 descriptions.
May 19, 2017
Corrected typos in orderable part numbers.
May 11, 2017
▪ Updated package outline drawings to latest version.
▪ Updated Byte 6 IDs.
April 27, 2017
▪ Updated Phase Jitter, PLL Mode IF-UPI typical and maximum values.
April 21, 2017
▪ Update Features and Key Specifications.
▪ Updated PCIe Common Clocked, PCIe Separate Clocked, and QPI/UPI to latest format, added IF-UPI
spec to QPI/UPI tables.
▪ Updated Test Loads drawing to latest version.
▪ Corrected SMBus Addressing table for 1233/1253.
April 11, 2017
▪ Reverted back to original Device ID Scheme, byte 6 updated accordingly:
9ZML1233=ED
9ZML1253=FD
January 31, 2017
Initial release.
©2017 Integrated Device Technology, Inc.
24
December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
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December 1, 2017
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