DATASHEET
CA3140, CA3140A
FN957
Rev.10.00
Jul 11, 2005
4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output
The CA3140A and CA3140 are integrated circuit operational
amplifiers that combine the advantages of high voltage
PMOS transistors with high voltage bipolar transistors on a
single monolithic chip.
The CA3140A and CA3140 BiMOS operational amplifiers
feature gate protected MOSFET (PMOS) transistors in the
input circuit to provide very high input impedance, very low
input current, and high speed performance. The CA3140A
and CA3140 operate at supply voltage from 4V to 36V
(either single or dual supply). These operational amplifiers
are internally phase compensated to achieve stable
operation in unity gain follower operation, and additionally,
have access terminal for a supplementary external capacitor
if additional frequency roll-off is desired. Terminals are also
provided for use in applications requiring input offset voltage
nulling. The use of PMOS field effect transistors in the input
stage results in common mode input voltage capability down
to 0.5V below the negative supply terminal, an important
attribute for single supply applications. The output stage
uses bipolar transistors and includes built-in protection
against damage from load terminal short circuiting to either
supply rail or to ground.
The CA3140A and CA3140 are intended for operation at
supply voltages up to 36V (18V).
Features
• MOSFET Input Stage
- Very High Input Impedance (ZIN) -1.5T (Typ)
- Very Low Input Current (Il) -10pA (Typ) at 15V
- Wide Common Mode Input Voltage Range (VlCR) - Can be
Swung 0.5V Below Negative Supply Voltage Rail
- Output Swing Complements Input Common Mode
Range
• Directly Replaces Industry Type 741 in Most Applications
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Ground-Referenced Single Supply Amplifiers in
Automobile and Portable Instrumentation
• Sample and Hold Amplifiers
• Long Duration Timers/Multivibrators
(seconds-Minutes-Hours)
• Photocurrent Instrumentation
• Peak Detectors
• Active Filters
• Comparators
• Interface in 5V TTL Systems and Other Low
Supply Voltage Systems
• All Standard Operational Amplifier Applications
• Function Generators
• Tone Controls
• Power Supplies
• Portable Instruments
• Intrusion Alarm Systems
Pinout
CA3140 (PDIP, SOIC)
TOP VIEW
FN957 Rev.10.00
Jul 11, 2005
OFFSET
NULL
1
INV. INPUT
2
NON-INV.
INPUT
3
V-
4
+
8
STROBE
7
V+
6
OUTPUT
5
OFFSET
NULL
Page 1 of 24
CA3140, CA3140A
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
CA3140AE
-55 to 125
8 Ld PDIP
E8.3
CA3140AEZ*
(See Note)
-55 to 125
8 Ld PDIP
(Pb-free)
E8.3
CA3140AM
(3140A)
-55 to 125
8 Ld SOIC
M8.15
CA3140AM96
(3140A)
-55 to 125
8 Ld SOIC Tape and Reel
CA3140AMZ
(3140A) (See Note)
-55 to 125
8 Ld SOIC
(Pb-free)
CA3140AMZ96
(3140A) (See Note)
-55 to 125
8 Ld SOIC Tape and Reel
(Pb-free)
CA3140E
-55 to 125
8 Ld PDIP
E8.3
CA3140EZ*
(See Note)
-55 to 125
8 Ld PDIP
(Pb-free)
E8.3
CA3140M
(3140)
-55 to 125
8 Ld SOIC
M8.15
CA3140M96
(3140)
-55 to 125
8 Ld SOIC Tape and Reel
CA3140MZ
(3140) (See Note)
-55 to 125
8 Ld SOIC
(Pb-free)
CA3140MZ96
(3140) (See Note)
-55 to 125
8 Ld SOIC Tape and Reel
(Pb-free)
M8.15
M8.15
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
FN957 Rev.10.00
Jul 11, 2005
Page 2 of 24
CA3140, CA3140A
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V
Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V++8V) To (V- -0.5V)
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 1)
JA (oC/W) JC (oC/W)
PDIP Package* . . . . . . . . . . . . . . . . . .
115
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
165
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details
2. Short circuit may be applied to ground or to either supply.
Electrical Specifications
VSUPPLY = 15V, TA = 25oC
TYPICAL VALUES
PARAMETER
SYMBOL
Input Offset Voltage Adjustment Resistor
TEST CONDITIONS
Typical Value of Resistor
Between Terminals 4 and 5 or 4 and 1 to
Adjust Max VIO
CA3140
CA3140A
UNITS
4.7
18
k
Input Resistance
RI
1.5
1.5
T
Input Capacitance
CI
4
4
pF
Output Resistance
RO
60
60
Equivalent Wideband Input Noise Voltage
(See Figure 27)
eN
BW = 140kHz, RS = 1M
48
48
V
Equivalent Input Noise Voltage (See Figure 35)
eN
RS = 100
f = 1kHz
40
40
nV/Hz
f = 10kHz
12
12
nV/Hz
IOM+
Source
40
40
mA
IOM-
Sink
18
18
mA
Short Circuit Current to Opposite Supply
Gain-Bandwidth Product, (See Figures 6, 30)
fT
4.5
4.5
MHz
Slew Rate, (See Figure 31)
SR
9
9
V/s
220
220
A
Rise Time
0.08
0.08
s
Overshoot
10
10
%
To 1mV
4.5
4.5
s
To 10mV
1.4
1.4
s
Sink Current From Terminal 8 To Terminal 4 to
Swing Output Low
Transient Response (See Figure 28)
tr
OS
Settling Time at 10VP-P, (See Figure 5)
Electrical Specifications
tS
RL = 2k
CL = 100pF
RL = 2k
CL = 100pF
Voltage Follower
For Equipment Design, at VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified
CA3140
PARAMETER
CA3140A
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Offset Voltage
|VIO|
-
5
15
-
2
5
mV
Input Offset Current
|IIO|
-
0.5
30
-
0.5
20
pA
II
-
10
50
-
10
40
pA
Input Current
FN957 Rev.10.00
Jul 11, 2005
Page 3 of 24
CA3140, CA3140A
Electrical Specifications
For Equipment Design, at VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified (Continued)
CA3140
PARAMETER
Large Signal Voltage Gain (Note 3)
(See Figures 6, 29)
Common Mode Rejection Ratio
(See Figure 34)
CA3140A
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
AOL
20
100
-
20
100
-
kV/V
86
100
-
86
100
-
dB
-
32
320
-
32
320
V/V
70
90
-
70
90
-
dB
CMRR
Common Mode Input Voltage Range (See Figure 8)
VICR
-15
-15.5 to +12.5
11
-15
-15.5 to +12.5
12
V
Power-Supply Rejection Ratio,
VIO/VS (See Figure 36)
PSRR
-
100
150
-
100
150
V/V
76
80
-
76
80
-
dB
Max Output Voltage (Note 4)
(See Figures 2, 8)
VOM+
+12
13
-
+12
13
-
V
VOM-
-14
-14.4
-
-14
-14.4
-
V
Supply Current (See Figure 32)
I+
-
4
6
-
4
6
mA
Device Dissipation
PD
-
120
180
-
120
180
mW
VIO/T
-
8
-
-
6
-
V/oC
Input Offset Voltage Temperature Drift
NOTES:
3. At VO = 26VP-P , +12V, -14V and RL = 2k.
4. At RL = 2k.
Electrical Specifications
For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC
TYPICAL VALUES
SYMBOL
CA3140
CA3140A
UNITS
Input Offset Voltage
PARAMETER
|VIO|
5
2
mV
Input Offset Current
|IIO|
0.1
0.1
pA
Input Current
II
2
2
pA
Input Resistance
RI
1
1
T
AOL
100
100
kV/V
100
100
dB
CMRR
32
32
V/V
90
90
dB
VICR
-0.5
-0.5
V
2.6
2.6
V
PSRR
VIO/VS
100
100
V/V
80
80
dB
VOM+
3
3
V
VOM-
0.13
0.13
V
Source
IOM+
10
10
mA
Sink
I
Large Signal Voltage Gain (See Figures 6, 29)
Common Mode Rejection Ratio
Common Mode Input Voltage Range (See Figure 8)
Power Supply Rejection Ratio
Maximum Output Voltage (See Figures 2, 8)
Maximum Output Current:
OM-
1
1
mA
Slew Rate (See Figure 31)
SR
7
7
V/s
Gain-Bandwidth Product (See Figure 30)
fT
3.7
3.7
MHz
Supply Current (See Figure 32)
I+
1.6
1.6
mA
Device Dissipation
PD
8
8
mW
FN957 Rev.10.00
Jul 11, 2005
Page 4 of 24
CA3140, CA3140A
Electrical Specifications
For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC (Continued)
TYPICAL VALUES
PARAMETER
SYMBOL
CA3140
CA3140A
UNITS
200
200
A
Sink Current from Terminal 8 to Terminal 4 to Swing Output Low
Block Diagram
2mA
4mA
7 V+
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
+
200A
3
INPUT
-
A 10
2
1.6mA
200A
2A
A
10,000
2mA
A 1
C1
12pF
5
1
OFFSET
NULL
FN957 Rev.10.00
Jul 11, 2005
6 OUTPUT
4 V8
STROBE
Page 5 of 24
CA3140, CA3140A
Schematic Diagram
BIAS CIRCUIT
INPUT STAGE
SECOND STAGE
OUTPUT STAGE
DYNAMIC CURRENT SINK
7 V+
D1
D7
Q1
Q3
Q2
D8
R10
1K
Q4
Q5
Q6
Q20
R9
50
Q19 R11
20
Q7
R12
12K
R14
20K
Q21
Q17
R1
8K
R13
5K
R8
Q8
1K Q
18
D2
D3
6 OUTPUT
D4
D5
INVERTING
INPUT
2
NON-INVERTING
INPUT
3
-
Q9
+
Q10
C1
R2
500
R3
500
Q11
R4
500
Q15
1
Q16
D6
R6
50
R5
500
OFFSET NULL
Q14
Q13
Q12
5
NOTE:
12pF
R7
30
8
4
STROBE
V-
All resistance values are in ohms.
Application Information
Circuit Description
As shown in the block diagram, the input terminals may be
operated down to 0.5V below the negative supply rail. Two
class A amplifier stages provide the voltage gain, and a unique
class AB amplifier stage provides the current gain necessary to
drive low-impedance loads.
A biasing circuit provides control of cascoded constant current
flow circuits in the first and second stages. The CA3140 includes
an on chip phase compensating capacitor that is sufficient for
the unity gain voltage follower configuration.
Input Stage
The schematic diagram consists of a differential input stage using
PMOS field-effect transistors (Q9, Q10) working into a mirror pair
of bipolar transistors (Q11, Q12) functioning as load resistors
together with resistors R2 through R5. The mirror pair transistors
also function as a differential-to-single-ended converter to provide
FN957 Rev.10.00
Jul 11, 2005
base current drive to the second stage bipolar transistor (Q13).
Offset nulling, when desired, can be effected with a 10k
potentiometer connected across Terminals 1 and 5 and with its
slider arm connected to Terminal 4. Cascode-connected bipolar
transistors Q2, Q5 are the constant current source for the input
stage. The base biasing circuit for the constant current source is
described subsequently. The small diodes D3, D4, D5 provide
gate oxide protection against high voltage transients, e.g., static
electricity.
Second Stage
Most of the voltage gain in the CA3140 is provided by the
second amplifier stage, consisting of bipolar transistor Q13 and
its cascode connected load resistance provided by bipolar
transistors Q3, Q4. On-chip phase compensation, sufficient for
a majority of the applications is provided by C1. Additional
Miller-Effect compensation (roll off) can be accomplished,
when desired, by simply connecting a small capacitor between
Terminals 1 and 8. Terminal 8 is also used to strobe the output
Page 6 of 24
CA3140, CA3140A
stage into quiescence. When terminal 8 is tied to the negative
supply rail (Terminal 4) by mechanical or electrical means, the
output Terminal 6 swings low, i.e., approximately to Terminal 4
potential.
Output Stage
The CA3140 Series circuits employ a broad band output stage
that can sink loads to the negative supply to complement the
capability of the PMOS input stage when operating near the
negative rail. Quiescent current in the emitter-follower cascade
circuit (Q17, Q18) is established by transistors (Q14, Q15) whose
base currents are “mirrored” to current flowing through diode D2 in
the bias circuit section. When the CA3140 is operating such that
output Terminal 6 is sourcing current, transistor Q18 functions as
an emitter-follower to source current from the V+ bus (Terminal 7),
via D7, R9, and R11. Under these conditions, the collector
potential of Q13 is sufficiently high to permit the necessary flow of
base current to emitter follower Q17 which, in turn, drives Q18.
current in diode connected transistor Q2 establishes the currents
in transistors Q14 and Q15.
Typical Applications
Wide dynamic range of input and output characteristics with the
most desirable high input impedance characteristics is achieved
in the CA3140 by the use of an unique design based upon the
PMOS Bipolar process. Input common mode voltage range and
output swing capabilities are complementary, allowing operation
with the single supply down to 4V.
The wide dynamic range of these parameters also means that
this device is suitable for many single supply applications, such
as, for example, where one input is driven below the potential
of Terminal 4 and the phase sense of the output signal must be
maintained – a most important consideration in comparator
applications.
When the CA3140 is operating such that output Terminal 6 is
sinking current to the V- bus, transistor Q16 is the current sinking
element. Transistor Q16 is mirror connected to D6, R7, with
current fed by way of Q21, R12, and Q20. Transistor Q20, in turn,
is biased by current flow through R13, zener D8, and R14. The
dynamic current sink is controlled by voltage level sensing. For
purposes of explanation, it is assumed that output Terminal 6 is
quiescently established at the potential midpoint between the V+
and V- supply rails. When output current sinking mode operation
is required, the collector potential of transistor Q13 is driven below
its quiescent level, thereby causing Q17, Q18 to decrease the
output voltage at Terminal 6. Thus, the gate terminal of PMOS
transistor Q21 is displaced toward the V- bus, thereby reducing
the channel resistance of Q21. As a consequence, there is an
incremental increase in current flow through Q20, R12, Q21, D6,
R7, and the base of Q16. As a result, Q16 sinks current from
Terminal 6 in direct response to the incremental change in output
voltage caused by Q18. This sink current flows regardless of load;
any excess current is internally supplied by the emitter-follower
Q18. Short circuit protection of the output circuit is provided by
Q19, which is driven into conduction by the high voltage drop
developed across R11 under output short circuit conditions. Under
these conditions, the collector of Q19 diverts current from Q4 so
as to reduce the base current drive from Q17, thereby limiting
current flow in Q18 to the short circuited load terminal.
Bias Circuit
Quiescent current in all stages (except the dynamic current sink)
of the CA3140 is dependent upon bias current flow in R1. The
function of the bias circuit is to establish and maintain constant
current flow through D1, Q6, Q8 and D2. D1 is a diode connected
transistor mirror connected in parallel with the base emitter
junctions of Q1, Q2, and Q3. D1 may be considered as a current
sampling diode that senses the emitter current of Q6 and
automatically adjusts the base current of Q6 (via Q1) to maintain a
constant current through Q6, Q8, D2. The base currents in Q2, Q3
are also determined by constant current flow D1. Furthermore,
FN957 Rev.10.00
Jul 11, 2005
Page 7 of 24
CA3140, CA3140A
power transistors and thyristors directly without the need for
level shifting circuitry usually associated with the 741 series of
operational amplifiers.
Output Circuit Considerations
Excellent interfacing with TTL circuitry is easily achieved with a
single 6.2V zener diode connected to Terminal 8 as shown in
Figure 1. This connection assures that the maximum output
signal swing will not go more positive than the zener voltage
minus two base-to-emitter voltage drops within the CA3140.
These voltages are independent of the operating supply
voltage.
V+
5V TO 36V
2
6.2V
6
CA3140
3
Offset Voltage Nulling
LOGIC
SUPPLY
5V
7
8
The input offset voltage can be nulled by connecting a 10k
potentiometer between Terminals 1 and 5 and returning its
wiper arm to terminal 4, see Figure 3A. This technique,
however, gives more adjustment range than required and
therefore, a considerable portion of the potentiometer rotation
is not fully utilized. Typical values of series resistors (R) that
may be placed at either end of the potentiometer, see Figure
3B, to optimize its utilization range are given in the Electrical
Specifications table.
TYPICAL
TTL GATE
5V
4
Figure 4 shows some typical configurations. Note that a series
resistor, RL, is used in both cases to limit the drive available to
the driven device. Moreover, it is recommended that a series
diode and shunt diode be used at the thyristor input to prevent
large negative transient surges that can appear at the gate of
thyristors, from damaging the integrated circuit.
OUTPUT STAGE TRANSISTOR (Q15, Q16)
SATURATION VOLTAGE (mV)
FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO
TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT
SWING TO TTL LEVELS
1000
An alternate system is shown in Figure 3C. This circuit uses
only one additional resistor of approximately the value shown
in the table. For potentiometers, in which the resistance does
not drop to 0 at either end of rotation, a value of resistance
10% lower than the values shown in the table should be used.
SUPPLY VOLTAGE (V-) = 0V
TA = 25oC
SUPPLY VOLTAGE (V+) = +5V
100
+15V
Low Voltage Operation
+30V
Operation at total supply voltages as low as 4V is possible with
the CA3140. A current regulator based upon the PMOS
threshold voltage maintains reasonable constant operating
current and hence consistent performance down to these lower
voltages.
10
1
0.01
0.1
1.0
LOAD (SINKING) CURRENT (mA)
The low voltage limitation occurs when the upper extreme of the
input common mode voltage range extends down to the voltage
at Terminal 4. This limit is reached at a total supply voltage just
below 4V. The output voltage range also begins to extend down to
the negative supply rail, but is slightly higher than that of the input.
Figure 8 shows these characteristics and shows that with 2V dual
supplies, the lower extreme of the input common mode voltage
range is below ground potential.
10
FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15
AND Q16) vs LOAD CURRENT
Figure 2 shows output current sinking capabilities of the
CA3140 at various supply voltages. Output voltage swing to
the negative supply rail permits this device to operate both
V+
V+
2
2
7
CA3140
3
1
5
2
6
CA3140
6
3
4
R
V+
7
1
3
R
1
10k
10k
6
CA3140
4
5
7
5
4
10k
R
V-
FIGURE 3A. BASIC
V-
FIGURE 3B. IMPROVED RESOLUTION
V-
FIGURE 3C. SIMPLER IMPROVED RESOLUTION
FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS
FN957 Rev.10.00
Jul 11, 2005
Page 8 of 24
CA3140, CA3140A
RS
V+
LOAD
30V
NO LOAD
120VAC
2
2
MT2
7
CA3140
6
6
RL
4
MT1
RL
LOAD
CA3140
3
3
+HV
7
4
FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
FOLLOWER
+15V
7
0.1F
3
SIMULATED
LOAD
10k
CA3140
2
0.05F
10
1mV
10mV
INPUT VOLTAGE (V)
0.1F
-15V
2k
SUPPLY VOLTAGE: VS = 15V
TA = 25oC
6
2k
100pF
4
LOAD RESISTANCE (RL) = 2k
LOAD CAPACITANCE (CL) = 100pF
8
6
1mV
INVERTING
5k
10mV
+15V
4
7
2
2
FOLLOWER
0
INVERTING
-2
CA3140
200
-4
1mV
-8
10mV
-10
0.1
1mV
1.0
SETTLING TIME (s)
4
4.99k
10mV
6
0.1F
2k
5.11k
-15V
SETTLING POINT
10
D1
D2
1N914
FIGURE 5A. WAVEFORM
SIMULATED
LOAD
100pF
3
-6
0.1F
5k
1N914
FIGURE 5B. TEST CIRCUITS
FIGURE 5. SETTLING TIME vs INPUT VOLTAGE
Bandwidth and Slew Rate
For those cases where bandwidth reduction is desired, for
example, broadband noise reduction, an external capacitor
connected between Terminals 1 and 8 can reduce the open
loop -3dB bandwidth. The slew rate will, however, also be
proportionally reduced by using this additional capacitor. Thus,
a 20% reduction in bandwidth by this technique will also
reduce the slew rate by about 20%.
Figure 5 shows the typical settling time required to reach 1mV
or 10mV of the final value for various levels of large signal
inputs for the voltage follower and inverting unity gain
amplifiers.
FN957 Rev.10.00
Jul 11, 2005
The exceptionally fast settling time characteristics are largely
due to the high combination of high gain and wide bandwidth of
the CA3140; as shown in Figure 6.
Input Circuit Considerations
As mentioned previously, the amplifier inputs can be driven
below the Terminal 4 potential, but a series current limiting
resistor is recommended to limit the maximum input terminal
current to less than 1mA to prevent damage to the input
protection circuitry.
Moreover, some current limiting resistance should be provided
between the inverting input and the output when the CA3140 is
Page 9 of 24
CA3140, CA3140A
The typical input current is on the order of 10pA when the
inputs are centered at nominal device dissipation. As the
output supplies load current, device dissipation will increase,
raising the chip temperature and resulting in increased input
current. Figure 7 shows typical input terminal current versus
ambient temperature for the CA3140.
100
-75
SUPPLY VOLTAGE: VS = 15V
TA = 25oC
OL
RL = 2k,
CL = 0pF
-90
-105
-120
-135
80
-150
OPEN LOOP PHASE
(DEGREES)
OPEN LOOP VOLTAGE GAIN (dB)
It is well known that MOSFET devices can exhibit slight
changes in characteristics (for example, small changes in input
60
RL = 2k,
CL = 100pF
40
offset voltage) due to the application of large differential input
voltages that are sustained over long periods at elevated
temperatures.
Both applied voltage and temperature accelerate these
changes. The process is reversible and offset voltage shifts of
the opposite polarity reverse the offset. Figure 9 shows the
typical offset voltage change as a function of various stress
voltages at the maximum rating of 125oC (for metal can); at
lower temperatures (metal can and plastic), for example, at
85oC, this change in voltage is considerably less. In typical
linear applications, where the differential voltage is small and
symmetrical, these incremental changes are of about the same
magnitude as those encountered in an operational amplifier
employing a bipolar transistor input stage.
10K
INPUT CURRENT (pA)
used as a unity gain voltage follower. This resistance prevents
the possibility of extremely large input signal transients from
forcing a signal through the input protection network and
directly driving the internal constant current source which could
result in positive feedback via the output terminal. A 3.9k
resistor is sufficient.
SUPPLY VOLTAGE: VS = 15V
1K
100
10
20
0
101
102
103
104
105
106
FREQUENCY (Hz)
107
1
-60
108
RL =
0
+VICR AT TA = 125oC
+VICR AT TA = 25oC
+VICR AT TA = -55oC
-0.5
-1.0
+VOUT AT TA = 125oC
+VOUT AT TA = 25oC
+VOUT AT TA = -55oC
-1.5
-2.0
-2.5
-3.0
0
5
10
15
SUPPLY VOLTAGE (V+, V-)
20
-20
0
20
40
60
80
TEMPERATURE (oC)
100
120
25
1.5
-VICR AT TA = 125oC
1.0
-VICR AT TA = 25oC
0.5
-VOUT FOR
TA = -55oC to 125oC
0
-VICR AT TA = -55oC
-0.5
-1.0
-1.5
0
5
10
15
SUPPLY VOLTAGE (V+, V-)
20
FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
FN957 Rev.10.00
Jul 11, 2005
140
FIGURE 7. INPUT CURRENT vs TEMPERATURE
INPUT AND OUTPUT VOLTAGE EXCURSIONS
FROM TERMINAL 4 (V-)
INPUT AND OUTPUT VOLTAGE EXCURSIONS
FROM TERMINAL 7 (V+)
FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs
FREQUENCY
-40
Page 10 of 24
25
CA3140, CA3140A
OFFSET VOLTAGE SHIFT (mV)
7
TA = 125oC
FOR METAL CAN PACKAGES
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
6
5
4
3
2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
1
0
0
500
1000 1500 2000 2500 3000 3500 4000 4500
TIME (HOURS)
FIGURE 9. TYPICAL INCREMENTAL OFFSET VOLTAGE
SHIFT vs OPERATING LIFE
Super Sweep Function Generator
A function generator having a wide tuning range is shown in
Figure 10. The 1,000,000/1 adjustment range is accomplished
by a single variable potentiometer or by an auxiliary sweeping
signal. The CA3140 functions as a non-inverting readout
amplifier of the triangular signal developed across the
integrating capacitor network connected to the output of the
CA3080A current source.
Buffered triangular output signals are then applied to a second
CA3080 functioning as a high speed hysteresis switch. Output
from the switch is returned directly back to the input of the
CA3080A current source, thereby, completing the positive
feedback loop
The triangular output level is determined by the four 1N914
level limiting diodes of the second CA3080 and the resistor
divider network connected to Terminal No. 2 (input) of the
CA3080. These diodes establish the input trip level to this
switching stage and, therefore, indirectly determine the
amplitude of the output triangle.
Compensation for propagation delays around the entire loop is
provided by one adjustment on the input of the CA3080. This
adjustment, which provides for a constant generator amplitude
output, is most easily made while the generator is sweeping.
High frequency ramp linearity is adjusted by the single 7pF to
60pF capacitor in the output of the CA3080A.
It must be emphasized that only the CA3080A is characterized
for maximum output linearity in the current generator function.
Meter Driver and Buffer Amplifier
Figure 11 shows the CA3140 connected as a meter driver and
buffer amplifier. Low driving impedance is required of the
CA3080A current source to assure smooth operation of the
Frequency Adjustment Control. This low-driving impedance
requirement is easily met by using a CA3140 connected as a
voltage follower. Moreover, a meter may be placed across the
input to the CA3080A to give a logarithmic analog indication of
the function generator’s frequency.
FN957 Rev.10.00
Jul 11, 2005
Analog frequency readout is readily accomplished by the means
described above because the output current of the CA3080A
varies approximately one decade for each 60mV change in the
applied voltage, VABC (voltage between Terminals 5 and 4 of the
CA3080A of the function generator). Therefore, six decades
represent 360mV change in VABC .
Now, only the reference voltage must be established to set the
lower limit on the meter. The three remaining transistors from
the CA3086 Array used in the sweep generator are used for
this reference voltage. In addition, this reference generator
arrangement tends to track ambient temperature variations,
and thus compensates for the effects of the normal negative
temperature coefficient of the CA3080A VABC terminal voltage.
Another output voltage from the reference generator is used to
insure temperature tracking of the lower end of the Frequency
Adjustment Potentiometer. A large series resistance simulates
a current source, assuring similar temperature coefficients at
both ends of the Frequency Adjustment Control.
To calibrate this circuit, set the Frequency Adjustment
Potentiometer at its low end. Then adjust the Minimum
Frequency Calibration Control for the lowest frequency. To
establish the upper frequency limit, set the Frequency
Adjustment Potentiometer to its upper end and then adjust the
Maximum Frequency Calibration Control for the maximum
frequency. Because there is interaction among these controls,
repetition of the adjustment procedure may be necessary. Two
adjustments are used for the meter. The meter sensitivity
control sets the meter scale width of each decade, while the
meter position control adjusts the pointer on the scale with
negligible effect on the sensitivity adjustment. Thus, the meter
sensitivity adjustment control calibrates the meter so that it
deflects 1/6 of full scale for each decade change in frequency.
Sine Wave Shaper
The circuit shown in Figure 12 uses a CA3140 as a voltage
follower in combination with diodes from the CA3019 Array to
convert the triangular signal from the function generator to a
sine-wave output signal having typically less than 2% THD.
The basic zero crossing slope is established by the 10k
potentiometer connected between Terminals 2 and 6 of the
CA3140 and the 9.1k resistor and 10k potentiometer from
Terminal 2 to ground. Two break points are established by
diodes D1 through D4. Positive feedback via D5 and D6
establishes the zero slope at the maximum and minimum
levels of the sine wave. This technique is necessary because
the voltage follower configuration approaches unity gain rather
than the zero gain required to shape the sine wave at the two
extremes.
Page 11 of 24
CA3140, CA3140A
CENTERING
-15V 10k
7.5k
+15V
360
3
7
+
-
2
4
5
2M
15k
+15V
51
pF
7-60
pF
-15V
39k
120
-15V
+
CA3140
3
-
2
HIGH
FREQ.
SHAPE
FREQUENCY
ADJUSTMENT
10k
0.1
F
5.1k
OUTPUT
AMPLIFIER
+15V
THIS NETWORK IS USED WHEN THE
OPTIONAL BUFFER CIRCUIT IS NOT USED
62k
10k
-
2
11k
11k
10k
-15V
2k
+15V
5
6
4
100k
FROM BUFFER METER
DRIVER (OPTIONAL)
0.1
F
7
6
CA3080A
360
SYMMETRY
-15V
+15V
HIGH
FREQUENCY
LEVEL
910k
7-60pF
EXTERNAL
OUTPUT
EXTERNAL
OUTPUT
7
6
CA3080
+
4
3
2.7k
-15V
13k
TO
SINE WAVE
SHAPER
TO OUTPUT
AMPLIFIER
1N914
FIGURE 10A. CIRCUIT
FREQUENCY
ADJUSTMENT
Top Trace: Output at junction of 2.7 and 51 resistors;
5V/Div., 500ms/Div.
Center Trace: External output of triangular function generator;
2V/Div., 500ms/Div.
+15V
METER DRIVER
AND BUFFER
AMPLIFIER
Bottom Trace: Output of “Log” generator; 10V/Div., 500ms/Div.
FIGURE 10B. FIGURE FUNCTION GENERATOR SWEEPING
POWER
SUPPLY 15V
M
-15V
FUNCTION
GENERATOR
WIDEBAND
LINE DRIVER
SINE WAVE
SHAPER
51
SWEEP
GENERATOR
FINE
RATE
GATE DC LEVEL
SWEEP ADJUST
OFF INT.
COARSE
RATE
1V/Div., 1s/Div.
EXT.
EXTERNAL
INPUT
SWEEP
LENGTH
Three tone test signals, highest frequency 0.5MHz. Note the slight
asymmetry at the three second/cycle signal. This asymmetry is due to
slightly different positive and negative integration from the CA3080A
and from the PC board and component leakages at the 100pA level.
FIGURE 10C. FUNCTION GENERATOR WITH FIXED
FREQUENCIES
V-
V-
FIGURE 10D. INTERCONNECTIONS
FIGURE 10. FUNCTION GENERATOR
FN957 Rev.10.00
Jul 11, 2005
Page 12 of 24
CA3140, CA3140A
500k
FREQUENCY
ADJUSTMENT
10k
SWEEP IN
FREQUENCY
CALIBRATION
MAXIMUM
620k
7
51k
3
6
CA3140
3M
-
2
4.7k
4
2k
+15V
0.1F
METER
SENSITIVITY
ADJUSTMENT
12k
FREQUENCY 2.4k
CALIBRATION
MINIMUM
2.5
k
0.1F
620
9
-15V
2k
7
6
R1
10k
14
METER
POSITION
ADJUSTMENT
3.6k 13
3/ OF CA3086
5
10k
EXTERNAL
OUTPUT
D4
5
D3
12
6
7
-15V
R3 10k
D1
9.1k
TO
WIDEBAND
OUTPUT
AMPLIFIER
SUBSTRATE
OF CA3019
1M
100
k
10
4
+15V
510
8
-
0.1F
1k
11
6
CA3140
2
5.6k
7.5k
7
+
3
5.1k
200A
M METER
510
-15V
+15V
TO CA3080A
OF FUNCTION CA3080A
GENERATOR
(FIGURE 10)
4
5
+
8
D6
9
1
3
4
2
D2
430
R2
1k
D
CA3019 5
DIODE ARRAY
-15V
FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER
FIGURE 12. SINE WAVE SHAPER
750k
“LOG”
SAWTOOTH 18M
1N914
100k
100k FINE
RATE
1M
22M
SAWTOOTH
SYMMETRY
1N914
0.47F
0.047F
8.2k
+15V SAWTOOTH AND
RAMP LOW LEVEL
SET (-14.5V)
COARSE
RATE
4700pF
50k
75k
470pF
7
2
-
3
CA3140
+
4
51k
SAWTOOTH
+15V
0.1
F
“LOG”+15V
6
50k
LOG
RATE
ADJUST
-15V
43k
10k
10k
7
-
3
CA3140
+
4
100k
TO OUTPUT 2
AMPLIFIER
30k
0.1
F
+15V
36k
TRIANGLE
6
10k
GATE
PULSE
OUTPUT
-15V
EXTERNAL OUTPUT
TO FUNCTION GENERATOR “SWEEP IN”
SWEEP WIDTH
-15V
3
6
CA3140
LOGVIO
2
-
5
1
51k
4
6.8k
91k
10k
TRIANGLE
25k
3.9
100
+15V
7
+
-15V
390
5
1
4
2
TRANSISTORS
FROM CA3086
ARRAY
SAWTOOTH
“LOG”
3
FIGURE 13. SWEEPING GENERATOR
FN957 Rev.10.00
Jul 11, 2005
Page 13 of 24
CA3140, CA3140A
This circuit can be adjusted most easily with a distortion
analyzer, but a good first approximation can be made by
comparing the output signal with that of a sine wave generator.
The initial slope is adjusted with the potentiometer R1, followed
by an adjustment of R2. The final slope is established by
adjusting R3, thereby adding additional segments that are
contributed by these diodes. Because there is some interaction
among these controls, repetition of the adjustment procedure
may be necessary.
REFERENCE
VOLTAGE
VOLTAGE
ADJUSTMENT
3
+
7
CA3140
INPUT
2
-
6
REGULATED
OUTPUT
4
Sweeping Generator
Figure 13 shows a sweeping generator. Three CA3140s are
used in this circuit. One CA3140 is used as an integrator, a
second device is used as a hysteresis switch that determines
the starting and stopping points of the sweep. A third CA3140
is used as a logarithmic shaping network for the log function.
Rates and slopes, as well as sawtooth, triangle, and
logarithmic sweeps are generated by this circuit.
Wideband Output Amplifier
Figure 14 shows a high slew rate, wideband amplifier suitable
for use as a 50 transmission line driver. This circuit, when
used in conjunction with the function generator and sine wave
shaper circuits shown in Figures 10 and 12 provides 18VP-P
output open circuited, or 9VP-P output when terminated in 50.
The slew rate required of this amplifier is 28V/s (18VP-P x x
0.5MHz).
+15V
+
SIGNAL
LEVEL
ADJUSTMENT
2.5k
200
3
-
8
4
-
+
+15V
3k
-15V
200
2.4pF
2pF
1.8k
2.2
k
2N3053
1N914
2.7
1N914
2.7
6
CA3140
2
50F
25V
7
+
1
OUTPUT
DC LEVEL
ADJUSTMENT
-
50F
25V
2.2
k
51
OUT
2W
2N4037
-15V
NOMINAL BANDWIDTH = 10MHz
tr = 35ns
FIGURE 14. WIDEBAND OUTPUT AMPLIFIER
Power Supplies
High input impedance, common mode capability down to the
negative supply and high output drive current capability are key
factors in the design of wide range output voltage supplies that
use a single input voltage to provide a regulated output voltage
that can be adjusted from essentially 0V to 24V.
Unlike many regulator systems using comparators having a
bipolar transistor input stage, a high impedance reference
voltage divider from a single supply can be used in connection
with the CA3140 (see Figure 15).
FN957 Rev.10.00
Jul 11, 2005
FIGURE 15. BASIC SINGLE SUPPLY VOLTAGE REGULATOR
SHOWING VOLTAGE FOLLOWER CONFIGURATION
Essentially, the regulators, shown in Figures 16 and 17, are
connected as non inverting power operational amplifiers with a
gain of 3.2. An 8V reference input yields a maximum output
voltage slightly greater than 25V. As a voltage follower, when the
reference input goes to 0V the output will be 0V. Because the
offset voltage is also multiplied by the 3.2 gain factor, a
potentiometer is needed to null the offset voltage.
Series pass transistors with high ICBO levels will also prevent
the output voltage from reaching zero because there is a finite
voltage drop (VCESAT) across the output of the CA3140 (see
Figure 2). This saturation voltage level may indeed set the
lowest voltage obtainable.
The high impedance presented by Terminal 8 is advantageous
in effecting current limiting. Thus, only a small signal transistor
is required for the current-limit sensing amplifier. Resistive
decoupling is provided for this transistor to minimize damage to
it or the CA3140 in the event of unusual input or output
transients on the supply rail.
Figures 16 and 17, show circuits in which a D2201 high speed
diode is used for the current sensor. This diode was chosen for
its slightly higher forward voltage drop characteristic, thus giving
greater sensitivity. It must be emphasized that heat sinking of
this diode is essential to minimize variation of the current trip
point due to internal heating of the diode. That is, 1A at 1V
forward drop represents one watt which can result in significant
regenerative changes in the current trip point as the diode
temperature rises. Placing the small signal reference amplifier in
the proximity of the current sensing diode also helps minimize
the variability in the trip level due to the negative temperature
coefficient of the diode. In spite of those limitations, the current
limiting point can easily be adjusted over the range from 10mA
to 1A with a single adjustment potentiometer. If the temperature
stability of the current limiting system is a serious consideration,
the more usual current sampling resistor type of circuitry should
be employed.
A power Darlington transistor (in a metal can with heatsink), is
used as the series pass element for the conventional current
limiting system, Figure 16, because high power Darlington
dissipation will be encountered at low output voltage and high
currents.
Page 14 of 24
CA3140, CA3140A
A small heat sink VERSAWATT transistor is used as the series
pass element in the fold back current system, Figure 17, since
dissipation levels will only approach 10W. In this system, the
D2201 diode is used for current sampling. Foldback is
provided by the 3k and 100k divider network connected to
the base of the current sensing transistor.
Both regulators provide better than 0.02% load regulation.
Because there is constant loop gain at all voltage settings, the
+30V
3
2N6385
CURRENT
POWER DARLINGTON LIMITING
ADJUST
D2201
2
75
1k
OUTPUT
0.1 24V
AT 1A
1k
100
7
8
1k
56pF
2
6
2.7k 10F
CA3140
+
5
-
1
100k
INPUT
+
2.2k
-
10 11
1 2
9
3
8 7
5
6
4
+30V
1k 200
1
12
2N2102
7
+
2.7k 10F
5
-
+
100k
-
13
+
2.2k
250F
0.01F
-
10 11
1 2
9
3
8 7
5
6
4
12
180k
1k
82k
3
4
5F 50k
14
VOLTAGE
ADJUST
100k
+
-
250F
0.01F
13
CA3086
CA3086
1k
1k
62k
62k
HUM AND NOISE OUTPUT
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