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HD6417751RBP240V

HD6417751RBP240V

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    BBGA256

  • 描述:

    IC MCU 32BIT ROMLESS 256BGA

  • 数据手册
  • 价格&库存
HD6417751RBP240V 数据手册
The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH7751 Group, SH7751R Group User’s Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series Rev.3.01 Sep 2013 Page ii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product. 5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. “Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. “High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products. 11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. (2012.4) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page iii of liv General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed. 5. Reading from/Writing to Reserved Bit of Each Register Note: Treat the reserved bit of register used in each module as follows except in cases where the specifications for values which are read from or written to the bit are provided in the description. The bit is always read as 0. The write value should be 0 or one, which has been read immediately before writing. Writing the value, which has been read immediately before writing has the advantage of preventing the bit from being affected on its extended function when the function is assigned. Page iv of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Preface The SH-4 (SH7751 Group (SH7751, SH7751R)) microprocessor incorporates the 32-bit SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7751 Group is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and PCI controller (PCIC). This series can be used in a wide range of multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous DRAM and PCMCIA. Target Readers: This manual is designed for use by people who design application systems using the SH7751 or SH7751R. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. This hardware manual contains revisions related to the addition of R-mask functionality. Be sure to check the text for the updated content. Purpose: This manual provides the information of the hardware functions and electrical characteristics of the SH7751 and SH7751R. The SH-4 Software Manual contains detailed information of executable instructions. Please read the Software Manual together with this manual. How to Use the Book: • To understand general functions → Read the manual from the beginning. The manual explains the CPU, system control functions, peripheral functions and electrical characteristics in that order. • To understanding CPU functions → Refer to the separate SH-4 Software Manual. Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.renesas.com/) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page v of liv • User manuals for SH7751 and SH7751R Name of Document Document No. SH7751 Group, SH7751R Group Hardware Manual This manual SH-4 Software Manual REJ09B0318-0600 • User manuals for development tools Name of Document Document No. SuperH™ C/C++ Compiler, Assembler, Optimizing Linkage Editor User's REJ10B0047-0100H Manual SuperH™ RISC engine Simulator/Debugger User's Manual REJ10B0210-0300 High-performance Embedded Workshop User's Manual REJ10J1554-0100 Page vi of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Main Revisions for This Edition Item Page Revision (See Manual for Details) All ⎯ Added ONPAC-BGA products (HD6417750SBA200V) 1.1 SH7751/SH7751R Group Features 2 Table amended Table 1.1 SH7751/SH7751R Group Features 8 Item Features CPU • Item Renesas Electronics original SuperH architecture Features Product lineup Abbreviation Voltage Operating Frequency Model No. Package SH7751 1.8 V 167 MHz 256-pin BGA SH7751R 1.5 V 240 MHz HD6417751BP167 HD6417751F167 256-pin QFP HD6417751RBP240 256-pin BGA HD6417751RBA240H 22.2.1 PCI Configuration Register 0 (PCICONF0) 857 22.12.5 Notes on Parity Error Detection during Master Access 980, 981 Newly added 23.1 Absolute Maximum Ratings 983 Table amended and note added Table 23.1 Absolute Maximum Ratings HD6417751RF240 256-pin QFP HD6417751RBG240 292-pin BGA Note amended Note: * The vendor ID H'1054 specifies Hitachi, Ltd., but the SH7751 and SH7751R are now products of Renesas Electronics Corp. For information on these products, contact Renesas Electronics Corp. Item Symbol Value I/O, RTC, CPG power supply voltage VDDQ, VDD-RTC, VDD-CPG –0.3 to 4.2 VDD, VDD-PLL1/2 –0.3 to 2.5 Internal power supply voltage Unit V 1 –0.3 to 4.6* V –0.3 to 2.1*1 Input voltage Vin –0.3 to VDDQ +0.3 V Operating temperature Topr –20 to 75, –40 to 85*2 °C Storage temperature Tstg –55 to 125 °C Notes: 1. HD6417751R only. 2. HD6417751RBA240HV only. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page vii of liv Item Page Revision (See Manual for Details) 23.2 DC Characteristics 982, 983 Table title amended and note added 988,. 989 Table title amended and note added Table 23.2 DC Characteristics (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV) Ta = –20 to +75°C* 3 Table 23.4 DC Characteristics (HD6417751RBP200 (V), HD6417751RBG200 (V), 3 HD6417751RBA240HV* ) Ta = –20 to +75°C* Notes: 3. Ta = –40 to 85°C for the HD6417751RBA240HV. Notes: 3. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. 4. Ta = –40 to 85°C for the HD6417751RBA240HV. 4 23.3 AC Characteristics 996 Table title amended Table 23.11 Clock Timing (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*) 997 Table title amended and note added 23.3.1 Clock and Control Signal Timing 998, 999 Table 23.9 Clock Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV) Table 23.14 Clock and Control Signal Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV) VDDQ = 3.0 to 3.6 V, VDD = 2 1.5 V, Ta = –20 to 75°C* , CL = 30 pF Page viii of liv Note: * This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. Table title and table amended and note added Item Max Unit 1 tOSC2 2 — ms 1 Symbol tOSC3 2 — ms 1 tOSC4 2 — ms Standby return oscillation settling time 1* Standby return oscillation settling time 2* Standby return oscillation settling time 3* Min Figure Notes: 1. When the oscillation settling time of the crystal resonator is 1 ms or less. 2. Ta = –40 to 85°C for the HD6417751RBA240HV. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Item Page Revision (See Manual for Details) 23.3.1 Clock and Control Signal Timing 1002, 1003 Table title and table amended and note added Item Table 23.16 Clock and Control Signal Timing (HD6417751RBP200 (V), HD6417751RBG200 (V), 2 HD6417751RBA240HV* ) Symbol Unit tOSC2 2 — ms 1 tOSC3 2 — ms 1 tOSC4 2 — ms Standby return oscillation settling time 2* Standby return oscillation settling time 3* Min Figure Notes: 1. When the oscillation settling time of the crystal resonator is 1 ms or less. 2. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. VDDQ = 3.0 to 3.6 V, VDD = 3 1.5 V, Ta = –20 to 75°C* , CL = 30 pF 23.3.2 Control Signal Timing Max 1 Standby return oscillation settling time 1* 3. Ta = –40 to 85°C for the HD6417751RBA240HV. 1012 Table amended and note added HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751 RBA240HV Table 23.19 Control Signal Timing HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 2 RBA240HV* 1 Item Symbol Min HD6417751 RF240 (V) 1 Max Min HD6417751 RF200 (V) 1 * * 1 * Max Min * Max Min Max Unit Figure Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta= –20 to 3 75°C* , CL = 30 pF, PLL2 on 2. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. 3. Ta = –40 to 85°C for the HD6417751RBA240HV. 23.3.3 Bus Timing Table 23.21 Bus Timing (1) 1016, 1017 Table amended and note added HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751 RBA240HV HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 2 RBA240HV* 1 1 Symbol Min Max Min Max HD6417751 RF200 (V) 1 * * Item HD6417751 RF240 (V) 1 * Min Max * Min Max Unit Notes Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta= –20 to 3 75°C* , CL = 30 pF, PLL2 on 2. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. 3. Ta = –40 to 85°C for the HD6417751RBA240HV. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page ix of liv Item Page Revision (See Manual for Details) 23.3.4 Peripheral Module Signal Timing 1067 to 1069 Table amended and note added Table 23.23 Peripheral Module Signal Timing (1) HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 RBA240HV*3 HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751 RBA240HV 2 * Module Item Symbol Min HD6417751 RF240 (V) 2 * Max Min Max HD6417751 RF200 (V) 2 *2 * Min Max Min Max Unit Figure Notes Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta= –20 to 4 75°C* , CL = 30 pF, PLL2 on 3. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. 4. Ta = –40 to 85°C for the HD6417751RBA240HV. Table 23.25 PCIC Signal Timing (in PCIREQ/PCIGNT NonPort Mode) (1) 1076 Notes: 1. HD6417751RF240 (V), HD6417751RF200 (V) 2. Ta = –40 to 85°C for the HD6417751RBA240HV. HD6417751RBP240 (V), HD6417751RBP200 (V), HD6417751RBG240 (V), HD6417751RBG200 (V), HD6417751RBA240HV, HD6417751RF240 (V), HD6417751RF200 (V): VDDQ = 3.0 to 3.6 V, VDD = 2 1.5 V, Ta = –20 to 75°C* , CL = 30 pF Table 23.27 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (1) Table title amended and note added Asterisk "*" in table changed to "*1" "3.0 (3.5*)" → "3.0 (3.5* )" 1 1079 Table title amended and note added Note: * Ta = –40 to 85°C for the HD6417751RBA240HV. HD6417751RBP240 (V), HD6417751RBP200 (V), HD6417751RBG240 (V), HD6417751RBG200 (V), HD6417751RBA240HV, HD6417751RF240 (V), HD6417751RF200 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75°C*, CL = 30 pF Page x of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Item Page Revision (See Manual for Details) Appendix B Package Dimensions 1092 Figure title amended 1094 Figure newly added 1105 Table amended Figure B.2 Package Dimensions (256-pin BGA: Devices Other than HD6417751RBA240HV) Figure B.4 Package Dimensions (256-Pin BGA: HD6417750RBA240HV) D.2 Handling of Unused Pins Table D.4 Handling of Pins When PCI Is Not Used Appendix H Product Lineup Table H.1 SH7751/SH7751R Product Lineup R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 1125 Pin Name I/O Handling AD31–AD0 I/O Pull up to 3.3 V* Table note amended Notes: 1. Contact a Renesas sales office regarding product versions with specifications for a wider temperature range (−40 to +85°C). The wide temperature range (−40 to +85°C) is the standard specification for the HD6417751RBA240HV. Page xi of liv All trademarks and registered trademarks are the property of their respective owners. Page xii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 SH7751/SH7751R Group Features ........................................................................................ 1 Block Diagram ....................................................................................................................... 9 Pin Arrangement .................................................................................................................. 10 Pin Functions ....................................................................................................................... 13 1.4.1 Pin Functions (256-Pin QFP).................................................................................. 13 1.4.2 Pin Functions (256-Pin BGA)................................................................................. 24 1.4.3 Pin Functions (292-Pin BGA)................................................................................. 35 Section 2 Programming Model ............................................................................47 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Data Formats........................................................................................................................ 47 Register Configuration......................................................................................................... 48 2.2.1 Privileged Mode and Banks .................................................................................... 48 2.2.2 General Registers.................................................................................................... 51 2.2.3 Floating-Point Registers.......................................................................................... 53 2.2.4 Control Registers .................................................................................................... 55 2.2.5 System Registers..................................................................................................... 56 Memory-Mapped Registers.................................................................................................. 58 Data Format in Registers...................................................................................................... 59 Data Formats in Memory ..................................................................................................... 59 Processor States ................................................................................................................... 60 Processor Modes .................................................................................................................. 62 Section 3 Memory Management Unit (MMU) ....................................................63 3.1 3.2 3.3 Overview.............................................................................................................................. 63 3.1.1 Features................................................................................................................... 63 3.1.2 Role of the MMU.................................................................................................... 63 3.1.3 Register Configuration............................................................................................ 66 3.1.4 Caution.................................................................................................................... 66 Register Descriptions ........................................................................................................... 67 Address Space...................................................................................................................... 71 3.3.1 Physical Address Space .......................................................................................... 71 3.3.2 External Memory Space.......................................................................................... 74 3.3.3 Virtual Address Space............................................................................................. 75 3.3.4 On-Chip RAM Space.............................................................................................. 76 3.3.5 Address Translation ................................................................................................ 76 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode ...................... 77 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xiii of liv 3.4 3.5 3.6 3.7 3.8 3.3.7 Address Space Identifier (ASID) ............................................................................ 77 TLB Functions ..................................................................................................................... 78 3.4.1 Unified TLB (UTLB) Configuration ...................................................................... 78 3.4.2 Instruction TLB (ITLB) Configuration................................................................... 82 3.4.3 Address Translation Method................................................................................... 82 MMU Functions................................................................................................................... 85 3.5.1 MMU Hardware Management................................................................................ 85 3.5.2 MMU Software Management ................................................................................. 85 3.5.3 MMU Instruction (LDTLB).................................................................................... 85 3.5.4 Hardware ITLB Miss Handling .............................................................................. 86 3.5.5 Avoiding Synonym Problems................................................................................. 87 MMU Exceptions................................................................................................................. 88 3.6.1 Instruction TLB Multiple Hit Exception................................................................. 88 3.6.2 Instruction TLB Miss Exception............................................................................. 88 3.6.3 Instruction TLB Protection Violation Exception .................................................... 89 3.6.4 Data TLB Multiple Hit Exception .......................................................................... 90 3.6.5 Data TLB Miss Exception ...................................................................................... 91 3.6.6 Data TLB Protection Violation Exception.............................................................. 92 3.6.7 Initial Page Write Exception................................................................................... 93 Memory-Mapped TLB Configuration ................................................................................. 94 3.7.1 ITLB Address Array ............................................................................................... 94 3.7.2 ITLB Data Array 1.................................................................................................. 95 3.7.3 ITLB Data Array 2.................................................................................................. 96 3.7.4 UTLB Address Array.............................................................................................. 97 3.7.5 UTLB Data Array 1 ................................................................................................ 98 3.7.6 UTLB Data Array 2 ................................................................................................ 99 Usage Notes ....................................................................................................................... 100 Section 4 Caches................................................................................................ 101 4.1 4.2 4.3 Overview............................................................................................................................ 101 4.1.1 Features................................................................................................................. 101 4.1.2 Register Configuration.......................................................................................... 102 Register Descriptions......................................................................................................... 103 Operand Cache (OC) ......................................................................................................... 105 4.3.1 Configuration........................................................................................................ 105 4.3.2 Read Operation ..................................................................................................... 108 4.3.3 Write Operation .................................................................................................... 109 4.3.4 Write-Back Buffer ................................................................................................ 111 4.3.5 Write-Through Buffer........................................................................................... 111 4.3.6 RAM Mode........................................................................................................... 111 Page xiv of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 4.3.7 4.3.8 4.3.9 4.3.10 4.4 4.5 4.6 4.7 OC Index Mode .................................................................................................... 113 Coherency between Cache and External Memory ................................................ 113 Prefetch Operation ................................................................................................ 113 Notes on Using OC RAM Mode (SH7751R Only) when in Cache Enhanced Mode ..................................................................................................................... 114 Instruction Cache (IC)........................................................................................................ 116 4.4.1 Configuration ........................................................................................................ 116 4.4.2 Read Operation ..................................................................................................... 119 4.4.3 IC Index Mode ...................................................................................................... 120 Memory-Mapped Cache Configuration (SH7751)............................................................. 120 4.5.1 IC Address Array .................................................................................................. 120 4.5.2 IC Data Array........................................................................................................ 122 4.5.3 OC Address Array ................................................................................................ 123 4.5.4 OC Data Array ...................................................................................................... 124 Memory-Mapped Cache Configuration (SH7751R).......................................................... 125 4.6.1 IC Address Array .................................................................................................. 125 4.6.2 IC Data Array........................................................................................................ 127 4.6.3 OC Address Array ................................................................................................ 128 4.6.4 OC Data Array ...................................................................................................... 129 4.6.5 Summary of Memory-Mapped OC Addresses...................................................... 130 Store Queues ...................................................................................................................... 131 4.7.1 SQ Configuration.................................................................................................. 131 4.7.2 SQ Writes.............................................................................................................. 131 4.7.3 Transfer to External Memory................................................................................ 132 4.7.4 Determination of SQ Access Exception................................................................ 133 4.7.5 SQ Read (SH7751R only)..................................................................................... 133 4.7.6 SQ Usage Notes (SH7751 Only) .......................................................................... 134 Section 5 Exceptions..........................................................................................137 5.1 5.2 5.3 5.4 5.5 Overview............................................................................................................................ 137 5.1.1 Features................................................................................................................. 137 5.1.2 Register Configuration.......................................................................................... 137 Register Descriptions ......................................................................................................... 138 Exception Handling Functions........................................................................................... 139 5.3.1 Exception Handling Flow ..................................................................................... 139 5.3.2 Exception Handling Vector Addresses ................................................................. 139 Exception Types and Priorities .......................................................................................... 140 Exception Flow .................................................................................................................. 143 5.5.1 Exception Flow ..................................................................................................... 143 5.5.2 Exception Source Acceptance............................................................................... 144 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xv of liv 5.6 5.7 5.8 5.5.3 Exception Requests and BL Bit ............................................................................ 146 5.5.4 Return from Exception Handling.......................................................................... 146 Description of Exceptions.................................................................................................. 146 5.6.1 Resets.................................................................................................................... 147 5.6.2 General Exceptions............................................................................................... 152 5.6.3 Interrupts............................................................................................................... 166 5.6.4 Priority Order with Multiple Exceptions .............................................................. 169 Usage Notes ....................................................................................................................... 170 Restrictions ........................................................................................................................ 171 Section 6 Floating-Point Unit............................................................................ 173 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Overview............................................................................................................................ 173 Data Formats...................................................................................................................... 173 6.2.1 Floating-Point Format........................................................................................... 173 6.2.2 Non-Numbers (NaN) ............................................................................................ 175 6.2.3 Denormalized Numbers ........................................................................................ 176 Registers ............................................................................................................................ 177 6.3.1 Floating-Point Registers ....................................................................................... 177 6.3.2 Floating-Point Status/Control Register (FPSCR) ................................................. 179 6.3.3 Floating-Point Communication Register (FPUL) ................................................. 180 Rounding............................................................................................................................ 181 Floating-Point Exceptions.................................................................................................. 181 Graphics Support Functions............................................................................................... 183 6.6.1 Geometric Operation Instructions......................................................................... 183 6.6.2 Pair Single-Precision Data Transfer...................................................................... 184 Usage Notes ....................................................................................................................... 185 6.7.1 Rounding Mode and Underflow Flag ................................................................... 185 6.7.2 Setting of Overflow Flag by FIPR or FTRV Instruction ...................................... 186 6.7.3 Sign of Operation Result when Using FIPR or FTRV Instruction ....................... 187 6.7.4 Notes on Double-Precision FADD and FSUB Instructions .................................. 187 Section 7 Instruction Set.................................................................................... 189 7.1 7.2 7.3 7.4 Execution Environment ..................................................................................................... 189 Addressing Modes ............................................................................................................. 191 Instruction Set .................................................................................................................... 195 Usage Notes ....................................................................................................................... 207 7.4.1 Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction (H'FFFD) .............................................................................................................. 207 Page xvi of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Section 8 Pipelining ...........................................................................................211 8.1 8.2 8.3 8.4 Pipelines............................................................................................................................. 211 Parallel-Executability......................................................................................................... 218 Execution Cycles and Pipeline Stalling ............................................................................. 222 Usage Notes ....................................................................................................................... 238 Section 9 Power-Down Modes ..........................................................................239 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Overview............................................................................................................................ 239 9.1.1 Types of Power-Down Modes .............................................................................. 239 9.1.2 Register Configuration.......................................................................................... 241 9.1.3 Pin Configuration.................................................................................................. 241 Register Descriptions ......................................................................................................... 242 9.2.1 Standby Control Register (STBCR)...................................................................... 242 9.2.2 Peripheral Module Pin High Impedance Control.................................................. 244 9.2.3 Peripheral Module Pin Pull-Up Control................................................................ 244 9.2.4 Standby Control Register 2 (STBCR2)................................................................. 245 9.2.5 Clock Stop Register 00 (CLKSTP00)................................................................... 246 9.2.6 Clock Stop Clear Register 00 (CLKSTPCLR00).................................................. 247 Sleep Mode ........................................................................................................................ 248 9.3.1 Transition to Sleep Mode...................................................................................... 248 9.3.2 Exit from Sleep Mode........................................................................................... 248 Deep Sleep Mode............................................................................................................... 248 9.4.1 Transition to Deep Sleep Mode ............................................................................ 248 9.4.2 Exit from Deep Sleep Mode ................................................................................. 249 Pin Sleep Mode .................................................................................................................. 249 9.5.1 Transition to Pin Sleep Mode ............................................................................... 249 9.5.2 Exit from Pin Sleep Mode..................................................................................... 249 Standby Mode .................................................................................................................... 249 9.6.1 Transition to Standby Mode.................................................................................. 249 9.6.2 Exit from Standby Mode....................................................................................... 250 9.6.3 Clock Pause Function ........................................................................................... 251 Module Standby Function.................................................................................................. 251 9.7.1 Transition to Module Standby Function ............................................................... 251 9.7.2 Exit from Module Standby Function .................................................................... 252 Hardware Standby Mode ................................................................................................... 253 9.8.1 Transition to Hardware Standby Mode ................................................................. 253 9.8.2 Exit from Hardware Standby Mode ...................................................................... 253 9.8.3 Usage Notes .......................................................................................................... 254 STATUS Pin Change Timing ............................................................................................ 254 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xvii of liv 9.9.1 In Reset ................................................................................................................. 255 9.9.2 In Exit from Standby Mode .................................................................................. 256 9.9.3 In Exit from Sleep Mode ...................................................................................... 257 9.9.4 In Exit from Deep Sleep Mode ............................................................................. 260 9.9.5 Hardware Standby Mode Timing.......................................................................... 262 9.10 Usage Notes ....................................................................................................................... 264 9.10.1 Note on Current Consumption .............................................................................. 264 Section 10 Clock Oscillation Circuits ............................................................... 267 10.1 Overview............................................................................................................................ 267 10.1.1 Features................................................................................................................. 267 10.2 Overview of CPG............................................................................................................... 269 10.2.1 Block Diagram of CPG......................................................................................... 269 10.2.2 CPG Pin Configuration......................................................................................... 272 10.2.3 CPG Register Configuration................................................................................. 272 10.3 Clock Operating Modes ..................................................................................................... 273 10.4 CPG Register Description.................................................................................................. 275 10.4.1 Frequency Control Register (FRQCR) ................................................................. 275 10.5 Changing the Frequency .................................................................................................... 278 10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off) ............ 278 10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)............. 278 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)....................... 279 10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off) ...................... 279 10.5.5 Changing CPU or Peripheral Module Clock Division Ratio ................................ 279 10.6 Output Clock Control......................................................................................................... 280 10.7 Overview of Watchdog Timer ........................................................................................... 280 10.7.1 Block Diagram...................................................................................................... 280 10.7.2 Register Configuration.......................................................................................... 281 10.8 WDT Register Descriptions............................................................................................... 281 10.8.1 Watchdog Timer Counter (WTCNT).................................................................... 281 10.8.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 282 10.8.3 Notes on Register Access ..................................................................................... 284 10.9 Using the WDT.................................................................................................................. 285 10.9.1 Standby Clearing Procedure ................................................................................. 285 10.9.2 Frequency Changing Procedure............................................................................ 285 10.9.3 Using Watchdog Timer Mode .............................................................................. 286 10.9.4 Using Interval Timer Mode .................................................................................. 286 10.10 Notes on Board Design ...................................................................................................... 287 10.11 Usage Notes ....................................................................................................................... 289 10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7751 Only)................. 289 Page xviii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Section 11 Realtime Clock (RTC) .....................................................................291 11.1 Overview............................................................................................................................ 291 11.1.1 Features................................................................................................................. 291 11.1.2 Block Diagram...................................................................................................... 292 11.1.3 Pin Configuration.................................................................................................. 293 11.1.4 11.1.4 Register Configuration............................................................................... 293 11.2 Register Descriptions ......................................................................................................... 295 11.2.1 64 Hz Counter (R64CNT)..................................................................................... 295 11.2.2 Second Counter (RSECCNT) ............................................................................... 296 11.2.3 Minute Counter (RMINCNT) ............................................................................... 296 11.2.4 Hour Counter (RHRCNT)..................................................................................... 297 11.2.5 Day-of-Week Counter (RWKCNT)...................................................................... 297 11.2.6 Day Counter (RDAYCNT) ................................................................................... 298 11.2.7 Month Counter (RMONCNT) .............................................................................. 298 11.2.8 Year Counter (RYRCNT) ..................................................................................... 299 11.2.9 Second Alarm Register (RSECAR) ...................................................................... 300 11.2.10 Minute Alarm Register (RMINAR)...................................................................... 300 11.2.11 Hour Alarm Register (RHRAR) ........................................................................... 301 11.2.12 Day-of-Week Alarm Register (RWKAR)............................................................. 301 11.2.13 Day Alarm Register (RDAYAR).......................................................................... 302 11.2.14 Month Alarm Register (RMONAR) ..................................................................... 303 11.2.15 RTC Control Register 1 (RCR1)........................................................................... 303 11.2.16 RTC Control Register 2 (RCR2)........................................................................... 305 11.2.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR) (SH7751R Only) ................................................................................................... 308 11.3 Operation ........................................................................................................................... 309 11.3.1 Time Setting Procedures ....................................................................................... 309 11.3.2 Time Reading Procedures ..................................................................................... 311 11.3.3 Alarm Function ..................................................................................................... 312 11.4 Interrupts............................................................................................................................ 313 11.5 Usage Notes ....................................................................................................................... 313 11.5.1 Register Initialization............................................................................................ 313 11.5.2 Carry Flag and Interrupt Flag in Standby Mode ................................................... 313 11.5.3 Crystal Oscillation Circuit .................................................................................... 313 Section 12 Timer Unit (TMU) ...........................................................................315 12.1 Overview............................................................................................................................ 315 12.1.1 Features................................................................................................................. 315 12.1.2 Block Diagram...................................................................................................... 316 12.1.3 Pin Configuration.................................................................................................. 316 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xix of liv 12.2 12.3 12.4 12.5 12.1.4 Register Configuration.......................................................................................... 317 Register Descriptions......................................................................................................... 318 12.2.1 Timer Output Control Register (TOCR)............................................................... 318 12.2.2 Timer Start Register (TSTR) ................................................................................ 319 12.2.3 Timer Start Register 2 (TSTR2) ........................................................................... 320 12.2.4 Timer Constant Registers (TCOR) ....................................................................... 321 12.2.5 Timer Counters (TCNT) ....................................................................................... 321 12.2.6 Timer Control Registers (TCR) ............................................................................ 322 12.2.7 Input Capture Register 2 (TCPR2) ....................................................................... 326 Operation ........................................................................................................................... 327 12.3.1 Counter Operation ................................................................................................ 327 12.3.2 Input Capture Function ......................................................................................... 330 Interrupts............................................................................................................................ 332 Usage Notes ....................................................................................................................... 332 12.5.1 Register Writes ..................................................................................................... 332 12.5.2 TCNT Register Reads........................................................................................... 333 12.5.3 Resetting the RTC Frequency Divider.................................................................. 333 12.5.4 External Clock Frequency .................................................................................... 333 Section 13 Bus State Controller (BSC) ............................................................. 335 13.1 Overview............................................................................................................................ 335 13.1.1 Features................................................................................................................. 335 13.1.2 Block Diagram...................................................................................................... 337 13.1.3 Pin Configuration.................................................................................................. 338 13.1.4 Register Configuration.......................................................................................... 340 13.1.5 Overview of Areas................................................................................................ 341 13.1.6 PCMCIA Support ................................................................................................. 344 13.2 Register Descriptions......................................................................................................... 348 13.2.1 Bus Control Register 1 (BCR1) ............................................................................ 348 13.2.2 Bus Control Register 2 (BCR2) ............................................................................ 357 13.2.3 Bus Control Register 3 (BCR3) (SH7751R Only)................................................ 359 13.2.4 Bus Control Register 4 (BCR4) (SH7751R Only)................................................ 361 13.2.5 Wait Control Register 1 (WCR1) ......................................................................... 363 13.2.6 Wait Control Register 2 (WCR2) ......................................................................... 366 13.2.7 Wait Control Register 3 (WCR3) ......................................................................... 374 13.2.8 Memory Control Register (MCR)......................................................................... 376 13.2.9 PCMCIA Control Register (PCR) ........................................................................ 383 13.2.10 Synchronous DRAM Mode Register (SDMR) ..................................................... 386 13.2.11 Refresh Timer Control/Status Register (RTCSR)................................................. 388 13.2.12 Refresh Timer Counter (RTCNT)......................................................................... 390 Page xx of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 13.2.13 Refresh Time Constant Register (RTCOR) .......................................................... 391 13.2.14 Refresh Count Register (RFCR) ........................................................................... 392 13.2.15 Notes on Accessing Refresh Control Registers .................................................... 392 13.3 Operation ........................................................................................................................... 393 13.3.1 Endian/Access Size and Data Alignment.............................................................. 393 13.3.2 Areas ..................................................................................................................... 400 13.3.3 SRAM Interface.................................................................................................... 405 13.3.4 DRAM Interface ................................................................................................... 413 13.3.5 Synchronous DRAM Interface ............................................................................. 427 13.3.6 Burst ROM Interface ............................................................................................ 457 13.3.7 PCMCIA Interface................................................................................................ 460 13.3.8 MPX Interface....................................................................................................... 471 13.3.9 Byte Control SRAM Interface .............................................................................. 485 13.3.10 Waits between Access Cycles............................................................................... 489 13.3.11 Bus Arbitration ..................................................................................................... 490 13.3.12 Master Mode ......................................................................................................... 493 13.3.13 Slave Mode ........................................................................................................... 494 13.3.14 Cooperation between Master and Slave................................................................ 495 13.3.15 Notes on Usage ..................................................................................................... 495 Section 14 Direct Memory Access Controller (DMAC) ...................................497 14.1 Overview............................................................................................................................ 497 14.1.1 Features................................................................................................................. 497 14.1.2 Block Diagram (SH7751) ..................................................................................... 500 14.1.3 Pin Configuration (SH7751) ................................................................................. 501 14.1.4 Register Configuration (SH7751) ......................................................................... 502 14.2 Register Descriptions ......................................................................................................... 504 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ........................................... 504 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)................................... 505 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3).......................... 506 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3).................................... 507 14.2.5 DMA Operation Register (DMAOR) ................................................................... 515 14.3 Operation ........................................................................................................................... 517 14.3.1 DMA Transfer Procedure ..................................................................................... 517 14.3.2 DMA Transfer Requests ....................................................................................... 520 14.3.3 Channel Priorities ................................................................................................. 523 14.3.4 Types of DMA Transfer........................................................................................ 526 14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 535 14.3.6 Ending DMA Transfer .......................................................................................... 549 14.4 Examples of Use ................................................................................................................ 552 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xxi of liv 14.5 14.6 14.7 14.8 14.9 14.4.1 Examples of Transfer between External Memory and an External Device with DACK........................................................................................................... 552 On-Demand Data Transfer Mode (DDT Mode) ................................................................ 553 14.5.1 Operation .............................................................................................................. 553 14.5.2 Pins in DDT Mode................................................................................................ 555 14.5.3 Transfer Request Acceptance on Each Channel ................................................... 558 14.5.4 Notes on Use of DDT Module .............................................................................. 580 Configuration of the DMAC (SH7751R)........................................................................... 583 14.6.1 Block Diagram of the DMAC............................................................................... 583 14.6.2 Pin Configuration (SH7751R) .............................................................................. 584 14.6.3 Register Configuration (SH7751R) ...................................................................... 585 Register Descriptions (SH7751R)...................................................................................... 588 14.7.1 DMA Source Address Registers 0−7 (SAR0−SAR7)........................................... 588 14.7.2 DMA Destination Address Registers 0−7 (DAR0−DAR7) .................................. 588 14.7.3 DMA Transfer Count Registers 0−7 (DMATCR0−DMATCR7) ......................... 589 14.7.4 DMA Channel Control Registers 0−7 (CHCR0−CHCR7) ................................... 589 14.7.5 DMA Operation Register (DMAOR) ................................................................... 593 Operation (SH7751R) ........................................................................................................ 595 14.8.1 Channel Specification for a Normal DMA Transfer............................................. 595 14.8.2 Channel Specification for DDT-Mode DMA Transfer ......................................... 595 14.8.3 Transfer Channel Notification in DDT Mode....................................................... 596 14.8.4 Clearing Request Queues by DTR Format ........................................................... 597 14.8.5 Interrupt-Request Codes ....................................................................................... 597 Usage Notes ....................................................................................................................... 600 Section 15 Serial Communication Interface (SCI)............................................ 603 15.1 Overview............................................................................................................................ 603 15.1.1 Features................................................................................................................. 603 15.1.2 Block Diagram...................................................................................................... 605 15.1.3 Pin Configuration.................................................................................................. 606 15.1.4 Register Configuration.......................................................................................... 606 15.2 Register Descriptions......................................................................................................... 607 15.2.1 Receive Shift Register (SCRSR1) ........................................................................ 607 15.2.2 Receive Data Register (SCRDR1) ........................................................................ 607 15.2.3 Transmit Shift Register (SCTSR1) ....................................................................... 608 15.2.4 Transmit Data Register (SCTDR1)....................................................................... 608 15.2.5 Serial Mode Register (SCSMR1).......................................................................... 609 15.2.6 Serial Control Register (SCSCR1)........................................................................ 611 15.2.7 Serial Status Register (SCSSR1) .......................................................................... 615 15.2.8 Serial Port Register (SCSPTR1) ........................................................................... 619 Page xxii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 15.2.9 Bit Rate Register (SCBRR1) ................................................................................ 623 15.3 Operation ........................................................................................................................... 631 15.3.1 Overview............................................................................................................... 631 15.3.2 Operation in Asynchronous Mode ........................................................................ 633 15.3.3 Multiprocessor Communication Function............................................................. 644 15.3.4 Operation in Synchronous Mode .......................................................................... 655 15.4 SCI Interrupt Sources and DMAC ..................................................................................... 665 15.5 Usage Notes ....................................................................................................................... 666 Section 16 Serial Communication Interface with FIFO (SCIF) ........................671 16.1 Overview............................................................................................................................ 671 16.1.1 Features................................................................................................................. 671 16.1.2 Block Diagram...................................................................................................... 673 16.1.3 Pin Configuration.................................................................................................. 674 16.1.4 Register Configuration.......................................................................................... 674 16.2 Register Descriptions ......................................................................................................... 675 16.2.1 Receive Shift Register (SCRSR2)......................................................................... 675 16.2.2 Receive FIFO Data Register (SCFRDR2) ............................................................ 675 16.2.3 Transmit Shift Register (SCTSR2) ....................................................................... 676 16.2.4 Transmit FIFO Data Register (SCFTDR2) ........................................................... 676 16.2.5 Serial Mode Register (SCSMR2).......................................................................... 677 16.2.6 Serial Control Register (SCSCR2)........................................................................ 679 16.2.7 Serial Status Register (SCFSR2) .......................................................................... 682 16.2.8 Bit Rate Register (SCBRR2) ................................................................................ 688 16.2.9 FIFO Control Register (SCFCR2) ........................................................................ 689 16.2.10 FIFO Data Count Register (SCFDR2) .................................................................. 692 16.2.11 Serial Port Register (SCSPTR2) ........................................................................... 693 16.2.12 Line Status Register (SCLSR2) ............................................................................ 700 16.3 Operation ........................................................................................................................... 701 16.3.1 Overview............................................................................................................... 701 16.3.2 Serial Operation .................................................................................................... 703 16.4 SCIF Interrupt Sources and the DMAC ............................................................................. 713 16.5 Usage Notes ....................................................................................................................... 714 Section 17 Smart Card Interface ........................................................................719 17.1 Overview............................................................................................................................ 719 17.1.1 Features................................................................................................................. 719 17.1.2 Block Diagram...................................................................................................... 720 17.1.3 Pin Configuration.................................................................................................. 721 17.1.4 Register Configuration.......................................................................................... 721 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xxiii of liv 17.2 Register Descriptions......................................................................................................... 722 17.2.1 Smart Card Mode Register (SCSCMR1) .............................................................. 722 17.2.2 Serial Mode Register (SCSMR1).......................................................................... 723 17.2.3 Serial Control Register (SCSCR1)........................................................................ 724 17.2.4 Serial Status Register (SCSSR1) .......................................................................... 725 17.3 Operation ........................................................................................................................... 726 17.3.1 Overview .............................................................................................................. 726 17.3.2 Pin Connections .................................................................................................... 727 17.3.3 Data Format .......................................................................................................... 728 17.3.4 Register Settings ................................................................................................... 729 17.3.5 Clock..................................................................................................................... 731 17.3.6 Data Transfer Operations...................................................................................... 734 17.4 Usage Notes ....................................................................................................................... 741 Section 18 I/O Ports........................................................................................... 747 18.1 Overview............................................................................................................................ 747 18.1.1 Features................................................................................................................. 747 18.1.2 Block Diagrams .................................................................................................... 748 18.1.3 Pin Configuration.................................................................................................. 755 18.1.4 Register Configuration.......................................................................................... 758 18.2 Register Descriptions......................................................................................................... 759 18.2.1 Port Control Register A (PCTRA)........................................................................ 759 18.2.2 Port Data Register A (PDTRA) ............................................................................ 760 18.2.3 Port Control Register B (PCTRB) ........................................................................ 761 18.2.4 Port Data Register B (PDTRB)............................................................................. 762 18.2.5 GPIO Interrupt Control Register (GPIOIC).......................................................... 763 18.2.6 Serial Port Register (SCSPTR1) ........................................................................... 764 18.2.7 Serial Port Register (SCSPTR2) ........................................................................... 766 Section 19 Interrupt Controller (INTC)............................................................. 769 19.1 Overview............................................................................................................................ 769 19.1.1 Features................................................................................................................. 769 19.1.2 Block Diagram...................................................................................................... 769 19.1.3 Pin Configuration.................................................................................................. 771 19.1.4 Register Configuration.......................................................................................... 771 19.2 Interrupt Sources................................................................................................................ 772 19.2.1 NMI Interrupt........................................................................................................ 772 19.2.2 IRL Interrupts ....................................................................................................... 773 19.2.3 On-Chip Peripheral Module Interrupts ................................................................. 775 19.2.4 Interrupt Exception Handling and Priority............................................................ 776 Page xxiv of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 19.3 Register Descriptions ......................................................................................................... 780 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ................................................ 780 19.3.2 Interrupt Control Register (ICR)........................................................................... 781 19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00) .................................... 783 19.3.4 Interrupt Factor Register 00 (INTREQ00)............................................................ 784 19.3.5 Interrupt Mask Register 00 (INTMSK00)............................................................. 784 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) ........................................... 785 19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation ........................... 786 19.4 INTC Operation ................................................................................................................. 787 19.4.1 Interrupt Operation Sequence ............................................................................... 787 19.4.2 Multiple Interrupts ................................................................................................ 789 19.4.3 Interrupt Masking with MAI Bit........................................................................... 789 19.5 Interrupt Response Time.................................................................................................... 790 19.6 Usage Notes ....................................................................................................................... 791 19.6.1 NMI Interrupts (SH7751 Only)............................................................................. 791 Section 20 User Break Controller (UBC) ..........................................................795 20.1 Overview............................................................................................................................ 795 20.1.1 Features................................................................................................................. 795 20.1.2 Block Diagram...................................................................................................... 796 20.2 Register Descriptions ......................................................................................................... 798 20.2.1 Access to UBC Registers ...................................................................................... 798 20.2.2 Break Address Register A (BARA) ...................................................................... 799 20.2.3 Break ASID Register A (BASRA)........................................................................ 800 20.2.4 Break Address Mask Register A (BAMRA)......................................................... 800 20.2.5 Break Bus Cycle Register A (BBRA)................................................................... 801 20.2.6 Break Address Register B (BARB) ...................................................................... 803 20.2.7 Break ASID Register B (BASRB) ........................................................................ 803 20.2.8 Break Address Mask Register B (BAMRB) ......................................................... 803 20.2.9 Break Data Register B (BDRB) ............................................................................ 803 20.2.10 Break Data Mask Register B (BDMRB)............................................................... 804 20.2.11 Break Bus Cycle Register B (BBRB) ................................................................... 805 20.2.12 Break Control Register (BRCR) ........................................................................... 805 20.3 Operation ........................................................................................................................... 808 20.3.1 Explanation of Terms Relating to Accesses.......................................................... 808 20.3.2 Explanation of Terms Relating to Instruction Intervals ........................................ 808 20.3.3 User Break Operation Sequence ........................................................................... 809 20.3.4 Instruction Access Cycle Break ............................................................................ 810 20.3.5 Operand Access Cycle Break................................................................................ 811 20.3.6 Condition Match Flag Setting............................................................................... 812 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xxv of liv 20.3.7 Program Counter (PC) Value Saved ..................................................................... 812 20.3.8 Contiguous A and B Settings for Sequential Conditions ...................................... 813 20.3.9 Usage Notes .......................................................................................................... 814 20.4 User Break Debug Support Function ................................................................................. 816 20.5 Examples of Use ................................................................................................................ 818 20.6 User Break Controller Stop Function................................................................................. 820 20.6.1 Transition to User Break Controller Stopped State............................................... 820 20.6.2 Cancelling the User Break Controller Stopped State............................................ 820 20.6.3 Examples of Stopping and Restarting the User Break Controller......................... 821 Section 21 High-performance User Debug Interface (H-UDI) ........................ 823 21.1 Overview............................................................................................................................ 823 21.1.1 Features................................................................................................................. 823 21.1.2 Block Diagram...................................................................................................... 823 21.1.3 Pin Configuration.................................................................................................. 825 21.1.4 Register Configuration.......................................................................................... 826 21.2 Register Descriptions......................................................................................................... 827 21.2.1 Instruction Register (SDIR) .................................................................................. 827 21.2.2 Data Register (SDDR) .......................................................................................... 828 21.2.3 Bypass Register (SDBPR) .................................................................................... 828 21.2.4 Interrupt Factor Register (SDINT)........................................................................ 829 21.2.5 Boundary Scan Register (SDBSR) ....................................................................... 829 21.3 Operation ........................................................................................................................... 843 21.3.1 TAP Control ......................................................................................................... 843 21.3.2 H-UDI Reset ......................................................................................................... 844 21.3.3 H-UDI Interrupt .................................................................................................... 844 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) ............................. 845 21.4 Usage Notes ....................................................................................................................... 845 Section 22 PCI Controller (PCIC)..................................................................... 847 22.1 Overview............................................................................................................................ 847 22.1.1 Features................................................................................................................. 847 22.1.2 Block Diagram...................................................................................................... 848 22.1.3 Pin Configuration.................................................................................................. 849 22.1.4 Register Configuration.......................................................................................... 850 22.2 PCIC Register Descriptions ............................................................................................... 856 22.2.1 PCI Configuration Register 0 (PCICONF0) ......................................................... 856 22.2.2 PCI Configuration Register 1 (PCICONF1) ......................................................... 857 22.2.3 PCI Configuration Register 2 (PCICONF2) ......................................................... 863 22.2.4 PCI Configuration Register 3 (PCICONF3) ......................................................... 865 Page xxvi of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 22.2.5 22.2.6 22.2.7 22.2.8 PCI Configuration Register 4 (PCICONF4) ......................................................... 867 PCI Configuration Register 5 (PCICONF5) ......................................................... 869 PCI Configuration Register 6 (PCICONF6) ......................................................... 871 PCI Configuration Register 7 (PCICONF7) to PCI Configuration Register 10 (PCICONF10)....................................................................................................... 873 22.2.9 PCI Configuration Register 11 (PCICONF11) ..................................................... 874 22.2.10 PCI Configuration Register 12 (PCICONF12) ..................................................... 875 22.2.11 PCI Configuration Register 13 (PCICONF13) ..................................................... 875 22.2.12 PCI Configuration Register 14 (PCICONF14) ..................................................... 876 22.2.13 PCI Configuration Register 15 (PCICONF15) ..................................................... 877 22.2.14 PCI Configuration Register 16 (PCICONF16) ..................................................... 879 22.2.15 PCI Configuration Register 17 (PCICONF17) ..................................................... 881 22.2.16 Reserved Area....................................................................................................... 883 22.2.17 PCI Control Register (PCICR).............................................................................. 884 22.2.18 PCI Local Space Register [1:0] (PCILSR [1:0])................................................... 888 22.2.19 PCI Local Address Register [1:0] (PCILAR [1:0])............................................... 890 22.2.20 PCI Interrupt Register (PCIINT)........................................................................... 892 22.2.21 PCI Interrupt Mask Register (PCIINTM) ............................................................. 895 22.2.22 PCI Address Data Register at Error (PCIALR) .................................................... 897 22.2.23 PCI Command Data Register at Error (PCICLR) ................................................. 898 22.2.24 PCI Arbiter Interrupt Register (PCIAINT) ........................................................... 900 22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM).............................................. 902 22.2.26 PCI Error Bus Master Data Register (PCIBMLR)................................................ 903 22.2.27 PCI DMA Transfer Arbitration Register (PCIDMABT) ...................................... 904 22.2.28 PCI DMA Transfer PCI Address Register [3:0] (PCIDPA [3:0])......................... 905 22.2.29 PCI DMA Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0]) ...... 907 22.2.30 PCI DMA Transfer Counter Register [3:0] (PCIDTC [3:0]) ................................ 908 22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0]) ............................................... 910 22.2.32 PIO Address Register (PCIPAR) .......................................................................... 913 22.2.33 Memory Space Base Register (PCIMBR)............................................................. 915 22.2.34 I/O Space Base Register (PCIIOBR) .................................................................... 917 22.2.35 PCI Power Management Interrupt Register (PCIPINT) ....................................... 918 22.2.36 PCI Power Management Interrupt Mask Register (PCIPINTM) .......................... 919 22.2.37 PCI Clock Control Register (PCICLKR).............................................................. 920 22.2.38 PCIC-BSC Registers............................................................................................. 921 22.2.39 Port Control Register (PCIPCTR)......................................................................... 923 22.2.40 Port Data Register (PCIPDTR) ............................................................................. 926 22.2.41 PIO Data Register (PCIPDR)................................................................................ 927 22.3 Description of Operation.................................................................................................... 928 22.3.1 Operating Modes................................................................................................... 928 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xxvii of liv 22.4 22.5 22.6 22.7 22.8 22.9 22.10 22.11 22.12 22.3.2 PCI Commands..................................................................................................... 929 22.3.3 PCIC Initialization ................................................................................................ 930 22.3.4 Local Register Access........................................................................................... 931 22.3.5 Host Functions ...................................................................................................... 931 22.3.6 PCI Bus Arbitration in Non-host Mode ................................................................ 934 22.3.7 PIO Transfers........................................................................................................ 934 22.3.8 Target Transfers.................................................................................................... 937 22.3.9 DMA Transfers..................................................................................................... 940 22.3.10 Transfer Contention within PCIC ......................................................................... 946 22.3.11 PCI Bus Basic Interface........................................................................................ 947 Endians .............................................................................................................................. 959 22.4.1 Internal Bus (Peripheral Bus) Interface for Peripheral Modules........................... 959 22.4.2 Endian Control for Local Bus ............................................................................... 961 22.4.3 Endian Control in DMA Transfers ....................................................................... 961 22.4.4 Endian Control in Target Transfers (Memory Read/Memory Write) ................... 963 22.4.5 Endian Control in Target Transfers (I/O Read/I/O Write).................................... 966 22.4.6 Endian Control in Target Transfers (Configuration Read/Configuration Write)........................................................... 966 Resetting ............................................................................................................................ 968 Interrupts............................................................................................................................ 969 22.6.1 Interrupts from PCIC to CPU ............................................................................... 969 22.6.2 Interrupts from External PCI Devices................................................................... 970 22.6.3 INTA..................................................................................................................... 971 Error Detection .................................................................................................................. 971 PCIC Clock........................................................................................................................ 971 Power Management ........................................................................................................... 972 22.9.1 Power Management Overview.............................................................................. 972 22.9.2 Stopping the Clock ............................................................................................... 973 22.9.3 Compatibility with Standby and Sleep ................................................................. 976 Port Functions .................................................................................................................... 976 Version Management......................................................................................................... 977 Usage Notes ....................................................................................................................... 977 22.12.1 Notes on Arbiter Interrupt Usage (SH7751 Only) ................................................ 977 22.12.2 Notes on I/O Read and I/O Write Commands (SH7751 Only)............................. 980 22.12.3 Notes on Configuration-Read and Configuration-Write Commands (SH7751 Only)...................................................................................................... 980 22.12.4 Notes on Target Read/Write Cycle Timing (SH7751 Only)................................. 980 22.12.5 Notes on Parity Error Detection during Master Access ........................................ 980 Page xxviii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Section 23 Electrical Characteristics .................................................................983 23.1 Absolute Maximum Ratings .............................................................................................. 983 23.2 DC Characteristics ............................................................................................................. 984 23.3 AC Characteristics ............................................................................................................. 996 23.3.1 Clock and Control Signal Timing ......................................................................... 998 23.3.2 Control Signal Timing ........................................................................................ 1012 23.3.3 Bus Timing ......................................................................................................... 1016 23.3.4 Peripheral Module Signal Timing....................................................................... 1067 23.3.5 AC Characteristic Test Conditions ..................................................................... 1081 23.3.6 Change in Delay Time Based on Load Capacitance ........................................... 1082 Appendix A Address List ................................................................................1083 Appendix B Package Dimensions....................................................................1091 Appendix C Mode Pin Settings .......................................................................1095 Appendix D Pin Functions...............................................................................1099 D.1 D.2 D.3 Pin States.......................................................................................................................... 1099 Handling of Unused Pins ................................................................................................. 1104 Note on Pin Processing .................................................................................................... 1105 Appendix E Synchronous DRAM Address Multiplexing Tables...................1107 Appendix F Instruction Prefetching and Its Side Effects.................................1119 Appendix G Power-On and Power-Off Procedures.........................................1121 G.1 G.2 G.3 Power-On Stipulations ..................................................................................................... 1121 Power-Off Stipulations .................................................................................................... 1121 Common Stipulations for Power-On and Power-Off ....................................................... 1124 Appendix H Product Lineup ............................................................................1125 Appendix I Version Registers..........................................................................1127 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xxix of liv Page xxx of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Figures Section 1 Overview Figure 1.1 Block Diagram of SH7751/SH7751R Group Functions ............................................. 9 Figure 1.2 Pin Arrangement (256-Pin QFP)............................................................................... 10 Figure 1.3 Pin Arrangement (256-Pin BGA).............................................................................. 11 Figure 1.4 Pin Arrangement (292-Pin BGA).............................................................................. 12 Section 2 Programming Model Figure 2.1 Data Formats ............................................................................................................. 47 Figure 2.2 CPU Register Configuration in Each Processor Mode.............................................. 50 Figure 2.3 General Registers ...................................................................................................... 52 Figure 2.4 Floating-Point Registers............................................................................................ 54 Figure 2.5 Data Formats In Memory .......................................................................................... 60 Figure 2.6 Processor State Transitions ....................................................................................... 61 Section 3 Memory Management Unit (MMU) Figure 3.1 Role of the MMU ...................................................................................................... 65 Figure 3.2 MMU-Related Registers ........................................................................................... 67 Figure 3.3 Physical Address Space (MMUCR.AT = 0) ............................................................. 71 Figure 3.4 P4 Area...................................................................................................................... 72 Figure 3.5 External Memory Space ............................................................................................ 74 Figure 3.6 Virtual Address Space (MMUCR.AT = 1)................................................................ 75 Figure 3.7 UTLB Configuration ................................................................................................. 78 Figure 3.8 Relationship between Page Size and Address Format............................................... 79 Figure 3.9 ITLB Configuration................................................................................................... 82 Figure 3.10 Flowchart of Memory Access Using UTLB ............................................................. 83 Figure 3.11 Flowchart of Memory Access Using ITLB ............................................................... 84 Figure 3.12 Operation of LDTLB Instruction .............................................................................. 86 Figure 3.13 Memory-Mapped ITLB Address Array..................................................................... 95 Figure 3.14 Memory-Mapped ITLB Data Array 1 ....................................................................... 96 Figure 3.15 Memory-Mapped ITLB Data Array 2 ....................................................................... 97 Figure 3.16 Memory-Mapped UTLB Address Array ................................................................... 98 Figure 3.17 Memory-Mapped UTLB Data Array 1...................................................................... 99 Figure 3.18 Memory-Mapped UTLB Data Array 2.................................................................... 100 Section 4 Caches Figure 4.1 Cache and Store Queue Control Registers (CCR)................................................... 103 Figure 4.2 Configuration of Operand Cache (SH7751)............................................................ 106 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xxxi of liv Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 4.7 Figure 4.8 Figure 4.9 Figure 4.10 Figure 4.11 Figure 4.12 Figure 4.13 Figure 4.14 Figure 4.15 Figure 4.16 Configuration of Operand Cache (SH7751R) ......................................................... 107 Configuration of Write-Back Buffer ....................................................................... 111 Configuration of Write-Through Buffer.................................................................. 111 Configuration of Instruction Cache (SH7751) ........................................................ 117 Configuration of Instruction Cache (SH7751R)...................................................... 118 Memory-Mapped IC Address Array ....................................................................... 121 Memory-Mapped IC Data Array............................................................................. 122 Memory-Mapped OC Address Array...................................................................... 124 Memory-Mapped OC Data Array ........................................................................... 125 Memory-Mapped IC Address Array ....................................................................... 126 Memory-Mapped IC Data Array............................................................................. 127 Memory-Mapped OC Address Array...................................................................... 129 Memory-Mapped OC Data Array ........................................................................... 130 Store Queue Configuration...................................................................................... 131 Section 5 Exceptions Figure 5.1 Register Bit Configurations..................................................................................... 138 Figure 5.2 Instruction Execution and Exception Handling....................................................... 143 Figure 5.3 Example of General Exception Acceptance Order.................................................. 145 Section 6 Floating-Point Unit Figure 6.1 Format of Single-Precision Floating-Point Number................................................ 173 Figure 6.2 Format of Double-Precision Floating-Point Number .............................................. 174 Figure 6.3 Single-Precision NaN Bit Pattern............................................................................ 176 Figure 6.4 Floating-Point Registers.......................................................................................... 178 Section 8 Pipelining Figure 8.1 Basic Pipelines ........................................................................................................ 212 Figure 8.2 Instruction Execution Patterns ................................................................................ 213 Figure 8.3 Examples of Pipelined Execution ........................................................................... 225 Section 9 Power-Down Modes Figure 9.1 STATUS Output in Power-On Reset ...................................................................... 255 Figure 9.2 STATUS Output in Manual Reset .......................................................................... 255 Figure 9.3 STATUS Output in Standby → Interrupt Sequence ............................................... 256 Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence ................................... 256 Figure 9.5 STATUS Output in Standby → Manual Reset Sequence ....................................... 257 Figure 9.6 STATUS Output in Sleep → Interrupt Sequence.................................................... 257 Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence ....................................... 258 Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence............................................ 259 Page xxxii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 9.14 Figure 9.15 STATUS Output in Deep Sleep → Interrupt Sequence .......................................... 260 STATUS Output in Deep Sleep → Power-On Reset Sequence .............................. 260 STATUS Output in Deep Sleep → Manual Reset Sequence .................................. 261 Hardware Standby Mode Timing (When CA = Low in Normal Operation)........... 262 Hardware Standby Mode Timing (When CA = Low in WDT Operation) .............. 263 Timing When Power Other than VDD-RTC Is Off ................................................ 263 Timing When VDD-RTC Power Is Off → On........................................................ 264 Section 10 Clock Oscillation Circuits Figure 10.1 (1) Block Diagram of CPG (SH7751) .................................................................... 269 Figure 10.1 (2) Block Diagram of CPG (SH7751R).................................................................. 270 Figure 10.2 Block Diagram of WDT.......................................................................................... 280 Figure 10.3 Writing to WTCNT and WTCSR............................................................................ 284 Figure 10.4 Points for Attention when Using Crystal Resonator ............................................... 287 Figure 10.5 Points for Attention when Using PLL Oscillator Circuit ........................................ 288 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Realtime Clock (RTC) Block Diagram of RTC ........................................................................................... 292 Examples of Time Setting Procedures .................................................................... 309 Examples of Time Reading Procedures .................................................................. 311 Example of Use of Alarm Function ........................................................................ 312 Example of Crystal Oscillation Circuit Connection ................................................ 314 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Timer Unit (TMU) Block Diagram of TMU .......................................................................................... 316 Example of Count Operation Setting Procedure ..................................................... 328 TCNT Auto-Reload Operation................................................................................ 329 Count Timing when Operating on Internal Clock ................................................... 329 Count Timing when Operating on External Clock.................................................. 330 Count Timing when Operating on On-Chip RTC Output Clock............................. 330 Operation Timing when Using Input Capture Function .......................................... 331 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Bus State Controller (BSC) Block Diagram of BSC ........................................................................................... 337 Correspondence between Virtual Address Space and External Memory Space...... 341 External Memory Space Allocation ........................................................................ 343 Example of RDY Sampling Timing at which BCR4 Is Set (Two Wait Cycles Are Inserted by WCR2) ............................................................ 362 Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR.................................................. 393 Figure 13.6 Basic Timing of SRAM Interface ........................................................................... 406 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xxxiii of liv Figure 13.7 Figure 13.8 Figure 13.9 Figure 13.10 Figure 13.11 Figure 13.12 Example of 32-Bit Data Width SRAM Connection.............................................. 407 Example of 16-Bit Data Width SRAM Connection.............................................. 408 Example of 8-Bit Data Width SRAM Connection................................................ 409 SRAM Interface Wait Timing (Software Wait Only)........................................... 410 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal)......... 411 SRAM Interface Read Strobe Negate Timing (AnS = 1, AnW = 4, and AnH = 2)....................................................................... 412 Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3).............................. 413 Figure 13.14 Basic DRAM Access Timing ............................................................................... 415 Figure 13.15 DRAM Wait State Timing.................................................................................... 416 Figure 13.16 DRAM Burst Access Timing................................................................................ 417 Figure 13.17 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1) .......................... 418 Figure 13.18 Burst Access Timing in DRAM EDO Mode ........................................................ 419 Figure 13.19 (1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, AnW = 0)................................................................. 420 Figure 13.19 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0)................................................................. 421 Figure 13.19 (3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, AnW = 0) ........................................................................ 422 Figure 13.19 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0) ........................................................................ 423 Figure 13.20 CAS-Before-RAS Refresh Operation ................................................................... 424 Figure 13.21 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) ............ 425 Figure 13.22 DRAM Self-Refresh Cycle Timing ...................................................................... 426 Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) ......... 428 Figure 13.24 Basic Timing for Synchronous DRAM Burst Read.............................................. 431 Figure 13.25 Basic Timing for Synchronous DRAM Single Read ............................................ 433 Figure 13.26 Basic Timing for Synchronous DRAM Burst Write............................................. 434 Figure 13.27 Basic Timing for Synchronous DRAM Single Write ........................................... 436 Figure 13.28 Burst Read Timing................................................................................................ 438 Figure 13.29 Burst Read Timing (RAS Down, Same Row Address) ........................................ 439 Figure 13.30 Burst Read Timing (RAS Down, Different Row Addresses) ............................... 440 Figure 13.31 Burst Write Timing............................................................................................... 441 Figure 13.32 Burst Write Timing (Same Row Address)............................................................ 442 Figure 13.33 Burst Write Timing (Different Row Addresses)................................................... 443 Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle .................................................................................................. 446 Figure 13.35 Auto-Refresh Operation........................................................................................ 448 Figure 13.36 Synchronous DRAM Auto-Refresh Timing ......................................................... 448 Figure 13.37 Synchronous DRAM Self-Refresh Timing........................................................... 450 Page xxxiv of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Figure 13.38 (1) Synchronous DRAM Mode Write Timing (PALL) .......................................... 452 Figure 13.38 (2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ................ 453 Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8) ..... 455 Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM ....................................... 456 Figure 13.41 Burst ROM Basic Access Timing......................................................................... 458 Figure 13.42 Burst ROM Wait Access Timing .......................................................................... 459 Figure 13.43 Burst ROM Wait Access Timing .......................................................................... 460 Figure 13.44 Example of PCMCIA Interface............................................................................. 464 Figure 13.45 Basic Timing for PCMCIA Memory Card Interface ............................................ 465 Figure 13.46 Wait Timing for PCMCIA Memory Card Interface.............................................. 466 Figure 13.47 PCMCIA Space Allocation................................................................................... 467 Figure 13.48 Basic Timing for PCMCIA I/O Card Interface..................................................... 468 Figure 13.49 Wait Timing for PCMCIA I/O Card Interface...................................................... 469 Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface............................. 470 Figure 13.51 Example of 32-Bit Data Width MPX Connection ................................................ 472 Figure 13.52 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait) ....... 473 Figure 13.53 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted).. 474 Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait) ...... 475 Figure 13.55 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted) 476 Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait) ........ 477 Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control) . 478 Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait)........ 479 Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control) 480 Figure 13.60 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) ................................................ 481 Figure 13.61 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) ................................. 482 Figure 13.62 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) ................................................ 483 Figure 13.63 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) ................................. 484 Figure 13.64 Example of 32-Bit Data Width Byte Control SRAM ........................................... 485 Figure 13.65 Byte Control SRAM Basic Read Cycle (No Wait) ............................................... 486 Figure 13.66 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)...................... 487 Figure 13.67 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) ............................................................. 488 Figure 13.68 Waits between Access Cycles............................................................................... 490 Figure 13.69 Arbitration Sequence ............................................................................................ 492 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xxxv of liv Section 14 Direct Memory Access Controller (DMAC) Figure 14.1 Block Diagram of DMAC..................................................................................... 500 Figure 14.2 DMAC Transfer Flowchart................................................................................... 519 Figure 14.3 Round Robin Mode............................................................................................... 524 Figure 14.4 Example of Changes in Priority Order in Round Robin Mode ............................. 525 Figure 14.5 Data Flow in Single Address Mode ...................................................................... 527 Figure 14.6 DMA Transfer Timing in Single Address Mode .................................................. 528 Figure 14.7 Operation in Dual Address Mode ......................................................................... 529 Figure 14.8 Example of Transfer Timing in Dual Address Mode............................................ 530 Figure 14.9 Example of DMA Transfer in Cycle Steal Mode.................................................. 531 Figure 14.10 Example of DMA Transfer in Burst Mode ........................................................... 531 Figure 14.11 Bus Handling with Two DMAC Channels Operating .......................................... 535 Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle)............................................................... 538 Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle)................................................................ 539 Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle)............................................................... 540 Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle)................................................................ 541 Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → External Bus..................................................................................................... 542 Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI (Level Detection) .................................................................................................. 543 Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection) .................................................................................................. 544 Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection)................................................................................................... 545 Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection) .................................................................................................. 546 Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection)................................................................................................... 547 Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM: Row Hit Write) ..................................................................................................... 548 Figure 14.23 On-Demand Transfer Mode Block Diagram ........................................................ 553 Figure 14.24 System Configuration in On-Demand Data Transfer Mode ................................. 555 Figure 14.25 Data Transfer Request Format .............................................................................. 556 Page xxxvi of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Figure 14.26 Single Address Mode/Synchronous DRAM → External Device Longword Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD = 1, CAS latency = 3, TPC = 3) ................................................................. 559 Figure 14.27 Single Address Mode/External Device → Synchronous DRAM Longword Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD = 1, TRWL = 2, TPC = 1) .......................................................................... 560 Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer .......... 561 Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ......................................... 562 Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ......................................... 562 Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer .................................................... 563 Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer .................................................... 564 Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer).... 565 Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer)................................................................ 566 Figure 14.35 Read from Synchronous DRAM Precharge Bank................................................. 567 Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss)..................... 567 Figure 14.37 Read from Synchronous DRAM (Row Hit).......................................................... 568 Figure 14.38 Write to Synchronous DRAM Precharge Bank .................................................... 568 Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) ........................ 569 Figure 14.40 Write to Synchronous DRAM (Row Hit) ............................................................. 569 Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ......................................... 570 Figure 14.42 DDT Mode Setting................................................................................................ 571 Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device → External Bus Data Transfer.............................................................................. 571 Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus → External Device Data Transfer......................................................................... 572 Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus → External Device Data Transfer ................................. 572 Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer ................................. 573 Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1–3 Using Data Bus............................................................. 574 Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus → External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus ........................................................................................ 575 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xxxvii of liv Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer/Direct Data Transfer Request to Channel 2............................................ 576 Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer/Direct Data Transfer Request to Channel 2............................................ 577 Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 ...... 578 Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 ...... 579 Figure 14.53 Block Diagram of the DMAC............................................................................... 583 Figure 14.54 DTR Format (Transfer Request Format) (SH7751R) ........................................... 594 Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ......................................... 598 Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus → External Device/ 32-Byte Block Transfer/On-Demand Data Transfer on Channel 4....................... 599 Section 15 Serial Communication Interface (SCI) Figure 15.1 Block Diagram of SCI .......................................................................................... 605 Figure 15.2 SCK Pin ................................................................................................................ 621 Figure 15.3 TxD Pin................................................................................................................. 622 Figure 15.4 RxD Pin ................................................................................................................ 622 Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) ............................................... 634 Figure 15.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) .......................................................................................... 636 Figure 15.7 Sample SCI Initialization Flowchart..................................................................... 637 Figure 15.8 Sample Serial Transmission Flowchart ................................................................ 638 Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit).................................................. 640 Figure 15.10 Sample Serial Reception Flowchart (1) ................................................................ 641 Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit).................................................. 644 Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A).......................................... 645 Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart ....................................... 647 Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 649 Figure 15.15 Sample Flowchart of Multiprocessor Serial Reception with Interrupt Generation ............................................................................................................ 651 Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (1) ....................................... 652 Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (2) ....................................... 653 Page xxxviii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Figure 15.17 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ........................................................................ 654 Figure 15.18 Data Format in Synchronous Communication...................................................... 655 Figure 15.19 Sample SCI Initialization Flowchart..................................................................... 657 Figure 15.20 Sample Serial Transmission Flowchart................................................................. 658 Figure 15.21 Example of SCI Transmit Operation .................................................................... 660 Figure 15.22 Sample Serial Reception Flowchart (1) ................................................................ 661 Figure 15.23 Example of SCI Receive Operation ...................................................................... 663 Figure 15.24 Sample Flowchart for Serial Data Transmission and Reception........................... 664 Figure 15.25 Receive Data Sampling Timing in Asynchronous Mode...................................... 668 Figure 15.26 Example of Synchronous Transmission by DMAC.............................................. 669 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.1 Block Diagram of SCIF ........................................................................................ 673 Figure 16.2 MD8/RTS2 Pin ..................................................................................................... 696 Figure 16.3 MD7/CTS2 Pin ..................................................................................................... 697 Figure 16.4 MD1/TxD2 Pin ..................................................................................................... 698 Figure 16.5 MD2/RxD2 Pin ..................................................................................................... 698 Figure 16.6 MD0/SCK2 Pin..................................................................................................... 699 Figure 16.7 Sample SCIF Initialization Flowchart................................................................... 705 Figure 16.8 Sample Serial Transmission Flowchart................................................................. 706 Figure 16.9 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit).................................................. 708 Figure 16.10 Example of Operation Using Modem Control (CTS2) ......................................... 708 Figure 16.11 Sample Serial Reception Flowchart (1) ................................................................ 709 Figure 16.11 Sample Serial Reception Flowchart (2) ................................................................ 710 Figure 16.12 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ........................................................................................................ 712 Figure 16.13 Example of Operation Using Modem Control (RTS2) ......................................... 712 Figure 16.14 Receive Data Sampling Timing in Asynchronous Mode...................................... 716 Section 17 Smart Card Interface Figure 17.1 Block Diagram of Smart Card Interface ............................................................... 720 Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections ............................. 727 Figure 17.3 Smart Card Interface Data Format ........................................................................ 728 Figure 17.4 TEND Generation Timing .................................................................................... 730 Figure 17.5 Sample Start Character Waveforms...................................................................... 731 Figure 17.6 Difference in Clock Output According to GM Bit Setting ................................... 734 Figure 17.7 Sample Initialization Flowchart ............................................................................ 735 Figure 17.8 Sample Transmission Processing Flowchart......................................................... 737 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xxxix of liv Figure 17.9 Figure 17.10 Figure 17.11 Figure 17.12 Figure 17.13 Sample Reception Processing Flowchart.............................................................. 739 Receive Data Sampling Timing in Smart Card Mode .......................................... 741 Retransfer Operation in SCI Receive Mode ......................................................... 743 Retransfer Operation in SCI Transmit Mode........................................................ 743 Procedure for Stopping and Restarting the Clock................................................. 744 Section 18 I/O Ports Figure 18.1 16-Bit Port A......................................................................................................... 748 Figure 18.2 16-Bit Port B......................................................................................................... 749 Figure 18.3 SCK Pin ................................................................................................................ 750 Figure 18.4 TxD Pin................................................................................................................. 751 Figure 18.5 RxD Pin ................................................................................................................ 751 Figure 18.6 MD1/TxD2 Pin ..................................................................................................... 752 Figure 18.7 MD2/RxD2 Pin..................................................................................................... 752 Figure 18.8 MD0/SCK2 Pin..................................................................................................... 753 Figure 18.9 MD7/CTS2 Pin ..................................................................................................... 754 Figure 18.10 MD8/RTS2 Pin ..................................................................................................... 755 Section 19 Interrupt Controller (INTC) Figure 19.1 Block Diagram of INTC ....................................................................................... 770 Figure 19.2 Example of IRL Interrupt Connection .................................................................. 773 Figure 19.3 Interrupt Operation Flowchart .............................................................................. 788 Section 20 User Break Controller (UBC) Figure 20.1 Block Diagram of User Break Controller ............................................................. 796 Figure 20.2 User Break Debug Support Function Flowchart................................................... 817 Section 21 High-performance User Debug Interface (H-UDI) Figure 21.1 Block Diagram of H-UDI Circuit ......................................................................... 824 Figure 21.2 TAP Control State Transition Diagram ................................................................ 843 Figure 21.3 H-UDI Reset ......................................................................................................... 844 Section 22 PCI Controller (PCIC) Figure 22.1 PCIC Block Diagram ............................................................................................ 848 Figure 22.2 PIO Memory Space Access .................................................................................. 936 Figure 22.3 PIO I/O Space Access........................................................................................... 937 Figure 22.4 Local Address Space Accessing Method .............................................................. 938 Figure 22.5 Example of DMA Transfer Control Register Settings.......................................... 942 Figure 22.6 Example of DMA Transfer Flowchart.................................................................. 944 Figure 22.7 Master Write Cycle in Host Mode (Single) .......................................................... 948 Page xl of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Figure 22.8 Master Read Cycle in Host Mode (Single) ........................................................... 949 Figure 22.9 Master Memory Write Cycle in Non-Host Mode (Burst) ..................................... 950 Figure 22.10 Master Memory Read Cycle in Non-Host Mode (Burst) ...................................... 951 Figure 22.11 Target Read Cycle in Non-Host Mode (Single).................................................... 953 Figure 22.12 Target Write Cycle in Non-Host Mode (Single)................................................... 954 Figure 22.13 Target Memory Read Cycle in Host Mode (Burst)............................................... 955 Figure 22.14 Target Memory Write Cycle in Host Mode (Burst).............................................. 956 Figure 22.15 Master Memory Write Cycle in Host Mode (Burst, With Stepping) .................... 957 Figure 22.16 Target Memory Read Cycle in Host Mode (Burst, With Stepping)...................... 958 Figure 22.17 Endian Conversion Modes for Peripheral Bus...................................................... 959 Figure 22.18 Peripheral Bus ↔ PCI Bus Data Alignment......................................................... 960 Figure 22.19 Endian Control for Local Bus ............................................................................... 961 Figure 22.20 Data Alignment at DMA Transfer ........................................................................ 962 Figure 22.21 (1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus) ............. 964 Figure 22.21 (2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus) .......... 965 Figure 22.22 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian) ...... 966 Figure 22.23 Data Alignment at Target Configuration Transfer (Both Big Endian and Little Endian) .................................................................... 967 Figure 22.24 Target Bus Timeout Interrupt Generation Example 1 (Example in which the Target Device Asserts STOP at the Sixteenth Clock Cycle after FRAME Was Asserted)...................................................................... 978 Figure 22.25 Target Bus Timeout Interrupt Generation Example 2 (Example in which the Target Device Takes 8 Clock Cycles to Prepare for the Third Data Transfer) ............................................................................................................... 979 Figure 22.26 Master Bus Timeout Interrupt Generation Example 1 (Example in which the Master Device Prepares the Data and Asserts IRDY at the Eighth Clock Cycle after FRAME Was Asserted)...................................................................... 979 Figure 22.27 Master Bus Timeout Interrupt Generation Example 2 (Example in which the Master Device Takes 8 Clock Cycles to Prepare for the Third Data Transfer following the Second Data Phase).......................................................... 980 Section 23 Electrical Characteristics Figure 23.1 EXTAL Clock Input Timing............................................................................... 1007 Figure 23.2 (1) CKIO Clock Output Timing ........................................................................... 1007 Figure 23.2 (2) CKIO Clock Output Timing ........................................................................... 1007 Figure 23.3 Power-On Oscillation Settling Time................................................................... 1008 Figure 23.4 Standby Return Oscillation Settling Time (Return by RESET or MRESET)..... 1008 Figure 23.5 Power-On Oscillation Settling Time................................................................... 1009 Figure 23.6 Standby Return Oscillation Settling Time (Return by RESET or MRESET)..... 1009 Figure 23.7 Standby Return Oscillation Settling Time (Return by NMI) .............................. 1010 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xli of liv Standby Return Oscillation Settling Time (Return by IRL3–IRL0) ................... 1010 PLL Synchronization Settling Time in Case of RESET, MRESET or NMI Interrupt...................................................................................................... 1011 Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt ............................ 1011 Figure 23.11 Control Signal Timing ........................................................................................ 1014 Figure 23.12 (1) Pin Drive Timing for Reset or Sleep Mode .................................................... 1014 Figure 23.12 (2) Pin Drive Timing for Software Standby Mode ............................................... 1015 Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (No Wait) .................................................. 1020 Figure 23.14 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)................................... 1021 Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait). 1022 Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/ Hold Time Insertion, AnS = 1, AnH = 1) ........................................................... 1023 Figure 23.17 Burst ROM Bus Cycle (No Wait)....................................................................... 1024 Figure 23.18 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait) ................................................................. 1025 Figure 23.19 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1).............................................................................................. 1026 Figure 23.20 Burst ROM Bus Cycle (One Internal Wait + One External Wait)...................... 1027 Figure 23.21 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011)....................................... 1028 Figure 23.22 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011)....................................... 1029 Figure 23.23 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD [1:0] = 01, CAS Latency = 3) ...................................... 1030 Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001, CAS Latency = 3) ............................................................................................... 1031 Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (RASD = 1, CAS Latency = 3) ........................................................................... 1032 Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) .................................... 1033 Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) .................................... 1034 Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RASD = 1, RCD [1:0] = 01, TRWL [2:0] = 010) .................................... 1035 Figure 23.29 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)............................................................................................. 1036 Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL [2:0] = 010) ............................................................... 1037 Figure 23.8 Figure 23.9 Page xlii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Figure 23.31 Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001)........ 1038 Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001). 1039 Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001)..................... 1040 Figure 23.34 (a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL).................. 1041 Figure 23.34 (b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET)..................... 1042 Figure 23.35 DRAM Bus Cycles (1) RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001 (2) RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 010......... 1043 Figure 23.36 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TRC [2:0] = 001) ................................................................................................ 1044 Figure 23.37 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001)................................................................................................. 1045 Figure 23.38 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001)................................................................................................. 1046 Figure 23.39 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width)......................................... 1047 Figure 23.40 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) .................................................................... 1048 Figure 23.41 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) .................................................................... 1049 Figure 23.42 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) ................................................................... 1050 Figure 23.43 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001) ................................................................... 1051 Figure 23.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) ........... 1052 Figure 23.45 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000) .................................................................... 1053 Figure 23.46 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000) .................................................................... 1054 Figure 23.47 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 000, TRC [2:0] = 001) ................................................................ 1055 Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 001, TRC [2:0] = 001) ................................................................................................ 1056 Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001).............................. 1057 Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait ........................................................................................... 1058 Figure 23.51 PCMCIA I/O Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait.............................................................. 1059 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xliii of liv Figure 23.52 PCMCIA I/O Bus Cycle (TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait, Bus Sizing)........................................................................... 1060 Figure 23.53 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait)............................................. 1061 Figure 23.54 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait)....... 1062 Figure 23.55 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data (No Internal Wait) (2) 1st Data (No Internal Wait), 2nd to 8th Data (No Internal Wait + External Wait Control).............................. 1063 Figure 23.56 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 8th Data (No Internal Wait + External Wait Control)........................................................................................ 1064 Figure 23.57 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait).............................. 1065 Figure 23.58 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS [0] = 1, AnH [1:0] = 01).. 1066 Figure 23.59 TCLK Input Timing............................................................................................ 1072 Figure 23.60 RTC Oscillation Settling Time at Power-On ...................................................... 1072 Figure 23.61 SCK Input Clock Timing.................................................................................... 1072 Figure 23.62 SCI I/O Synchronous Mode Clock Timing......................................................... 1073 Figure 23.63 I/O Port Input/Output Timing ............................................................................. 1073 Figure 23.64 (a) DREQ/DRAK Timing .................................................................................... 1073 Figure 23.64 (b) DBREQ/TR Input Timing and BAVL Output Timing ................................... 1074 Figure 23.65 TCK Input Timing .............................................................................................. 1074 Figure 23.66 RESET Hold Timing .......................................................................................... 1075 Figure 23.67 H-UDI Data Transfer Timing ............................................................................. 1075 Figure 23.68 Pin Break Timing................................................................................................ 1075 Figure 23.69 NMI Input Timing .............................................................................................. 1075 Figure 23.70 PCI Clock Input Timing ..................................................................................... 1078 Figure 23.71 Output Signal Timing ......................................................................................... 1078 Figure 23.72 Output Signal Timing ......................................................................................... 1079 Figure 23.73 I/O Port Input/Output Timing ............................................................................. 1080 Figure 23.74 Output Load Circuit............................................................................................ 1081 Figure 23.75 Load Capacitance−Delay Time........................................................................... 1082 Appendix B Package Dimensions Figure B.1 Package Dimensions (256-pin QFP) ..................................................................... 1091 Figure B.2 Package Dimensions (256-pin BGA: Devices Other than HD6417751RBA240HV)...................................................................................... 1092 Page xliv of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Figure B.3 Figure B.4 Package Dimensions (292-pin BGA) .................................................................... 1093 Package Dimensions (256-pin BGA: HD6417751RBA240HV).......................... 1094 Appendix F Instruction Prefetching and Its Side Effects Figure F.1 Instruction Prefetch ............................................................................................... 1119 Appendix G Power-On and Power-Off Procedures Figure G.1 Method for Temporarily Selecting Clock Operation Mode 6 ............................... 1123 Figure G.2 Power-On Procedure 1 .......................................................................................... 1124 Figure G.3 Power-On Procedure 2 .......................................................................................... 1124 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xlv of liv Page xlvi of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Tables Section 1 Overview Table 1.1 SH7751/SH7751R Group Features ............................................................................. 2 Table 1.2 Pin Functions............................................................................................................. 13 Table 1.3 Pin Functions............................................................................................................. 24 Table 1.4 Pin Functions............................................................................................................. 35 Section 2 Programming Model Table 2.1 Initial Register Values............................................................................................... 49 Section 3 Memory Management Unit (MMU) Table 3.1 MMU Registers......................................................................................................... 66 Section 4 Caches Table 4.1 Cache Features (SH7751)........................................................................................ 101 Table 4.2 Cache Features (SH7751R) ..................................................................................... 102 Table 4.3 Store Queue Features .............................................................................................. 102 Table 4.4 Cache Control Registers.......................................................................................... 102 Section 5 Exceptions Table 5.1 Exception-Related Registers ................................................................................... 137 Table 5.2 Exceptions ............................................................................................................... 140 Table 5.3 Types of Reset......................................................................................................... 148 Section 6 Floating-Point Unit Table 6.1 Floating-Point Number Formats and Parameters .................................................... 174 Table 6.2 Floating-Point Ranges ............................................................................................. 175 Section 7 Instruction Set Table 7.1 Addressing Modes and Effective Addresses ........................................................... 191 Table 7.2 Notation Used in Instruction List ............................................................................ 195 Table 7.3 Fixed-Point Transfer Instructions............................................................................ 196 Table 7.4 Arithmetic Operation Instructions........................................................................... 198 Table 7.5 Logic Operation Instructions................................................................................... 200 Table 7.6 Shift Instructions ..................................................................................................... 201 Table 7.7 Branch Instructions ................................................................................................. 202 Table 7.8 System Control Instructions .................................................................................... 203 Table 7.9 Floating-Point Single-Precision Instructions........................................................... 205 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xlvii of liv Table 7.10 Table 7.11 Table 7.12 Floating-Point Double-Precision Instructions ......................................................... 206 Floating-Point Control Instructions......................................................................... 206 Floating-Point Graphics Acceleration Instructions ................................................. 207 Section 8 Pipelining Table 8.1 Instruction Groups................................................................................................... 218 Table 8.2 Parallel-Executability.............................................................................................. 222 Table 8.3 Execution Cycles..................................................................................................... 229 Section 9 Power-Down Modes Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes............................. 240 Table 9.2 Power-Down Mode Registers ................................................................................. 241 Table 9.3 Power-Down Mode Pins ......................................................................................... 241 Table 9.4 State of Registers in Standby Mode ........................................................................ 250 Section 10 Clock Oscillation Circuits Table 10.1 CPG Pins ................................................................................................................. 272 Table 10.2 CPG Register........................................................................................................... 272 Table 10.3 (1) Clock Operating Modes (SH7751) ................................................................... 273 Table 10.3 (2) Clock Operating Modes (SH7751R)................................................................. 273 Table 10.4 FRQCR Settings and Internal Clock Frequencies ................................................... 274 Table 10.5 WDT Registers........................................................................................................ 281 Section 11 Realtime Clock (RTC) Table 11.1 RTC Pins ................................................................................................................. 293 Table 11.2 RTC Registers ......................................................................................................... 293 Table 11.3 Crystal Oscillation Circuit Constants (Recommended Values)............................... 313 Section 12 Timer Unit (TMU) Table 12.1 TMU Pins................................................................................................................ 316 Table 12.2 TMU Registers ........................................................................................................ 317 Table 12.3 TMU Interrupt Sources ........................................................................................... 332 Section 13 Bus State Controller (BSC) Table 13.1 BSC Pins ................................................................................................................. 338 Table 13.2 BSC Registers ......................................................................................................... 340 Table 13.3 External Memory Space Map.................................................................................. 342 Table 13.4 PCMCIA Interface Features.................................................................................... 344 Table 13.5 PCMCIA Support Interfaces ................................................................................... 345 Table 13.6 Idle Insertion between Accesses ............................................................................. 365 Page xlviii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Table 13.7 Table 13.8 Table 13.9 Table 13.10 Table 13.11 Table 13.12 Table 13.13 Table 13.14 Table 13.15 When MPX Interface Is Set (Areas 0 to 6).............................................................. 373 32-Bit External Device/Big-Endian Access and Data Alignment ........................... 394 16-Bit External Device/Big-Endian Access and Data Alignment ........................... 395 8-Bit External Device/Big-Endian Access and Data Alignment............................. 396 32-Bit External Device/Little-Endian Access and Data Alignment ........................ 397 16-Bit External Device/Little-Endian Access and Data Alignment ........................ 398 8-Bit External Device/Little-Endian Access and Data Alignment .......................... 399 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing.... 414 Example of Correspondence between LSI and Synchronous DRAM Address Pins (32-Bit Bus Width, AMX2–AMX0 = 000, AMXEXT = 0) ............................ 429 Table 13.16 Cycles in Which Pipelined Access Can Be Used .................................................... 445 Table 13.17 Relationship between Address and CE When Using PCMCIA Interface ............... 462 Section 14 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Table 14.14 Table 14.15 Table 14.16 Table 14.17 Table 14.18 Table 14.19 Direct Memory Access Controller (DMAC) DMAC Pins............................................................................................................. 501 DMAC Pins in DDT Mode ..................................................................................... 502 DMAC Registers..................................................................................................... 503 Selecting External Request Mode with RS Bits ...................................................... 521 Selecting On-Chip Peripheral Module Request Mode with RS Bits ....................... 522 Supported DMA Transfers ...................................................................................... 526 Relationship between DMA Transfer Type, Request Mode, and Bus Mode .......... 532 External Request Transfer Sources and Destinations in Normal DMA Mode ........ 533 External Request Transfer Sources and Destinations in DDT Mode ...................... 534 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings ................................................. 552 Usable SZ, ID, and MD Combination in DDT Mode ............................................. 557 DMAC Pins............................................................................................................. 584 DMAC Pins in DDT Mode ..................................................................................... 585 Register Configuration ............................................................................................ 586 Channel Selection by DTR Format (DMAOR.DBL = 1)........................................ 594 Notification of Transfer Channel in Eight-Channel DDT Mode............................. 596 Function of BAVL .................................................................................................. 596 DTR Format for Clearing Request Queues ............................................................. 597 DMAC Interrupt-Request Codes............................................................................. 598 Section 15 Serial Communication Interface (SCI) Table 15.1 SCI Pins................................................................................................................... 606 Table 15.2 SCI Registers........................................................................................................... 606 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode .................. 625 Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode..................... 628 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page xlix of liv Table 15.5 Table 15.6 Table 15.7 Table 15.8 Table 15.9 Table 15.10 Table 15.11 Table 15.12 Table 15.13 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)............................................................................................. 629 Maximum Bit Rate with External Clock Input (Asynchronous Mode)................... 630 Maximum Bit Rate with External Clock Input (Synchronous Mode)..................... 630 SCSMR1 Settings for Serial Transfer Format Selection ......................................... 632 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection .......................... 633 Serial Transfer Formats (Asynchronous Mode) ...................................................... 635 Receive Error Conditions........................................................................................ 643 SCI Interrupt Sources.............................................................................................. 666 SCSSR1 Status Flags and Transfer of Receive Data............................................... 667 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.1 SCIF Pins ................................................................................................................ 674 Table 16.2 SCIF Registers ........................................................................................................ 674 Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection ......................................... 702 Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection ............................................... 702 Table 16.5 Serial Transfer Formats........................................................................................... 703 Table 16.6 SCIF Interrupt Sources............................................................................................ 714 Section 17 Smart Card Interface Table 17.1 Smart Card Interface Pins ....................................................................................... 721 Table 17.2 Smart Card Interface Registers ............................................................................... 721 Table 17.3 Smart Card Interface Register Settings ................................................................... 729 Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings ..................................... 732 Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0)........ 732 Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) ..................... 732 Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ............. 733 Table 17.8 Register Settings and SCK Pin State....................................................................... 733 Table 17.9 Smart Card Mode Operating States and Interrupt Sources...................................... 740 Section 18 I/O Ports Table 18.1 32-Bit General-Purpose I/O Port Pins ..................................................................... 755 Table 18.2 SCI I/O Port Pins..................................................................................................... 757 Table 18.3 SCIF I/O Port Pins .................................................................................................. 757 Table 18.4 I/O Port Registers.................................................................................................... 758 Section 19 Interrupt Controller (INTC) Table 19.1 INTC Pins ............................................................................................................... 771 Table 19.2 INTC Registers ....................................................................................................... 771 Table 19.3 IRL3–IRL0 Pins and Interrupt Levels..................................................................... 774 Page l of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Table 19.4 Table 19.5 Table 19.6 Table 19.7 Table 19.8 Interrupt Exception Handling Sources and Priority Order ...................................... 777 Interrupt Request Sources and IPRA–IPRD Registers............................................ 781 Interrupt Request Sources and INTPRI00 Register................................................. 783 Bit Allocation .......................................................................................................... 786 Interrupt Response Time ......................................................................................... 790 Section 20 User Break Controller (UBC) Table 20.1 UBC Registers......................................................................................................... 797 Section 21 High-performance User Debug Interface (H-UDI) Table 21.1 H-UDI Pins.............................................................................................................. 825 Table 21.2 H-UDI Registers...................................................................................................... 826 Table 21.3 Structure of Boundary Scan Register ...................................................................... 830 Section 22 Table 22.1 Table 22.2 Table 22.3 Table 22.4 Table 22.5 Table 22.6 Table 22.7 Table 22.8 Table 22.9 Table 22.10 Table 22.11 Table 22.12 Table 22.13 Table 22.14 PCI Controller (PCIC) Pin Configuration .................................................................................................... 849 List of PCI Configuration Registers ........................................................................ 851 PCI Configuration Register Configuration............................................................. 852 List of PCIC Local Registers................................................................................... 853 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16).................................. 864 Memory Space Base Address Register (BASE0).................................................... 870 Memory Space Base Address Register (BASE1).................................................... 872 Operating Modes ..................................................................................................... 928 PCI Command Support ........................................................................................... 929 Access Size.............................................................................................................. 960 DMA Transfer Access Size and Endian Conversion Mode .................................... 962 Target Transfer Access Size and Endian Conversion Mode ................................... 963 Interrupts ................................................................................................................. 969 Method of Stopping Clock per Operating Mode ..................................................... 974 Section 23 Electrical Characteristics Table 23.1 Absolute Maximum Ratings.................................................................................... 983 Table 23.2 DC Characteristics (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV)........................................................................................ 984 Table 23.3 DC Characteristics (HD6417751RF240 (V)) .......................................................... 986 Table 23.4 DC Characteristics (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*3)..................................................................................... 988 Table 23.5 DC Characteristics (HD6417751RF200 (V)) .......................................................... 990 Table 23.6 DC Characteristics (HD6417751BP167 (V)) .......................................................... 992 Table 23.7 DC Characteristics (HD6417751F167 (V))............................................................. 994 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page li of liv Table 23.8 Table 23.9 Table 23.10 Table 23.11 Table 23.12 Table 23.13 Table 23.14 Table 23.15 Table 23.16 Table 23.17 Table 23.18 Table 23.19 Table 23.20 Table 23.21 Table 23.22 Table 23.23 Table 23.24 Table 23.25 Table 23.26 Table 23.27 Table 23.28 Permissible Output Currents ................................................................................... 996 Clock Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV)........................................................................................ 996 Clock Timing (HD6417751RF240 (V)).................................................................. 996 Clock Timing (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*)...................................................................................... 997 Clock Timing (HD6417751RF200 (V)).................................................................. 997 Clock Timing (HD6417751BP167 (V), HD6417751F167 (V)).............................. 997 Clock and Control Signal Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV).............................................. 998 Clock and Control Signal Timing (HD6417751RF240 (V))................................. 1000 Clock and Control Signal Timing (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*2)......................................... 1002 Clock and Control Signal Timing (HD6417751RF200 (V))................................. 1004 Clock and Control Signal Timing (HD6417751BP167 (V), HD6417751F167 (V))........................................................................................... 1006 Control Signal Timing........................................................................................... 1012 Control Signal Timing........................................................................................... 1013 Bus Timing (1) ...................................................................................................... 1016 Bus Timing (2) ...................................................................................................... 1018 Peripheral Module Signal Timing (1) ................................................................... 1067 Peripheral Module Signal Timing (2) ................................................................... 1070 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1) ......................... 1076 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (2) ......................... 1077 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (1).......................................................................................... 1079 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (2).......................................................................................... 1079 Appendix A Address List Table A.1 Address List .......................................................................................................... 1083 Appendix C Mode Pin Settings Table C.1 Clock Operating Modes (SH7751)........................................................................ 1095 Table C.2 Clock Operating Modes (SH7751R) ..................................................................... 1096 Table C.3 Area 0 Memory Map and Bus Width .................................................................... 1096 Table C.4 Endian ................................................................................................................... 1096 Table C.5 Master/Slave.......................................................................................................... 1097 Table C.6 Clock Input............................................................................................................ 1097 Table C.7 PCI Mode .............................................................................................................. 1097 Page lii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Appendix D Pin Functions Table D.1 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable, Disable Common)............................................................................ 1099 Table D.2 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable).... 1101 Table D.3 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Disable) .. 1103 Table D.4 Handling of Pins When PCI Is Not Used .............................................................. 1105 Appendix H Product Lineup Table H.1 SH7751/SH7751R Product Lineup ....................................................................... 1125 Appendix I Version Registers Table I.1 Register Configuration .......................................................................................... 1127 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page liii of liv Page liv of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Section 1 Overview 1.1 SH7751/SH7751R Group Features The SH7751/SH7751R Group microprocessor, featuring a built-in PCI bus controller compatible with PCs and multimedia devices. The SuperH™* RISC engine is a Renesas original 32-bit RISC (Reduced Instruction Set Computer) microcomputer. The SuperH™ RISC engine employs a fixedlength 16-bit instruction set, allowing an approximately 50% reduction in program size over a 32bit instruction set. The SH7751/SH7751R Group feature the SH-4 Core, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. The SH7751/SH7751R Group have an instruction cache, an operand cache that can be switched between copy-back and write-through modes, a 4-entry full-associative instruction TLB (table look aside buffer), and MMU (memory management unit) with 64-entry full-associative shared TLB. The SH7751/SH7751R Group also feature a bus state controller (BSC) that can be coupled to DRAM (page/EDO) and synchronous DRAM. Also, because of its built-in functions, such as PCI bus controller, timers, and serial communications functions, required for multimedia and OA equipment, use of the SH7751/SH7751R Group enable a dramatic reduction in system costs. The features of the SH7751/SH7751R Group are summarized in table 1.1. Note: * SuperH is a trademark of Renesas Electronics Corp. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1 of 1128 Section 1 Overview Table 1.1 SH7751 Group, SH7751R Group SH7751/SH7751R Group Features Item Features LSI • Superscalar architecture: Parallel execution of two instructions • External buses (SH buses) ⎯ Separate 26-bit address and 32-bit data buses ⎯ External bus frequency of 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency • External bus (PCI bus): ⎯ 32-bit address/data multiplexing ⎯ Selection of internal clock or external PCI-dedicated clock CPU • Renesas Electronics original SuperH architecture • 32-bit internal data bus • General register file: ⎯ Sixteen 32-bit general registers (and eight 32-bit shadow registers) ⎯ Seven 32-bit control registers ⎯ Four 32-bit system registers • RISC-type instruction set (upward-compatible with SuperH Series) ⎯ Fixed 16-bit instruction length for improved code efficiency ⎯ Load-store architecture ⎯ Delayed branch instructions ⎯ Conditional execution ⎯ C-based instruction set Page 2 of 1128 • Superscalar architecture (providing simultaneous execution of two instructions) including FPU • Instruction execution time: Maximum 2 instructions/cycle • Virtual address space: 4 Gbytes (448-Mbyte external memory space) • Space identifier ASIDs: 8 bits, 256 virtual address spaces • On-chip multiplier • Five-stage pipeline R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Item Features FPU • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754 • Floating-point registers: 32 bits × 16 × 2 banks (single-precision 32 bits × 16 or double-precision 64 bits × 8) × 2 banks • 32-bit CPU-FPU floating-point communication register (FPUL) • Supports FMAC (multiply-and-accumulate) instruction • Supports FDIV (divide) and FSQRT (square root) instructions • Supports FLDI0/FLDI1 (load constant 0/1) instructions • Instruction execution times ⎯ Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles (double-precision) ⎯ Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles (double-precision) Note: FMAC is supported for single-precision only. • 3-D graphics instructions (single-precision only): ⎯ 4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 7 cycles (latency) ⎯ 4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles (latency) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 3 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Item Features Clock pulse generator (CPG) • Choice of main clock ⎯ SH7751: 1/2, 1, 3, or 6 times EXTAL ⎯ SH7751R: 1, 6, or 12 times EXTAL • Clock modes: (Maximum frequency: Varies with models) ⎯ CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ⎯ Bus frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ⎯ Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock • Power-down modes ⎯ Sleep mode ⎯ Deep sleep mode ⎯ Pin sleep mode ⎯ Standby mode ⎯ Hardware standby mode ⎯ Module standby function Memory management unit (MMU) Page 4 of 1128 • Single-channel watchdog timer • 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs) • Single virtual mode and multiple virtual memory mode • Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 64 Kbytes, 1 Mbyte • 4-entry fully-associative TLB for instructions • 64-entry fully-associative TLB for instructions and operands • Supports software-controlled replacement and random-counter replacement algorithm • TLB contents can be accessed directly by address mapping R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Item Features Cache memory [SH7751] • Section 1 Overview Instruction cache (IC) ⎯ 8 Kbytes, direct mapping ⎯ 256 entries, 32-byte block length ⎯ Normal mode (8-Kbyte cache) ⎯ Index mode • Operand cache (OC) ⎯ 16 Kbytes, direct mapping ⎯ 512 entries, 32-byte block length ⎯ Normal mode (16-Kbyte cache) ⎯ Index mode ⎯ RAM mode (8-Kbyte cache + 8-Kbyte RAM) ⎯ Choice of write method (copy-back or write-through) Cache memory [SH7751R] • Single-stage copy-back buffer, single-stage write-through buffer • Cache memory contents can be accessed directly by address mapping (usable as on-chip memory) • Store queue (32 bytes × 2 entries) • Instruction cache (IC) ⎯ 16 Kbytes, 2-way set associative ⎯ 256 entries/way, 32-byte block length ⎯ Cache-double-mode (16-Kbyte cache) ⎯ Index mode ⎯ SH7751-compatible mode (8 Kbytes, direct mapping) • Operand cache (OC) ⎯ 32 Kbytes, 2-way set associative ⎯ 512 entries/way, 32-byte block length ⎯ Cache-double-mode (32-Kbyte cache) ⎯ Index mode ⎯ RAM mode (16-Kbyte cache + 16-Kbyte RAM) ⎯ Choice of write method (copy-back or write-through) ⎯ SH7751-compatible mode (16 Kbytes, direct mapping) • Single-stage copy-back buffer, single-stage write-through buffer • Cache memory contents can be accessed directly by address mapping (usable as on-chip memory) • Store queue (32 bytes × 2 entries) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 5 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Item Features Interrupt controller (INTC) • Five independent external interrupts (NMI, IRL3 to IRL0) • 15-level signed external interrupts: IRL3 to IRL0 • On-chip peripheral module interrupts: Priority level can be set for each module • Supports debugging by means of user break interrupts • Two break channels • Address, data value, access type, and data size can all be set as break conditions • Supports sequential break function • Supports external memory access User break controller (UBC) Bus state controller (BSC) ⎯ 32/16/8-bit external data bus • External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area: ⎯ Bus size (8, 16, or 32 bits) ⎯ Number of wait cycles (hardware wait function also supported) ⎯ Direct connection of DRAM, synchronous DRAM, and burst ROM possible by setting space type ⎯ Supports fast page mode and DRAM EDO ⎯ Supports PCMCIA interface ⎯ Chip select signals (CS0 to CS6) output for relevant areas • DRAM/synchronous DRAM refresh functions ⎯ Programmable refresh interval ⎯ Supports CAS-before-RAS refresh mode and self-refresh mode Page 6 of 1128 • DRAM/synchronous DRAM burst access function • Big endian or little endian mode can be set R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Item Features Direct memory access controller (DMAC) • Section 1 Overview Physical address DMA controller ⎯ SH7751: 4-channel ⎯ SH7751R: 8-channel • Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes • Address modes: ⎯ Single address mode ⎯ Dual address mode • Transfer requests: External, on-chip peripheral module, or auto-requests • Bus modes: Cycle-steal or burst mode • Supports on-demand data transfer mode (external bus 32 bit) • 5-channel auto-reload 32-bit timer Input-capture function on one channel • Selection from 7 counter input clocks in 3 of 5 channels and from 5 counter input clocks on remaining 2 of 5 channels Realtime clock (RTC) • On-chip clock and calendar functions • Built-in 32 kHz crystal oscillation circuit with maximum 1/256 second resolution (cycle interrupts) Serial communication interface (SCI, SCIF) • Two full-duplex communication channels (SCI, SCIF) • Channel 1 (SCI): Timer unit (TMU) ⎯ Choice of asynchronous mode or synchronous mode ⎯ Supports smart card interface • Channel 2 (SCIF): ⎯ Supports asynchronous mode ⎯ Separate 16-byte FIFOs provided for transmitter and receiver R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 7 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Item Features PCI bus controller (PCIC) • PCI bus controller (supports a subset of PCI revision 2.1)* ⎯ 32-bit bus ⎯ 33 MHz/66 MHz support • PCI master/slave support • PCI host function support ⎯ Built-in bus arbiter • 4 built-in PCI-dedicated DMAC (direct memory access controller) channels ⎯ Each channel equipped with 64-byte FIFO • Selection of built-in clock or external PCI-dedicated clock • Interrupt requests can be sent to CPU Product lineup Abbreviation Voltage Operating Frequency Model No. Package SH7751 1.8 V 167 MHz HD6417751BP167 256-pin BGA HD6417751F167 256-pin QFP HD6417751RBP240 256-pin BGA SH7751R 1.5 V 240 MHz HD6417751RBA240H 200 MHz Note: * HD6417751RF240 256-pin QFP HD6417751RBG240 292-pin BGA HD6417751RBP200 256-pin BGA HD6417751RF200 256-pin QFP HD6417751RBG200 292-pin BGA Some items are not compatible with PCI 2.1. For more information, see section 22.1.1, Features. Page 8 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 1.2 Section 1 Overview Block Diagram Figure 1.1 shows an internal block diagram of the SH7751/SH7751R Group. Cache and TLB controller 64-bit data (store) SH-4 Core O cache 32-bit data CPG UTLB 32-bit data ITLB Upper 32-bit data FPU Lower 32-bit data 29-bit address I cache 32-bit data (store) UBC 32-bit data (load) 32-bit address (data) 32-bit data (instructions) 32-bit address (instructions) CPU RTC Peripheral address bus SCI (SCIF) Peripheral data bus INTC BSC DMAC TMU PCIC 32-bit data 32-bit data Address 32-bit data Address (PCI)DMAC External (SH) bus interface 32-bit PCI address/ data 26-bit SH bus address 32-bit SH bus data Legend: BSC: Bus state controller CPG: Clock pulse generator DMAC: Direct memory access controller FPU: Floating-point unit INTC: Interrupt controller ITLB: Instruction TLB (translation lookaside buffer) UTLB: Unified TLB (translation lookaside buffer) RTC: Realtime clock SCI: Serial communication interface SCIF: Serial communication interface with FIFO TMU: Timer unit UBC: User break controller PCIC: PCI bus controller Figure 1.1 Block Diagram of SH7751/SH7751R Group Functions R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 9 of 1128 Section 1 Overview AD30 AD31 AD21 AD22 AD23 C/BE3 AD24 AD25 AD26 AD27 AD28 AD29 DEVSEL TRDY IRDY PCIFRAME C/BE2 AD16 AD17 AD18 AD19 AD20 AD11 AD12 AD13 AD14 AD15 C/BE1 PAR PERR PCILOCK PCISTOP C/BE0 AD8 AD9 AD10 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 AD2 AD3 AD4 AD5 AD6 AD7 Pin Arrangement IRL3 IRL2 IRL1 IRL0 AD0 AD1 1.3 SH7751 Group, SH7751R Group XTAL2 EXTAL2 VDD-RTC VSS-RTC CA RESET TRST MRESET NMI BACK/BSREQ BREQ/BSACK MD6/IOIS16 RDY TXD MD2/RXD2 RXD TCLK MD8/RTS2 SCK MD1/TXD2 MD0/SCK2 MD7/CTS2 AUDSYNC AUDCK AUDATA0 AUDATA1 AUDATA2 AUDATA3 Reserved MD3/CE2A MD4/CE2B MD5 DACK0 DACK1 DRAK0 DRAK1 STATUS0 STATUS1 DREQ0 DREQ1 ASEBRK/BRKACK TDO 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 QFP256 (Top view) VDD (internal) VSS (internal) VDDQ (IO) VSSQ (IO) SERR PCIREQ1/GNTIN PCIGNT1/REQOUT PCICLK PCIRST INTA IDSEL PCIREQ2/MD9 PCIREQ3/MD10 PCIREQ4 PCIGNT2 PCIGNT3 PCIGNT4 SLEEP WE3/ICIOWR WE2/ICIORD A25 A24 A23 A22 A21 A20 A19 A18 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 CAS3/DQM3 CAS2/DQM2 A17 A16 A15 A14 A13 A12 A4 A5 A6 A7 A8 A9 A10 A11 CS2 CS3 A0 A1 A2 A3 Reserved RD/CASS/FRAME CKE RAS D11 D12 D13 D14 D15 CAS0/DQM0 CAS1/DQM1 RD/WR CKIO Reserved D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 TDI CS0 CS1 CS4 CS5 CS6 BS WE0/REG WE1 D0 TMS TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VDD-PLL2 VSS-PLL2 VDD-PLL1 VSS-PLL1 VDD-CPG VSS-CPG XTAL EXTAL 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. Figure 1.2 Pin Arrangement (256-Pin QFP) Page 10 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 1 2 3 4 XTAL Section 1 Overview 5 6 7 8 DREQ0 VDD-PLL1 9 10 DACK1 11 AUDATA1 12 13 14 15 EXTAL TDO RDY AUDCK MD8/RTS2 AUDSYNC VDD-PLL2 DRAK1 MD3/CE2A DACK0 STATUS1 16 17 18 19 20 BACK/BSREQ TXD MD7/CTS2 A RESET MRESET XTAL2 EXTAL2 IRL3 * B CS0 CS1 DRAK0 STATUS0 TMS TCK MD5 MD1/TXD2 TCLK AUDATA2 AUDATA0 MD0/SCK2 BREQ/BSACK TRST CA IRL1 C CS4 DREQ1 CS6 RXD NC TDI MD4/CE2B IRL2 MD6/IOIS16 NMI SCK AD0 AD2 D CS5 BS D0 ASEBRK/ WE0/REG BRKACK MD2/RXD2 AUDATA3 AD1 AD3 AD5 E D1 WE1 D3 D2 IRL0 AD4 AD7 AD6 F AD9 G D4 D7 AD8 D5 AD11 H D8 C/BE0 D6 D11 AD10 AD15 AD13 D9 J D12 AD12 D10 D14 D13 BGA256 K D15 CAS0/DQM0 PERR CAS1/DQM1 NC PAR PCISTOP (Top view) L AD14 C/BE1 PCILOCK TRDY PCIFRAME M CKIO RD/WR CKE IRDY DEVSEL CS2 C/BE2 AD17 N RAS NC AD16 AD19 P RD/CASS/ FRAME AD18 AD22 AD20 R CS3 A0 A3 A1 AD24 AD23 T A4 A2 A7 D22 A5 PCIGNT2 A20 AD25 AD21 AD27 AD26 U A8 CAS3/DQM3 A6 A9 A16 D26 A24 D23 D19 A21 PCIREQ4 IDSEL C/BE3 AD28 V A10 D27 D16 D24 A17 A25 A18 D30 A22 D31 WE2/ICIORD A23 SLEEP W A14 A11 A13 CAS2/DQM2 D28 D17 D25 D20 Y A12 Notes: A15 D18 D21 D29 A19 WE3/ICIOWR INTA PCIGNT1/ AD29 PCIGNT4 PCIREQ3/MD10 REQOUT AD30 PCIRST PCIREQ1/ PCIREQ2/MD9 GNTIN AD31 PCIGNT3 SERR PCICLK VDDQ(IO) VSS (internal) VDD-CPG/RTC VSSQ(IO) VDD-PLL1/2 VSS-CPG/RTC VDD (internal) VSS-PLL1/2 NC Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDDPLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. * May be connected to VSSQ. Figure 1.3 Pin Arrangement (256-Pin BGA) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 11 of 1128 Section 1 Overview 1 SH7751 Group, SH7751R Group 2 3 4 5 6 7 STATUS0 VDD-PLL1 XTAL 8 9 10 MD5 11 12 13 MD1/TXD2 AUDATA0 14 15 16 17 NMI MD2/RXD2 18 19 20 XTAL2 VDD-RTC A EXTAL TCK AUDSYNC AUDATA3 TCLK VDD-PLL2 DRAK0 VSS-CPG MD0/SCK2 DACK0 AUDATA1 STATUS1 VSS-PLL2 EXTAL2 RESET MD6/IOIS16 IRL3 RXD BACK/BSREQ VSS-RTC B TMS CS0 VDD-CPG AUDCK MD8/RTS2 ASEBRK/ DRAK1 MD3/CE2A DACK1 AUDATA2 MD7/CTS2 TDO BRKACK DREQ0 TRST RDY BREQ/BSACK IRL1 CA C TDI CS4 DREQ1 VSS-PLL1 MD4/CE2B SCK TXD MRESET IRL2 IRL0 AD1 D CS1 BS CS5 AD0 AD2 AD4 E CS6 WE0/REG AD3 D0 AD5 BGA292 F WE1 AD7 D1 AD6 D3 AD8 (Top view) G D2 C/BE0 AD9 D5 AD11 H D4 D6 AD10 AD14 AD12 D8 J D7 D9 AD13 D11 PAR AD15 K D10 D12 PERR D14 C/BE1 PCISTOP L D13 CAS1/DQM1 PCILOCK DEVSEL IRDY D15 M CAS0/ RD/CASS/ RD/WR DQM0 FRAME TRDY C/BE2 AD16 N CKIO CS2 PCIFRAME CKE AD18 P RAS AD17 A0 AD19 AD21 R CS3 A1 AD20 AD23 A3 C/BE3 T A2 AD22 A4 AD24 A6 AD26 U A5 A7 A9 CAS3/DQM3 D26 D21 PCIREQ1/ AD25 GNTIN AD28 PCIRST PCIGNT1/ AD27 PCIGNT2 WE2/ICIORD A22 REQOUT SLEEP PCIREQ3/MD10 AD30 PCIREQ2/MD9 A23 V A8 A10 A12 CAS2/DQM2 D29 D18 D20 D25 A20 D31 W D17 A16 A11 A17 A14 D23 D28 D24 D19 A19 D30 A21 INTA A25 PCIGNT3 WE3/ICIOWR PCIREQ4 AD29 PCICLK AD31 Y A13 A15 D16 D22 D27 A18 A24 PCIGNT4 IDSEL SERR VDDQ(IO) VSS VDD-CPG/RTC VDD-PLL1/2 VSS-CPG/RTC VDD (internal) VSS-PLL1/2 Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. Figure 1.4 Pin Arrangement (292-Pin BGA) Page 12 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview 1.4 Pin Functions 1.4.1 Pin Functions (256-Pin QFP) Table 1.2 Pin Functions Memory Interface No. Pin Name I/O Function 1 TMS I Mode (H-UDI) 2 TCK I Clock (H-UDI) 3 VDDQ Power IO VDD 4 VSSQ Power IO GND 5 TDI I Data in (H-UDI) 6 CS0 O Chip select 0 CS0 CS0 7 CS1 O Chip select 1 CS1 CS1 8 CS4 O Chip select 4 CS4 CS4 9 CS5 O Chip select 5 CS5 CE1A CS5 10 CS6 O Chip select 6 CS6 CE1B CS6 11 BS O Bus start (BS) (BS) (BS) 12 WE0/REG O D7–D0 select signal WE0 REG 13 WE1 O D15-D8 select signal WE1 WE1 14 D0 I/O Data 15 VDDQ Power IO VDD 16 VSSQ Power IO GND 17 VDD Power Internal VDD 18 VSS Power Internal GND 19 D1 I/O Data A1 20 D2 I/O Data A2 21 D3 I/O Data A3 22 D4 I/O Data A4 23 D5 I/O Data A5 24 D6 I/O Data A6 25 D7 I/O Data A7 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Reset SRAM DRAM (BS) SDRAM (BS) PCMCIA MPX A0 Page 13 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Name I/O Function 26 D8 I/O Data A8 27 D9 I/O Data A9 28 D10 I/O Data A10 29 VDDQ Power IO VDD 30 VSSQ Power IO GND 31 D11 I/O Data A11 32 D12 I/O Data A12 33 D13 I/O Data A13 34 D14 I/O Data A14 35 D15 I/O Data A15 36 CAS0/ DQM0 O D7–D0 select signal CAS0 DQM0 37 CAS1/ DQM1 O D15–D8 select signal CAS1 DQM1 38 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR 39 CKIO O Clock output CKIO CKIO CKIO CKIO 40 Reserved 41 VDDQ Power IO VDD 42 VSSQ Power IO GND 43 Reserved 44 RD/CASS/ FRAME O Read/CAS/ FRAME CAS OE FRAME 45 CKE O Clock output enable 46 RAS O RAS 47 VDD Power Internal VDD 48 VSS Power Internal GND 49 CS2 O SRAM RD/WR DRAM SDRAM PCMCIA MPX Do not connect Do not connect OE CKE RAS RAS Chip select 2 CS2 (CS2) CS2 CS2 CS3 (CS3) CS3 CS3 50 CS3 O Chip select 3 51 A0 O Address 52 A1 O Address 53 A2 O Address 54 A3 O Address 55 VDDQ Power IO VDD Page 14 of 1128 Reset R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Name I/O Function 56 VSSQ Power IO GND 57 A4 O Address 58 A5 O Address 59 A6 O Address 60 A7 O Address 61 A8 O Address 62 A9 O Address 63 A10 O Address 64 A11 O Address 65 A12 O Address 66 A13 O Address 67 VDDQ Power IO VDD 68 VSSQ Power IO GND 69 A14 O Address 70 A15 O Address 71 A16 O Address 72 A17 O Address 73 CAS2/ DQM2 O 74 CAS3/ DQM3 75 DRAM SDRAM D23–D16 select signal CAS2 DQM2 O D31–D24 select signal CAS3 DQM3 D16 I/O Data A16 76 D17 I/O Data A17 77 D18 I/O Data A18 78 D19 I/O Data A19 79 VDDQ Power IO VDD 80 VSSQ Power IO GND 81 VDD Power Internal VDD 82 VSS Power Internal GND 83 D20 I/O Data A20 84 D21 I/O Data A21 85 D22 I/O Data A22 86 D23 I/O Data A23 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Reset SRAM PCMCIA MPX Page 15 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA 87 D24 I/O Data A24 88 D25 I/O Data A25 89 D26 I/O Data 90 D27 I/O Data 91 D28 I/O Data 92 D29 I/O Data 93 VDDQ Power IO VDD 94 VSSQ Power IO GND 95 D30 I/O Data ACCSIZE1 96 D31 I/O Data ACCSIZE2 97 VDD Power Internal VDD 98 VSS Power Internal GND 99 A18 O Address 100 A19 O Address 101 A20 O Address 102 A21 O Address 103 A22 O Address 104 A23 O Address ACCSIZE0 105 VDDQ Power IO VDD 106 VSSQ Power IO GND 107 A24 O Address 108 A25 O Address 109 WE2/ ICIORD O D23–D16 select signal WE2 ICIORD 110 WE3/ ICIOWR O D31–D24 select signal WE3 ICIOWR 111 VDD Power Internal VDD 112 VSS Power Internal GND 113 SLEEP I Sleep 114 PCIGNT4 O Bus grant (host function) 115 PCIGNT3 O Bus grant (host function) Page 16 of 1128 MPX R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Name I/O Function 116 PCIGNT2 O Bus grant (host function) 117 PCIREQ4 I* Bus request (host function) 118 PCIREQ3/ MD10 I* Bus request (host function)/ mode 119 VDDQ Power IO VDD 120 VSSQ Power IO GND 121 PCIREQ2/ MD9 I* Bus request (host function)/ mode 122 IDSEL I Configuration device select 123 INTA O Interrupt (async) Reset SRAM DRAM SDRAM PCMCIA MPX MD10 MD9 124 PCIRST O Reset output 125 PCICLK I PCI input clock 126 PCIGNT1/ REQOUT O Bus grant (host function)/ bus request 127 PCIREQ1/ GNTIN I Bus request (host function) /bus grant 128 SERR I/O System error 129 AD31 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 130 AD30 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 131 VDDQ Power IO VDD (Port) (Port) (Port) (Port) (Port) 132 VSSQ Power IO GND 133 AD29 I/O PCI address/ data/port R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 17 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Name I/O Function 134 AD28 I/O 135 AD27 SRAM DRAM SDRAM PCMCIA MPX PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 136 AD26 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 137 AD25 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 138 AD24 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 139 C/BE3 I/O Command/byt e enable 140 AD23 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 141 AD22 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 142 AD21 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 143 VDDQ Power IO VDD 144 VSSQ Power IO GND 145 VDD Power Internal VDD Reset 146 VSS Power Internal GND 147 AD20 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 148 AD19 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 149 AD18 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 150 AD17 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 151 AD16 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 152 C/BE2 I/O Command/ byte enable 153 PCIFRAME I/O Bus cycle 154 IRDY I/O Initiator ready 155 TRDY I/O Target ready Page 18 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Name I/O Function 156 DEVSEL I/O Device select 157 VDDQ Power IO VDD 158 VSSQ Power IO GND 159 PCISTOP I/O Transaction stop 160 PCILOCK I/O Exclusive access Reset SRAM DRAM SDRAM PCMCIA MPX 161 PERR I/O Parity error 162 PAR I/O Parity 163 C/BE1 I/O Command/ byte enable 164 AD15 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 165 AD14 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 166 AD13 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 167 AD12 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 168 AD11 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 169 VDDQ Power IO VDD 170 VSSQ Power IO GND 171 AD10 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 172 AD9 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 173 AD8 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 174 C/BE0 I/O Command/ byte enable 175 VDD Power Internal VDD 176 VSS Power Internal GND 177 AD7 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 178 AD6 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 19 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Name I/O Function 179 AD5 I/O 180 AD4 SRAM DRAM SDRAM PCMCIA MPX PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 181 AD3 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 182 AD2 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 183 VDDQ Power I/O VDD 184 VSSQ Power I/O GND 185 AD1 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 186 AD0 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 187 IRL0 I Interrupt 0 188 IRL1 I Interrupt 1 189 IRL2 I Interrupt 2 190 IRL3 I Interrupt 3 191 VSSQ Power I/O GND 192 VDDQ Power I/O VDD 193 XTAL2 O RTC crystal resonator pin 194 EXTAL2 I RTC crystal resonator pin 195 VDD-RTC Power RTC VDD 196 VSS-RTC Power RTC GND 2 197 CA* I Hardware standby 198 RESET I Reset 199 TRST I Reset (H-UDI) 200 MRESET I Manual reset 201 NMI I Nonmaskable interrupt Page 20 of 1128 Reset RESET R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Name I/O Function 202 BACK/ BSREQ O Bus acknowledge/ bus request 203 BREQ/ BSACK I Bus request/bus acknowledge 204 MD6/ IOIS16 I Mode/IOIS16 MD6 (PCMCIA) 205 RDY I Bus ready 206 TXD O SCI data output 207 VDDQ Power IO VDD 208 VSSQ Power IO GND 209 VDD Power Internal VDD 210 VSS Power Internal GND 211 MD2/RXD2 I Mode/SCIF data input 212 RXD I SCI data input 213 TCLK I/O RTC/TMU clock 214 MD8/RTS2 I/O Mode/SCIF data control (RTS) 215 SCK Reset SRAM DRAM SDRAM PCMCIA MPX IOIS16 RDY RDY RDY MD2 RXD2 RXD2 RXD2 RXD2 RXD2 MD8 RTS2 RTS2 RTS2 RTS2 RTS2 I/O SCIF clock 216 MD1/TXD2 I/O Mode/SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 217 MD0/SCK2 I/O Mode/SCIF clock MD0 SCK2 SCK2 SCK2 SCK2 SCK2 218 MD7/CTS2 I/O Mode/SCIF data control (CTS) MD7 CTS2 CTS2 CTS2 CTS2 CTS2 219 AUDSYNC AUD sync 220 AUDCK AUD clock 221 VDDQ Power IO VDD 222 VSSQ Power IO GND 223 AUDATA0 AUD data 224 AUDATA1 AUD data R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 21 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Name I/O Function 225 VDD Power Internal VDD 226 VSS Power Internal GND Reset SRAM DRAM SDRAM PCMCIA 227 AUDATA2 AUD data 228 AUDATA3 AUD data 229 Reserved Do not connect 230 MD3/CE2A I/O Mode/ PCMCIA-CE MD3 CE2A 231 MD4/CE2B I/O Mode/ PCMCIA-CE MD4 CE2B 232 MD5 I Mode MD5 233 VDDQ Power IO VDD 234 VSSQ Power IO GND 235 DACK0 O DMAC0 bus acknowledge 236 DACK1 O DMAC1 bus acknowledge 237 DRAK0 O DMAC0 request acknowledge 238 DRAK1 O DMAC1 request acknowledge 239 VDD Power Internal VDD 240 VSS Power Internal GND 241 STATUS0 O Status 242 STATUS1 O Status 243 DREQ0 I Request from DMAC0 244 DREQ1 I Request from DMAC1 245 ASEBRK/ BRKACK I/O Pin break/ acknowledge (H-UDI) 246 TDO O Data out (H-UDI) Page 22 of 1128 MPX R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Name I/O Function 247 VDDQ Power IO VDD 248 VSSQ Power IO GND 249 VDD-PLL2 Power PLL2 VDD 250 VSS-PLL2 Power PLL2 GND 251 VDD-PLL1 Power PLL1 VDD 252 VSS-PLL1 Power PLL1 GND 253 VDD-CPG Power CPG VDD 254 VSS-CPG Power CPG GND 255 XTAL O Crystal resonator 256 EXTAL I External input clock/crystal resonator Reset SRAM DRAM SDRAM PCMCIA MPX Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. However, on the SH7751 in hardware standby mode, supply power to RTC at the minimum. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D. * I/O attribute is I/O when used as a port. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 23 of 1128 Section 1 Overview 1.4.2 SH7751 Group, SH7751R Group Pin Functions (256-Pin BGA) Table 1.3 Pin Functions Memory Interface No. Pin Number Pin Name I/O Function 1 B3 TMS I Mode (H-UDI) 2 C4 TCK I Clock (H-UDI) 3 G3 VDDQ Power IO VDD 4 F2 VSSQ Power IO GND 5 D4 TDI I Data in (H-UDI) 6 B1 CS0 O Chip select 0 CS0 CS0 7 C2 CS1 O Chip select 1 CS1 CS1 8 C1 CS4 O Chip select 4 CS4 CS4 9 D3 CS5 O Chip select 5 CS5 10 D2 CS6 O Chip select 6 CS6 11 D1 BS O Bus start (BS) 12 E4 WE0/ REG O D7–D0 select signal WE0 REG 13 E3 WE1 O D15–D8 select signal WE1 WE1 14 E2 D0 I/O Data 15 G2 VDDQ Power IO VDD 16 L4 VSSQ Power IO GND 17 G4 VDD Power Internal VDD 18 F4 VSS Power Internal GND 19 E1 D1 I/O Data A1 20 F3 D2 I/O Data A2 21 F1 D3 I/O Data A3 22 G1 D4 I/O Data A4 23 H4 D5 I/O Data A5 24 H3 D6 I/O Data A6 25 H2 D7 I/O Data A7 26 H1 D8 I/O Data A8 Page 24 of 1128 Reset SRAM DRAM SDRAM PCMCIA CE1A (BS) (BS) MPX CS5 CE1B CS6 (BS) (BS) A0 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Number Pin Name I/O Function 27 J4 I/O Data A9 A10 D9 Reset SRAM DRAM SDRAM PCMCIA MPX 28 J3 D10 I/O Data 29 K3 VDDQ Power IO VDD 30 L3 VSSQ Power IO GND 31 J2 D11 I/O Data A11 32 J1 D12 I/O Data A12 33 K4 D13 I/O Data A13 34 K2 D14 I/O Data A14 35 K1 D15 I/O Data A15 36 L2 CAS0/ DQM0 O D7–D0 select signal CAS0 DQM0 37 M4 CAS1/ DQM1 O D15–D8 select signal CAS1 DQM1 38 M3 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR 39 M1 CKIO O Clock output CKIO CKIO CKIO CKIO 40 M2 NC 41 P3 VDDQ Power IO VDD 42 L1 VSSQ Power IO GND 43 N3 NC 44 P1 RD/ CASS/ FRAME O Read/CAS/ FRAME CAS OE FRAME 45 N2 CKE O Clock output enable 46 N1 RAS O RAS 47 P4 VDD Power Internal VDD RD/WR Do not connect Do not connect OE CKE RAS RAS 48 R4 VSS Power Internal GND 49 N4 CS2 O Chip select 2 CS2 (CS2) CS2 CS2 50 R3 CS3 O Chip select 3 CS3 (CS3) CS3 CS3 51 R1 A0 O Address 52 T4 A1 O Address 53 T3 A2 O Address 54 T2 A3 O Address 55 P2 VDDQ Power IO VDD R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 25 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Number Pin Name I/O Function 56 R2 VSSQ Power IO GND 57 T1 A4 O Address 58 U4 A5 O Address 59 U3 A6 O Address 60 U2 A7 O Address 61 U1 A8 O Address 62 V2 A9 O Address 63 V1 A10 O Address 64 W1 A11 O Address 65 Y1 A12 O Address 66 Y2 A13 O Address 67 V7 VDDQ Power IO VDD 68 V3 VSSQ Power IO GND 69 W3 A14 O Address 70 Y3 A15 O Address 71 V4 A16 O Address 72 W4 A17 O Address 73 Y4 CAS2/ DQM2 O 74 U5 CAS3/ DQM3 75 V5 D16 76 W5 D17 I/O Data A17 77 Y5 D18 I/O Data A18 A19 Reset SRAM DRAM SDRAM D23–D16 select signal CAS2 DQM2 O D31–D24 select signal CAS3 DQM3 I/O Data PCMCIA MPX A16 78 V6 D19 I/O Data 79 W7 VDDQ Power IO VDD 80 W2 VSSQ Power IO GND 81 U7 VDD Power Internal VDD 82 U6 VSS Power Internal GND 83 Y6 D20 I/O Data A20 84 Y7 D21 I/O Data A21 85 U8 D22 I/O Data A22 86 V8 D23 I/O Data A23 Page 26 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Number Pin Name I/O Function 87 W8 D24 I/O Data A24 88 Y8 D25 I/O Data A25 89 U9 D26 I/O Data 90 V9 D27 I/O Data Reset SRAM DRAM SDRAM PCMCIA MPX 91 W9 D28 I/O Data 92 Y9 D29 I/O Data 93 V10 VDDQ Power IO VDD 94 W6 VSSQ Power IO GND 95 W10 D30 I/O Data ACCSIZE1 96 Y10 D31 I/O Data ACCSIZE2 97 U10 VDD Power Internal VDD 98 U11 VSS Power Internal GND 99 V11 A18 O Address 100 Y11 A19 O Address 101 U12 A20 O Address 102 V12 A21 O Address 103 W12 A22 O Address ACCSIZE0 104 Y12 A23 O Address 105 V14 VDDQ Power IO VDD 106 W11 VSSQ Power IO GND 107 U13 A24 O Address 108 V13 A25 O Address 109 W13 WE2/ ICIORD O D23–D16 select signal WE2 ICIORD 110 Y13 WE3/ ICIOWR O D31–D24 select signal WE3 ICIOWR 111 U14 VDD Power Internal VDD 112 U15 VSS Power Internal GND 113 Y14 SLEEP I Sleep 114 V15 PCIGNT4 O Bus grant (host function) 115 Y15 PCIGNT3 O Bus grant (host function) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 27 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Number Pin Name 116 U16 117 I/O Function PCIGNT2 O Bus grant (host function) V16 PCIREQ4 I*1 Bus request (host function) 118 W16 PCIREQ3/ MD10 I*1 Bus request (host function)/ mode 119 W14 VDDQ Power IO VDD 120 W15 VSSQ Power IO GND 121 Y16 PCIREQ2/ MD9 I*1 Bus request (host function)/ mode 122 U17 IDSEL I Configuration device select 123 V17 INTA O Interrupt (async) 124 W17 PCIRST O Reset output 125 Y17 PCICLK I PCI input clock 126 W18 PCIGNT1/ REQOUT O Bus grant (host function)/ bus request 127 Y18 PCIREQ1/ GNTIN I Bus request (host function)/ bus grant 128 Y19 SERR I/O System error 129 Y20 AD31 I/O 130 W20 AD30 131 P18 132 133 SRAM DRAM SDRAM PCMCIA MPX PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) VDDQ Power IO VDD V18 VSSQ Power IO GND V19 AD29 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 134 V20 AD28 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 135 U18 AD27 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) Page 28 of 1128 Reset MD10 MD9 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Number Pin Name I/O Function 136 U20 AD26 I/O 137 T17 AD25 138 T18 139 SRAM DRAM SDRAM PCMCIA MPX PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) AD24 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) U19 C/BE3 I/O PCI address/ data/port 140 T20 AD23 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 141 R18 AD22 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 142 T19 AD21 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 143 N19 VDDQ Power IO VDD 144 W19 VSSQ Power IO GND 145 P17 VDD Power Internal VDD 146 R17 VSS Power Internal GND 147 R20 AD20 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 148 P20 AD19 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 149 P19 AD18 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 150 N20 AD17 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 151 N17 AD16 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 152 N18 C/BE2 I/O Command/ byte enable 153 M20 PCIFRAME I/O 154 M19 IRDY I/O Initiator ready 155 M18 TRDY I/O Target ready 156 M17 DEVSEL I/O Device select 157 L18 VDDQ Power IO VDD R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Reset Bus cycle Page 29 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Number Pin Name I/O Function 158 R19 VSSQ Power IO GND 159 L20 PCISTOP I/O Transaction stop 160 L19 PCILOCK I/O Exclusive access 161 L17 PERR I/O Parity error Reset SRAM DRAM SDRAM PCMCIA MPX 162 K20 PAR I/O Parity 163 K18 C/BE1 I/O Command/ byte enable 164 J20 AD15 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 165 J19 AD14 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 166 J18 AD13 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 167 J17 AD12 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 168 H20 AD11 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 169 G18 VDDQ Power IO VDD 170 K17 VSSQ Power IO GND 171 H19 AD10 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 172 G20 AD9 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 173 H18 AD8 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 174 H17 C/BE0 I/O Command/ byte enable 175 G17 VDD Power Internal VDD 176 F17 VSS Power Internal GND 177 F18 AD7 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 178 F20 AD6 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 179 E20 AD5 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) Page 30 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Number Pin Name I/O Function 180 E19 AD4 I/O 181 E18 AD3 182 D20 183 SRAM DRAM SDRAM PCMCIA MPX PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) AD2 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) G19 VDDQ Power I/O VDD 184 K19 VSSQ Power I/O GND 185 D19 AD1 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 186 D18 AD0 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 187 E17 IRL0 I Interrupt 0 188 C20 IRL1 I Interrupt 1 189 C19 IRL2 I Interrupt 2 I Interrupt 3 190 B20 IRL3 191 B18 NC Do not connect *2 192 D17 VDDQ Power I/O VDD 193 A20 XTAL2 O RTC crystal resonator pin 194 A19 EXTAL2 I RTC crystal resonator pin 195 A18 VDD-RTC Power RTC VDD 196 B19 VSS-RTC Power RTC GND 197 B17 CA I Hardware standby 198 A17 RESET I Reset 199 C16 TRST I Reset (H-UDI) 200 B16 MRESET I Manual reset 201 D16 NMI I Nonmaskable interrupt 202 A16 BACK/ BSREQ O Bus acknowledge/ bus request R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Reset RESET Page 31 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Number Pin Name 203 B15 204 I/O Function BREQ/ BSACK I Bus request/bus acknowledge C15 MD6/ IOIS16 I Mode/IOIS16 (PCMCIA) 205 A15 RDY I Bus ready 206 A14 TXD O SCI data output 207 B14 VDDQ Power IO VDD 208 F19 VSSQ Power IO GND 209 D14 VDD Power Internal VDD 210 D15 VSS Power Internal GND 211 D13 MD2/ RXD2 I Mode/SCIF data input Reset SRAM DRAM SDRAM PCMCIA MPX IOIS16 MD6 RDY RDY RDY MD2 RXD2 RXD2 RXD2 RXD2 RXD2 MD8 RTS2 RTS2 RTS2 RTS2 RTS2 212 C13 RXD I SCI data input 213 B13 TCLK I/O RTC/TMU clock 214 A13 MD8/ RTS2 I/O Mode/SCIF data control (RTS) 215 D12 SCK I/O SCIF clock 216 B11 MD1/ TXD2 I/O Mode/SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 217 C12 MD0/ SCK2 I/O Mode/SCIF clock MD0 SCK2 SCK2 SCK2 SCK2 SCK2 218 A12 MD7/ CTS2 I/O Mode/SCIF data control (CTS) MD7 CTS2 CTS2 CTS2 CTS2 CTS2 219 B12 AUDSYNC 220 A11 AUDCK 221 C14 VDDQ Power IO VDD 222 C18 VSSQ Power IO GND 223 C10 AUDATA0 AUD data 224 A10 AUDATA1 AUD data 225 D11 VDD Power Internal VDD 226 D10 VSS Power Internal GND Page 32 of 1128 AUD sync AUD clock R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Number Pin Name 227 B9 AUDATA2 AUD data 228 D9 AUDATA3 AUD data 229 C9 NC Do not connect 230 A9 MD3/CE2A I/O Mode/ PCMCIA-CE MD3 CE2A 231 D8 MD4/CE2B I/O Mode/ PCMCIA-CE MD4 CE2B 232 C8 MD5 Mode MD5 233 C11 VDDQ Power IO VDD 234 C17 VSSQ Power IO GND 235 B8 DACK0 O DMAC0 bus acknowledge 236 A8 DACK1 O DMAC1 bus acknowledge 237 B7 DRAK0 O DMAC0 request acknowledge 238 A7 DRAK1 O DMAC1 request acknowledge 239 D7 VDD Power Internal VDD 240 D6 VSS Power Internal GND 241 C6 STATUS0 O Status 242 B6 STATUS1 O Status 243 A6 DREQ0 I Request from DMAC0 244 C5 DREQ1 I Request from DMAC1 245 D5 ASEBRK/ BRKACK I/O Pin break/ acknowledge (H-UDI) 246 B4 TDO O Data out (H-UDI) 247 C7 VDDQ Power IO VDD I/O I Function 248 B10 VSSQ Power IO GND 249 A5 VDD-PLL2 Power PLL2 VDD R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Reset SRAM DRAM SDRAM PCMCIA MPX Page 33 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Number Pin Name I/O Function 250 B5 VSS-PLL2 Power PLL2 GND 251 A4 VDD-PLL1 Power PLL1 VDD 252 C3 VSS-PLL1 Power PLL1 GND 253 A3 VDD-CPG Power CPG VDD 254 B2 VSS-CPG Power CPG GND 255 A2 XTAL O Crystal resonator 256 A1 EXTAL I External input clock/crystal resonator Reset SRAM DRAM SDRAM PCMCIA MPX Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. However, on the SH7751 in hardware standby mode, supply power to RTC at the minimum. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D. 1. I/O attribute is I/O when used as a port. 2. May be connected to VSSQ. Page 34 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 1.4.3 Section 1 Overview Pin Functions (292-Pin BGA) Table 1.4 Pin Functions Memory Interface No. Pin Number Pin Name I/O Function 1 B1 TMS I Mode (H-UDI) 2 B2 TCK I Clock (H-UDI) 3 F4 VDDQ Power IO VDD 4 E4 VSS Power GND 5 C1 TDI I Data in (H-UDI) 6 C2 CS0 O Chip select 0 CS0 CS0 7 D1 CS1 O Chip select 1 CS1 CS1 8 D2 CS4 O Chip select 4 CS4 CS4 9 D3 CS5 O Chip select 5 CS5 10 E1 CS6 O Chip select 6 CS6 11 E2 BS O Bus start (BS) 12 E3 WE0/ REG O D7–D0 select signal WE0 REG 13 F1 WE1 O D15–D8 select signal WE1 WE1 14 F2 D0 I/O Data 15 G3 VDDQ Power IO VDD 16 D4 VSS Power GND 17 G4 VDD Power Internal VDD Reset SRAM DRAM SDRAM PCMCIA MPX CE1A (BS) (BS) CS5 CE1B CS6 (BS) (BS) A0 18 H4 VSS Power GND 19 F3 D1 I/O Data A1 20 G1 D2 I/O Data A2 21 G2 D3 I/O Data A3 22 H1 D4 I/O Data A4 23 H2 D5 I/O Data A5 24 H3 D6 I/O Data A6 25 J1 D7 I/O Data A7 26 J2 D8 I/O Data A8 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 35 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Number Pin Name I/O Function 27 J3 I/O Data A9 A10 D9 Reset SRAM DRAM SDRAM PCMCIA MPX 28 K1 D10 I/O Data 29 J4 VDDQ Power IO VDD 30 D5 VSS Power GND 31 K2 D11 I/O Data A11 32 K3 D12 I/O Data A12 33 L1 D13 I/O Data A13 34 L2 D14 I/O Data A14 35 L3 D15 I/O Data A15 36 M1 CAS0/ DQM0 O D7–D0 select signal CAS0 DQM0 37 M2 CAS1/ DQM1 O D15–D8 select signal CAS1 DQM1 38 M3 RD/WR O Read/write RD/WR RD/WR RD/WR RD/WR RD/WR 39 N1 CKIO O Clock output CKIO CKIO CKIO CKIO CKIO 40 K4 VDD Power Internal VDD 41 R4 VDDQ Power IO VDD 42 L4 VSS Power IO GND 43 M4 VDDQ Power I/O VDD 44 N2 RD/CASS/ FRAME O Read/CAS/ FRAME CAS OE FRAME 45 N3 CKE O Clock output enable 46 P1 RAS O RAS 47 P4 VDD Power Internal VDD 48 N4 VSS Power GND 49 P2 CS2 O Chip select 2 50 R1 CS3 O Chip select 3 51 R2 A0 O Address 52 R3 A1 O Address 53 T1 A2 O Address 54 T2 A3 O Address 55 P3 VDDQ Power IO VDD 56 T4 VSS Power GND Page 36 of 1128 OE CKE RAS RAS CS2 (CS2) CS2 CS2 CS3 (CS3) CS3 CS3 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Number Pin Name I/O Function 57 T3 A4 O Address 58 U1 A5 O Address 59 U2 A6 O Address 60 U3 A7 O Address 61 V1 A8 O Address 62 V2 A9 O Address 63 V3 A10 O Address 64 W1 A11 O Address 65 W2 A12 O Address Reset SRAM DRAM SDRAM PCMCIA MPX 66 Y1 A13 O Address 67 V7 VDDQ Power IO VDD 68 U4 VSS Power GND 69 Y2 A14 O Address 70 Y3 A15 O Address 71 W3 A16 O Address 72 Y4 A17 O Address 73 W4 CAS2/ DQM2 O D23–D16 select signal CAS2 DQM2 74 V4 CAS3/ DQM3 O D31–D24 select signal CAS3 DQM3 75 Y5 D16 I/O Data A16 76 W5 D17 I/O Data A17 77 V5 D18 I/O Data A18 78 Y6 D19 I/O Data A19 79 U6 VDDQ Power IO VDD 80 U5 VSS Power GND 81 U7 VDD Power Internal VDD 82 U8 VSS Power GND 83 W6 D20 I/O Data A20 84 V6 D21 I/O Data A21 85 Y7 D22 I/O Data A22 86 W7 D23 I/O Data A23 87 Y8 D24 I/O Data A24 88 W8 D25 I/O Data A25 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 37 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Number Pin Name I/O Function 89 V8 D26 I/O Data 90 Y9 D27 I/O Data 91 W9 D28 I/O Data 92 V9 D29 I/O Data 93 U9 VDDQ Power IO VDD 94 V10 VSS Power GND 95 Y10 D30 I/O Data ACCSIZE1 96 W10 D31 I/O Data ACCSIZE2 97 U10 VDD Power Internal VDD 98 U11 VSS Power GND 99 Y11 A18 O Address 100 W11 A19 O Address 101 V11 A20 O Address 102 Y12 A21 O Address 103 W12 A22 O Address 104 V12 A23 O Address 105 U15 VDDQ Power IO VDD 106 U17 VSS Power GND 107 Y13 A24 O Address 108 W13 A25 O Address 109 V13 WE2/ ICIORD O D23–D16 select signal WE2 ICIORD 110 Y14 WE3/ ICIOWR O D31–D24 select signal WE3 ICIOWR 111 U14 VDD Power Internal VDD 112 U13 VSS Power GND 113 W14 SLEEP I Sleep 114 Y15 PCIGNT4 O Bus grant (host function) 115 W15 PCIGNT3 O Bus grant (host function) 116 V15 PCIGNT2 O Bus grant (host function) 117 Y16 PCIREQ4 I* Bus grant (host function) Page 38 of 1128 Reset SRAM DRAM SDRAM PCMCIA MPX ACCSIZE0 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Number Pin Name 118 W16 PCIREQ3/ MD10 119 V14 VDDQ Power IO VDD 120 U16 VSS Power GND 121 V16 PCIREQ2/ MD9 I* Bus request (host function)/ mode 122 Y17 IDSEL I Configuration device select 123 W17 INTA O Interrupt (async) 124 V17 PCIRST O Reset output 125 Y18 PCICLK I PCI input clock 126 W18 PCIGNT1/ REQOUT O Bus grant (host function)/ bus request 127 V18 PCIREQ1/ GNTIN I Bus grant (host function)/ bus request 128 Y19 SERR I/O System error 129 Y20 AD31 I/O 130 W20 AD30 I/O 131 R17 VDDQ Power IO VDD 132 T17 VSS Power GND 133 W19 AD29 I/O 134 V20 AD28 135 V19 136 137 I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX I* Bus request (host function)/ mode MD10 PCI address/ data/port (Port) (Port) (Port) (Port) (Port) PCI address/ data/port (Port) (Port) (Port) (Port) (Port) PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) AD27 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) U20 AD26 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) U19 AD25 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 MD9 Page 39 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Number Pin Name I/O Function 138 U18 AD24 I/O PCI address/ data/port 139 T20 C/BE3 I/O PCI address/ data/port 140 T18 AD23 I/O 141 T19 AD22 142 R20 143 144 SRAM DRAM SDRAM PCMCIA MPX (Port) (Port) (Port) (Port) (Port) PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) AD21 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) P18 VDDQ Power IO VDD U12 VDDQ Power I/O VDD 145 P17 VDD Power Internal VDD 146 N17 VSS Power GND 147 R19 AD20 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 148 R18 AD19 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 149 P20 AD18 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 150 P19 AD17 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 151 N20 AD16 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 152 N18 C/BE2 I/O Command/ byte enable 153 N19 PCIFRAME I/O 154 M20 IRDY I/O Initiator ready 155 M19 TRDY I/O Target ready Bus cycle 156 M18 DEVSEL I/O Device select 157 M17 VDDQ Power IO VDD 158 L17 VDD Power Internal VDD 159 L20 PCISTOP I/O Transaction stop 160 L19 PCILOCK I/O Exclusive access 161 L18 PERR I/O Parity error Page 40 of 1128 Reset R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Number Pin Name I/O Function 162 K20 PAR I/O Parity 163 K19 C/BE1 I/O Command/ byte enable 164 K18 AD15 I/O 165 J20 AD14 166 J19 167 SRAM DRAM SDRAM PCMCIA MPX PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) AD13 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) J18 AD12 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 168 H20 AD11 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 169 F17 VDDQ Power IO VDD 170 K17 VSS Power GND 171 H19 AD10 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 172 H18 AD9 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 173 G20 AD8 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 174 G19 C/BE0 I/O Command/ byte enable 175 G17 VDD Power Internal VDD 176 H17 VSS Power GND 177 F20 AD7 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 178 F19 AD6 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 179 F18 AD5 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 180 E20 AD4 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 181 E19 AD3 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 182 E18 AD2 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 183 G18 VDDQ Power I/O VDD R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Reset Page 41 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Number Pin Name I/O Function 184 J17 VDDQ Power I/O VDD 185 D20 AD1 I/O 186 D19 AD0 187 D18 188 189 SRAM DRAM SDRAM PCMCIA MPX PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) IRL0 I Interrupt 0 C20 IRL1 I Interrupt 1 C19 IRL2 I Interrupt 2 190 B20 IRL3 I Interrupt 3 191 B18 VSS-RTC Power RTC GND 192 E17 VSS Power GND 193 A20 XTAL2 O RTC crystal resonator pin 194 A19 EXTAL2 I RTC crystal resonator pin 195 A18 VDD-RTC Power RTC VDD 196 B19 VDDQ Power IO VDD 197 C18 CA I Hardware standby 198 A17 RESET I Reset 199 B17 TRST I Reset (H-UDI) 200 C17 MRESET I Manual reset 201 A16 NMI I Nonmaskable interrupt 202 B16 BACK/ BSREQ O Bus acknowledge/ bus request 203 C16 BREQ/ BSACK I Bus request/bus acknowledge 204 A15 MD6/ IOIS16 I Mode/IOIS16 (PCMCIA) 205 B15 RDY I Bus ready 206 C15 TXD O SCI data output 207 C14 VDDQ Power IO VDD 208 C11 VSS Power GND Page 42 of 1128 Reset RESET IOIS16 MD6 RDY RDY RDY R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Number Pin Name I/O Function 209 D14 VDD Power Internal VDD 210 D16 VSS Power GND 211 A14 MD2/RXD2 I Mode/SCIF data input 212 B14 RXD I SCI data input 213 A13 TCLK I/O RTC/TMU clock 214 B13 MD8/RTS2 I/O Mode/SCIF data control (RTS) 215 C13 SCK I/O SCIF clock 216 A12 MD1/TXD2 I/O 217 B12 218 Reset SRAM DRAM SDRAM PCMCIA MPX MD2 RXD2 RXD2 RXD2 RXD2 RXD2 MD8 RTS2 RTS2 RTS2 RTS2 RTS2 Mode/SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 MD0/SCK2 I/O Mode/SCIF clock MD0 SCK2 SCK2 SCK2 SCK2 SCK2 C12 MD7/CTS2 Mode/SCIF data control (RTS) MD7 CTS2 CTS2 CTS2 CTS2 CTS2 219 A11 AUDSYNC AUD Sync 220 B11 AUDCK AUD clock 221 D15 VDDQ Power IO VDD 222 D10 VSS Power GND 223 A10 AUDATA0 AUD data 224 B10 AUDATA1 AUD data I/O 225 D11 VDD Power Internal VDD 226 D17 VSS Power GND 227 C10 AUDATA2 AUD data 228 A9 AUDATA3 AUD data 229 D8 VSS GND 230 B9 MD3/CE2A I/O Mode/ PCMCIA-CE MD3 CE2A 231 C9 MD4/CE2B I/O Mode/ PCMCIA-CE MD4 CE2B 232 A8 MD5 I Mode MD5 233 D12 VDDQ Power IO VDD 234 D9 VDDQ Power I/O VDD R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 43 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Number Pin Name I/O Function 235 B8 DACK0 O DMAC0 bus acknowledge 236 C8 DACK1 O DMAC1 bus acknowledge 237 A7 DRAK0 O DMAC0 request acknowledge 238 B7 DRAK1 O DMAC1 request acknowledge 239 D7 VDD Power Internal VDD 240 D6 VDDQ Power I/O VDD 241 A6 STATUS0 O Status 242 B6 STATUS1 O Status 243 C6 DREQ0 I Request from DMAC0 244 C5 DREQ1 I Request from DMAC1 245 B5 ASEBRK/ BRKACK I/O Pin break/ acknowledge (H-UDI) 246 C4 TDO O Data out (H-UDI) 247 C7 VDDQ Power IO VDD 248 D13 VSS Power GND 249 A5 VDD-PLL2 Power PLL2 VDD 250 B4 VSS-PLL2 Power PLL2 GND 251 A4 VDD-PLL1 Power PLL1 VDD 252 C3 VSS-PLL1 Power PLL1 GND 253 B3 VDD-CPG Power CPG VDD 254 A3 VSS-CPG Power CPG GND 255 A2 XTAL O Crystal resonator 256 A1 EXTAL I External input clock/crystal resonator 257 H8 VSS Power GND 258 J8 VSS Power GND 259 K8 VSS Power GND Page 44 of 1128 Reset SRAM DRAM SDRAM PCMCIA MPX R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Number Pin Name I/O Function 260 L8 VSS Power GND 261 M8 VSS Power GND 262 N8 VSS Power GND 263 N9 VSS Power GND 264 N10 VSS Power GND 265 N11 VSS Power GND 266 N12 VSS Power GND 267 N13 VSS Power GND 268 M13 VSS Power GND 269 L13 VSS Power GND 270 K13 VSS Power GND 271 J13 VSS Power GND 272 H13 VSS Power GND 273 H12 VSS Power GND 274 H11 VSS Power GND 275 H10 VSS Power GND 276 H9 VSS Power GND 277 J9 VSS Power GND 278 K9 VSS Power GND 279 L9 VSS Power GND 280 M9 VSS Power GND 281 M10 VSS Power GND 282 M11 VSS Power GND 283 M12 VSS Power GND 284 L12 VSS Power GND 285 K12 VSS Power GND 286 J12 VSS Power GND 287 J11 VSS Power GND 288 J10 VSS Power GND 289 K10 VSS Power GND 290 L10 VSS Power GND 291 L11 VSS Power GND 292 K11 VSS Power GND R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Reset SRAM DRAM SDRAM PCMCIA MPX Page 45 of 1128 Section 1 Overview SH7751 Group, SH7751R Group Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D. * I/O attribute is I/O when used as a port. Page 46 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 2 Programming Model Section 2 Programming Model 2.1 Data Formats The data formats handled by the SH-4 are shown in figure 2.1. 7 0 Byte (8 bits) 15 0 Word (16 bits) 31 0 Longword (32 bits) 31 30 Single-precision floating-point (32 bits) s exp 63 62 Double-precision floating-point (64 bits) 22 s 51 exp 0 fraction 0 fraction Figure 2.1 Data Formats R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 47 of 1128 Section 2 Programming Model 2.2 Register Configuration 2.2.1 Privileged Mode and Banks SH7751 Group, SH7751R Group Processor Modes: The SH-4 has two processor modes, user mode and privileged mode. The SH-4 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processor modes. General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processor mode change. In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC/STC instructions. In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed. Control Registers: Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processor modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers: System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), the program counter (PC), the floating-point status/control register (FPSCR), and the floating-point communication register (FPUL). Access to these registers does not depend on the processor mode. Page 48 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 2 Programming Model Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX. Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type Registers Initial Value* General registers R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, R8–R15 Undefined Control registers SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, IMASK = 1111 (H'F), reserved bits = 0, others undefined GBR, SSR, SPC, SGR, DBR Undefined VBR H'00000000 MACH, MACL, PR, FPUL Undefined PC H'A0000000 FPSCR H'00040001 FR0–FR15, XF0–XF15 Undefined System registers Floating-point registers Note: * Initialized by a power-on reset and manual reset. The register configuration in each processor mode is shown in figure 2.2. Switching between user mode and privileged mode is controlled by the processor mode bit (MD) in the status register. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 49 of 1128 Section 2 Programming Model 31 SH7751 Group, SH7751R Group 0 31 0 31 0 R0_BANK0*1*2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK1*1*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0*1*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SR SSR SR SSR GBR MACH MACL PR GBR MACH MACL PR VBR GBR MACH MACL PR VBR PC PC SPC PC SPC SGR SGR DBR (a) Register configuration in user mode R0_BANK0*1*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 (b) Register configuration in privileged mode (RB = 1) DBR R0_BANK1*1*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 (c) Register configuration in privileged mode (RB = 0) Notes: 1. The R0 register is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode. 2. Banked registers 3. Banked registers Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 4. Banked registers Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.2 CPU Register Configuration in Each Processor Mode Page 50 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 2.2.2 Section 2 Programming Model General Registers Figure 2.3 shows the relationship between the processor modes and general registers. The SH-4 has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0–R15 in one processor mode. The SH-4 has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below. • R0_BANK0–R7_BANK0 In user mode (SR.MD = 0), R0–R7 are always assigned to R0_BANK0–R7_BANK0. In privileged mode (SR.MD = 1), R0–R7 are assigned to R0_BANK0–R7_BANK0 only when SR.RB = 0. • R0_BANK1–R7_BANK1 In user mode, R0_BANK1–R7_BANK1 cannot be accessed. In privileged mode, R0–R7 are assigned to R0_BANK1–R7_BANK1 only when SR.RB = 1. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 51 of 1128 Section 2 Programming Model SH7751 Group, SH7751R Group SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0 R1 R2 R3 R4 R5 R6 R7 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 Figure 2.3 General Registers Programming Note: As the user's R0–R7 are assigned to R0_BANK0–R7_BANK0, and after an exception or interrupt R0–R7 are assigned to R0_BANK1–R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0–R7 (R0_BANK0–R7_BANK0). After a reset, the values of R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15 are undefined. Page 52 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 2.2.3 Section 2 Programming Model Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4). • Floating-point registers, FPRn_BANKi (32 registers) FPR0_BANK0, FPR1_BANK0, FPR2_BANK0, FPR3_BANK0, FPR4_BANK0, FPR5_BANK0, FPR6_BANK0, FPR7_BANK0, FPR8_BANK0, FPR9_BANK0, FPR10_BANK0, FPR11_BANK0, FPR12_BANK0, FPR13_BANK0, FPR14_BANK0, FPR15_BANK0 FPR0_BANK1, FPR1_BANK1, FPR2_BANK1, FPR3_BANK1, FPR4_BANK1, FPR5_BANK1, FPR6_BANK1, FPR7_BANK1, FPR8_BANK1, FPR9_BANK1, FPR10_BANK1, FPR11_BANK1, FPR12_BANK1, FPR13_BANK1, FPR14_BANK1, FPR15_BANK1 • Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 are assigned to FPR0_BANK0–FPR15_BANK0. When FPSCR.FR = 1, FR0–FR15 are assigned to FPR0_BANK1–FPR15_BANK1. • Double-precision floating-point registers or single-precision floating-point register pairs, DRi (8 registers): A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} • Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15} • Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0–XF15 are assigned to FPR0_BANK1–FPR15_BANK1. When FPSCR.FR = 1, XF0–XF15 are assigned to FPR0_BANK0–FPR15_BANK0. • Single-precision floating-point extended register pairs, XDi (8 registers): An XD register comprises two XF registers R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 53 of 1128 Section 2 Programming Model SH7751 Group, SH7751R Group XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} • Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPSCR.FR = 1 FPSCR.FR = 0 FV0 FV4 FV8 FV12 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 XF0 XF1 XD2 XF2 XF3 XD4 XF4 XF5 XD6 XF6 XF7 XD8 XF8 XF9 XD10 XF10 XF11 XD12 XF12 XF13 XD14 XF14 XF15 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 DR0 XMTRX XD0 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 DR0 FV0 DR2 DR4 FV4 DR6 DR8 FV8 DR10 DR12 FV12 DR14 Figure 2.4 Floating-Point Registers Page 54 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 2 Programming Model Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X = undefined)) 31 30 29 28 27 — MD RB BL 16 15 14 — FD 10 — 9 8 M Q 7 4 IMASK 3 2 — 1 0 S T Note: —: Reserved. These bits are always read as 0, and should only be written with 0. • MD: Processor mode MD = 0: User mode (some instructions cannot be executed, and some resources cannot be accessed) MD = 1: Privileged mode • RB: General register specification bit in privileged mode (set to 1 by a reset, exception, or interrupt) RB = 0: R0_BANK0–R7_BANK0 are accessed as general registers R0–R7. (R0_BANK1– R7_BANK1 can be accessed using LDC/STC instructions.) RB = 1: R0_BANK1–R7_BANK1 are accessed as general registers R0–R7. (R0_BANK0– R7_BANK0 can be accessed using LDC/STC instructions.) • BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt) BL = 1: Interrupt requests are masked. If a general exception other than a user break occurs while BL = 1, the processor switches to the reset state. • FD: FPU disable bit (cleared to 0 by a reset) FD = 1: An FPU instruction causes a general FPU disable exception, and if the FPU instruction is in a delay slot, a slot FPU disable exception is generated. (FPU instructions: H'F*** instructions, LDC(.L)/STS(.L) instructions for FPUL/FPSCR) • M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions. • IMASK: Interrupt mask level Interrupts of a lower level than IMASK are masked. IMASK does not change when an interrupt is generated. • S: Specifies a saturation operation for a MAC instruction. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 55 of 1128 Section 2 Programming Model SH7751 Group, SH7751R Group • T: True/false condition or carry/borrow bit Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC. Global base register, GBR (32 bits, initial value undefined): GBR is referenced as the base address in a GBR-referencing MOV instruction. Vector base register, VBR (32 bits, privilege protection, initial value = H'0000 0000): VBR is referenced as the branch destination base address in the event of an exception or interrupt. For details, see section 5, Exceptions. Saved general register 15, SGR (32 bits, privilege protection, initial value undefined): The contents of R15 are saved to SGR in the event of an exception or interrupt. Debug base register, DBR (32 bits, privilege protection, initial value undefined): When the user break debug function is enabled (BRCR.UBDE = 1), DBR is referenced as the user break handler branch destination address instead of VBR. 2.2.5 System Registers Multiply-and-accumulate register high, MACH (32 bits, initial value undefined) Multiply-and-accumulate register low, MACL (32 bits, initial value undefined) MACH/MACL is used for the added value in a MAC instruction, and to store a MAC instruction or MUL instruction operation result. Procedure register, PR (32 bits, initial value undefined): The return address is stored in PR in a subroutine call using a BSR, BSRF, or JSR instruction, and PR is referenced by the subroutine return instruction (RTS). Program counter, PC (32 bits, initial value = H'A000 0000): PC indicates the executing instruction address. Page 56 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 2 Programming Model Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 31 22 21 20 19 18 17 — FR SZ PR DN 12 11 Cause 7 6 Enable 2 Flag 1 0 RM Note: —: Reserved. These bits are always read as 0, and should only be written with 0. • FR: Floating-point register bank FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1– FPR15_BANK1 are assigned to XF0–XF15. FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1– FPR15_BANK1 are assigned to FR0–FR15. • SZ: Transfer size mode SZ = 0: The data size of the FMOV instruction is 32 bits. SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits). • PR: Precision mode PR = 0: Floating-point instructions are executed as single-precision operations. PR = 1: Floating-point instructions are executed as double-precision operations (the result of instructions for which double-precision is not supported is undefined). Do not set SZ and PR to 1 simultaneously; this setting is reserved. [SZ, PR = 11]: Reserved (FPU operation instruction is undefined.) • DN: Denormalization mode DN = 0: A denormalized number is treated as such. DN = 1: A denormalized number is treated as zero. • Cause: FPU exception cause field • Enable: FPU exception enable field • Flag: FPU exception flag field FPU Error (E) Invalid Division Operation (V) by Zero (Z) Overflow (O) Underflow Inexact (U) (I) Cause FPU exception cause field Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Enable FPU exception enable field None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag field None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 57 of 1128 Section 2 Programming Model SH7751 Group, SH7751R Group When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared. • RM: Rounding mode RM = 00: Round to Nearest RM = 01: Round to Zero RM = 10: Reserved RM = 11: Reserved • Bits 22 to 31: Reserved Floating-point communication register, FPUL (32 bits, initial value undefined): Data transfer between FPU registers and CPU registers is carried out via the FPUL register. Programming Note: When SZ = 1 and big endian mode is selected, FMOV can be used for double-precision floating-point data load or store operations. In little endian mode, two 32-bit data size moves must be executed, with SZ = 0, to load or store a double-precision floating-point data. 2.3 Memory-Mapped Registers Appendix A shows the control registers mapped to memory. The control registers are doublemapped to the following two memory areas. All registers have two addresses. H'1C00 0000–H'1FFF FFFF H'FC00 0000–H'FFFF FFFF These two areas are used as follows. • H'1C00 0000–H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding filed of the TLB enables access to a memorymapped register. Accessing this area without using the address translation function of the MMU is not guaranteed. • H'FC00 0000–H'FFFF FFFF Access to area H'FC00 0000–H'FFFF FFFF in user mode will cause an address error. Memorymapped registers can be referenced in user mode by means of access that involves address translation. Page 58 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 2 Programming Model Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. 2.4 Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 Longword 2.5 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big endian or little endian byte order can be selected for the data format. The endian should be set with the MD5 external pin in a power-on reset. Big endian is selected when the MD5 pin is low, and little endian when high. The endian cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 59 of 1128 Section 2 Programming Model SH7751 Group, SH7751R Group The data format in memory is shown in figure 2.5. A+1 A 31 7 A+2 23 15 07 07 A+3 A + 11 A + 10 A + 9 7 0 31 07 0 7 0 15 Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8 15 0 15 Word 0 31 Big endian 15 07 07 0 07 0 0 15 Word 1 0 A+8 7 Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8 Word 1 Longword 23 31 0 Word 0 Longword 0 Address A + 4 Address A Little endian Figure 2.5 Data Formats In Memory Note: The SH-4 does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. 2.6 Processor States The SH-4 has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The power-on reset state is entered when the RESET pin goes low. The CPU enters the manual reset state if the RESET pin is high and the MRESET pin is low. For more information on resets, see section 5, Exceptions. In the power-on reset state, the internal state of the CPU and the on-chip peripheral module registers are initialized. In the manual reset state, the internal state of the CPU and registers of onchip peripheral modules other than the bus state controller (BSC) are initialized. Since the bus state controller (BSC) is not initialized in the manual reset state, refreshing operations continue. Refer to the register configurations in the relevant sections for further details. Exception-Handling State: This is a transient state during which the CPU's processor state flow is altered by a reset, general exception, or interrupt exception source. In the case of a reset, the CPU branches to address H'A000 0000 and starts executing the usercoded exception handling program. In the case of a general exception or interrupt, the program counter (PC) contents are saved in the saved program counter (SPC), the status register (SR) contents are saved in the saved status register (SSR), and the R15 contents are saved in saved general register 15 (SGR). The CPU Page 60 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 2 Programming Model branches to the start address of the user-coded exception service routine found from the sum of the contents of the vector base address and the vector offset. See section 5, Exceptions, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state the CPU executes program instructions in sequence. Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are three modes in the power-down state: sleep mode, deep sleep mode, and standby mode. For details, see section 9, Power-Down Modes. Bus-Released State: In this state the CPU has released the bus to a device that requested it. Transitions between the states are shown in figure 2.6. From any state when RESET = 0 RESET = 1 and MRESET = 0 Power-on reset state Manual reset state RESET = 0 Reset state RESET = 1 RESET = 1, MRESET = 1 Exception-handling state Bus request Bus request clearance Interrupt Exception interrupt Bus-released state Bus request Bus request End of exception transition processing Interrupt Bus request clearance Bus request clearance Program execution state SLEEP instruction with STBY bit cleared Sleep mode SLEEP instruction with STBY bit set Standby mode Power-down state Figure 2.6 Processor State Transitions R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 61 of 1128 Section 2 Programming Model 2.7 SH7751 Group, SH7751R Group Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset state or exception state is entered, the MD bit is set to 1. There are certain registers and bits which can only be accessed in privileged mode. Page 62 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH-4 can handle 29-bit external memory space from an 8-bit address space identifier and 32bit logical (virtual) address space. Address translation from virtual address to physical address is performed using the memory management unit (MMU) built into the SH-4. The MMU performs high-speed address translation by caching user-created address translation table information in an address translation buffer (translation lookaside buffer: TLB). The SH-4 has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 Kbytes, and 1 Mbyte). It is possible to set the virtual address space access right and implement storage protection independently for privileged mode and user mode. 3.1.2 Role of the MMU The MMU was conceived as a means of making efficient use of physical memory. As shown in figure 3.1, when a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory, but if the process increases in size to the point where it does not fit into physical memory, it becomes necessary to divide the process into smaller parts, and map the parts requiring execution onto physical memory on an ad hoc basis ((1)). Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process. The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden ((2)). With a virtual memory system, the size of the available virtual memory is much larger than the actual physical memory, and processes are mapped onto this virtual memory. Thus processes only have to consider their operation in virtual memory, and mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally managed by the OS, and physical memory switching is carried out so as to enable the virtual memory required by a task to be mapped smoothly onto physical memory. Physical memory switching is performed via secondary storage, etc. The virtual memory system that came into being in this way works to best effect in a time sharing system (TSS) that allows a number of processes to run simultaneously ((3)). Running a number of processes in a TSS did not increase efficiency since each process had to take account of physical memory mapping. Efficiency is improved and the load on each process reduced by the use of a virtual memory system ((4)). In this system, virtual memory is allocated to each process. The task of the MMU is to map a number of virtual memory areas onto physical memory in an efficient R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 63 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group manner. It is also provided with memory protection functions to prevent a process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. In such cases, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could be implemented by software alone, having address translation performed by software each time a process accessed physical memory would be very inefficient. For this reason, a buffer for address translation (the translation lookaside buffer: TLB) is provided in hardware, and frequently used address translation information is placed here. The TLB can be described as a cache for address translation information. However, unlike a cache, if address translation fails—that is, if an exception occurs—switching of the address translation information is normally performed by software. Thus memory management can be performed in a flexible manner by software. There are two methods by which the MMU can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space called a page (usually from 1 to 64 Kbytes in size). In the following descriptions, the address space in virtual memory in the SH-4 is referred to as virtual address space, and the address space in physical memory as physical address space. Page 64 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Physical memory Section 3 Memory Management Unit (MMU) Process 1 Physical memory Process 1 Virtual memory MMU Physical memory Process 1 (2) (1) Process 1 Physical memory Process 1 Virtual memory MMU Physical memory Process 2 Process 2 Process 3 Process 3 (3) (4) Figure 3.1 Role of the MMU R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 65 of 1128 Section 3 Memory Management Unit (MMU) 3.1.3 SH7751 Group, SH7751R Group Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbreviation R/W Initial 1 Value* P4 Address*2 Page table entry high register PTEH R/W Undefined H'FF00 0000 H'1F00 0000 32 Page table entry low register PTEL R/W Undefined H'FF00 0004 H'1F00 0004 32 Page table entry assistance register PTEA R/W Undefined H'FF00 0034 H'1F00 0034 32 Translation table base register TTB R/W Undefined H'FF00 0008 H'1F00 0008 32 TLB exception address register TEA R/W Undefined H'FF00 000C H'1F00 000C 32 MMU control register MMUCR R/W H'0000 0000 H'FF00 0010 H'1F00 0010 32 Name Area 7 Address*2 Acces s Size Notes: 1. The initial value is the value after a power-on reset or manual reset. 2. P4 address is the address when using the virtual/physical address space P4 area. The area 7 address is the address used when making an access from physical address space area 7 using the TLB. 3.1.4 Caution Operation is not guaranteed if an area designated as a reserved area in this manual is accessed. Page 66 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 3.2 Section 3 Memory Management Unit (MMU) Register Descriptions There are six MMU-related registers. 1. PTEH 31 10 9 VPN 8 7 0 — — ASID 2. PTEL 31 30 29 28 10 9 PPN — — — 8 7 — V SZ 6 5 PR 4 3 2 1 0 SZ C D SH WT 3. PTEA 31 4 3 2 TC 0 SA 4. TTB 31 0 TTB 5. TEA 31 0 Virtual address at which MMU exception or address error occurred 6. MMUCR 26 25 24 23 31 LRUI — — 18 17 16 15 URB — — 10 9 URC 8 7 6 5 4 3 2 1 0 SV — — — — — TI — AT SQMD Note: — indicates a reserved bit: the write value must be 0, and a read will return 0. Figure 3.2 MMU-Related Registers R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 67 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware. VPN varies according to the page size, but the VPN set by hardware when an exception occurs consists of the upper 22 bits of the virtual address which caused the exception. VPN setting can also be carried out by software. The number of the currently executing process is set in the ASID field by software. ASID is not updated by hardware. VPN and ASID are recorded in the UTLB by means of the LDLTB instruction. A branch to the P0, P3, or V0 area which uses the updated ASID after the ASID field in PTEH is rewritten should be made at least 6 instructions after the PTEH update instruction. 2. Page table entry low register (PTEL): Longword access to PTEL can be performed from H'FF00 0004 in the P4 area and H'1F00 0004 in area 7. PTEL is used to hold the physical page number and page management information to be recorded in the UTLB by means of the LDTLB instruction. The contents of this register are not changed unless a software directive is issued. 3. Page table entry assistance register (PTEA): Longword access to PTEA can be performed from H'FF00 0034 in the P4 area and H'1F00 0034 in area 7. PTEA is used to store assistance bits for PCMCIA access to the UTLB by means of the LDTLB instruction. When performing PCMCIA access with the MMU off, access is always performed using the values of the SA and TC bits in this register. Access to a PCMCIA interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. The contents of this register are not changed unless a software directive is issued. 4. Translation table base register (TTB): Longword access to TTB can be performed from H'FF00 0008 in the P4 area and H'1F00 0008 in area 7. TTB is used, for example, to hold the base address of the currently used page table. The contents of TTB are not changed unless a software directive is issued. This register can be freely used by software. 5. TLB exception address register (TEA): Longword access to TEA can be performed from H'FF00 000C in the P4 area and H'1F00 000C in area 7. After an MMU exception or address error exception occurs, the virtual address at which the exception occurred is set in TEA by hardware. The contents of this register can be changed by software. 6. MMU control register (MMUCR): MMUCR contains the following bits: LRUI: Least recently used ITLB URB: UTLB replace boundary URC: UTLB replace counter SQMD: Store queue mode bit SV: Single virtual mode bit Page 68 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group TI: AT: Section 3 Memory Management Unit (MMU) TLB invalidate Address translation bit Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0, P3, or U0 area should be located at least eight instructions after the MMUCR update instruction. MMUCR contents can be changed by software. The LRUI bits and URC bits may also be updated by hardware. • LRUI: LRU bits that indicate the ITLB entry for which replacement is to be performed. The LRU (least recently used) method is used to decide the ITLB entry to be replaced in the event of an ITLB miss. The entry to be purged from the ITLB can be confirmed using the LRUI bits. LRUI is updated by means of the algorithm shown below. A dash in this table means that updating is not performed. LRUI [5] [4] [3] [2] [1] [0] When ITLB entry 0 is used 0 0 0 — — — When ITLB entry 1 is used 1 — — 0 0 — When ITLB entry 2 is used — 1 — 1 — 0 When ITLB entry 3 is used — — 1 — 1 1 Other than the above — — — — — — When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by an ITLB miss. An asterisk in this table means “Don't care”. LRUI [5] [4] [3] [2] [1] [0] ITLB entry 0 is updated 1 1 1 * * * ITLB entry 1 is updated 0 * * 1 1 * ITLB entry 2 is updated * 0 * 0 * 1 ITLB entry 3 is updated * * 0 * 0 0 Other than the above Setting prohibited R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 69 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group Ensure that values for which “Setting prohibited” is indicated in the above table are not set at the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update. • URB: Bits that indicate the UTLB entry boundary at which replacement is to be performed. Valid only when URB > 0. • URC: Random counter for indicating the UTLB entry for which replacement is to be performed with an LDTLB instruction. URC is incremented each time the UTLB is accessed. When URB > 0, URC is reset to 0 when the condition URC = URB occurs. Also note that, if a value is written to URC by software which results in the condition URC > URB, incrementing is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB instruction. • SQMD: Store queue mode bit. Specifies the right of access to the store queues. 0: User/privileged access possible 1: Privileged access possible (address error exception in case of user access) • SV: Bit that switches between single virtual memory mode and multiple virtual memory mode. 0: Multiple virtual memory mode 1: Single virtual memory mode When this bit is changed, ensure that 1 is also written to the TI bit. • TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB bits. This bit always returns 0 when read. • AT: Address translation enable bit. Specifies MMU enabling or disabling. 0: MMU disabled 1: MMU enabled MMU exceptions are not generated when the AT bit is 0. In the case of software that does not use the MMU, therefore, the AT bit should be cleared to 0. Page 70 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 3.3 Address Space 3.3.1 Physical Address Space Section 3 Memory Management Unit (MMU) The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical address space. The physical address space is divided into a number of areas, as shown in figure 3.3. The physical address space is permanently mapped onto 29-bit external memory space; this correspondence can be implemented by ignoring the upper 3 bits of the physical address space addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1 to P4 areas (except the store queue area) in user mode will cause an address error. External memory space H'0000 0000 P0 area Cacheable H'8000 0000 H'A000 0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'0000 0000 U0 area Cacheable H'8000 0000 P1 area Cacheable P2 area Non-cacheable Address error H'C000 0000 P3 area Cacheable H'E000 0000 P4 area Non-cacheable Store queue area Privileged mode User mode H'FFFF FFFF Address error H'E000 0000 H'E400 0000 H'FFFF FFFF Figure 3.3 Physical Address Space (MMUCR.AT = 0) When performing access from the CPU to a PCMCIA interface area in the SH-4, access is always performed using the values of the SA and TC bits set in the PTEA register. Access to a PCMCIA interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn, R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 71 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. For details, see section 14, Direct Memory Access Controller (DMAC). P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or not the cache is used is determined by the cache control register (CCR). When the cache is used, with the exception of the P1 area, switching between the copy-back method and the write-through method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area also appears in these areas. P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3 bits of an address gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area also appears in this area. P4 Area: The P4 area is mapped onto SH-4 on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4. H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 H'F500 0000 H'F600 0000 H'F700 0000 Instruction cache address array Instruction cache data array Instruction TLB address array Instruction TLB data arrays 1 and 2 Operand cache address array Operand cache data array Unified TLB address array Unified TLB data arrays 1 and 2 H'F800 0000 Reserved area H'FC00 0000 Control register area H'FFFF FFFF Figure 3.4 P4 Area Page 72 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the MMUCR.SQMD bit. For details, see section 4.7, Store Queues. The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache address array. For details, see section 4.5.1, IC Address Array. The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data array. For details, see section 4.5.2, IC Data Array. The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB address array. For details, see section 3.7.1, ITLB Address Array. The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2. The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address array. For details, see section 4.5.3, OC Address Array. The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data array. For details, see section 4.5.4, OC Data Array. The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address array. For details, see section 3.7.4, UTLB Address Array. The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1 and 2. For details, see sections 3.7.5, UTLB Data Array 1, and 3.7.6, UTLB Data Array 2. The area from H'FC00 0000 to H'FFFF FFFF is the on-chip peripheral module control register area. For details, see appendix A, Address List. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 73 of 1128 Section 3 Memory Management Unit (MMU) 3.3.2 SH7751 Group, SH7751R Group External Memory Space The SH-4 supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC). H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 (reserved area) Figure 3.5 External Memory Space Page 74 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 3.3.3 Section 3 Memory Management Unit (MMU) Virtual Address Space Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical address space in the SH-4 to be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256. This is called the virtual address space. Mapping from virtual address space to 29-bit external memory space is carried out using the TLB. Only when area 7 in external memory space is accessed using virtual address space, addresses H'1C00 0000 to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area control register area in the physical address space. Virtual address space is illustrated in figure 3.6. 256 External memory space 256 Area 0 Area 1 Area 2 P0 area Cacheable Address translation possible Area 3 Area 4 Area 5 U0 area Cacheable Address translation possible Area 6 Area 7 P1 area Cacheable Address translation not possible P2 area Non-cacheable Address translation not possible Address error P3 area Cacheable Address translation possible P4 area Non-cacheable Address translation not possible Store queue area Privileged mode User mode Address error Figure 3.6 Virtual Address Space (MMUCR.AT = 1) In the state of cache enabling, when the areas of P0, P3, and U0 are mapped onto the area of the PCMCIA interface by means of the TLB, it is necessary either to specify 1 for the WT bit or to specify 0 for the C bit on that page. At that time, the regions are accessed by the values of SA and TC set in page units of the TLB. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 75 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group Here, access to an area of the PCMCIA interface by accessing an area of P1, P2, or P4 from the CPU is disabled. In addition, the PCMCIA interface is always accessed by the DMAC with the values of CHCRn, SSAn, CHCRn.DsAn, CHCRn.STC and CHCRn.DTC in the DMAC. For details, see Section 14, Direct Memory Access Controller (DMAC). P0, P3, U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area, and U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and address translation using the TLB. These areas can be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page units. When CCR is in the cache-enabled state and the cacheability bit (C bit) in the TLB is 1, accesses can be performed using the cache. In write accesses to the cache, switching between the copy-back method and the write-through method is indicated by the TLB write-through bit (WT bit), and is specified in page units. Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in external memory space are allocated to the control register area. This enables control registers to be accessed from the U0 area in user mode. In this case, the C bit for the corresponding page must be cleared to 0. P1, P2, P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or P4 area (except for the store queue area). Accesses to these areas are the same as for physical address space. The store queue area can be mapped onto any external memory space by the MMU. However, operation in the case of an exception differs from that for normal P0, U0, and P3 spaces. For details, see section 4.7, Store Queues. 3.3.4 On-Chip RAM Space In the SH-4, half of the operand cache can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0, U0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area. Data accesses (byte/word/longword/quadword) can be used in this area. This area can only be used in RAM mode. 3.3.5 Address Translation When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes. Fast address translation is achieved by caching the contents of the address translation table located in external memory into the TLB. In the SH-4, basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the event Page 76 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) of an access to an area other than the P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the P1 or P2 area, the physical address is uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3 area, the TLB is searched using the virtual address, and if the virtual address is recorded in the TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and processing switches to the TLB miss exception handling routine. In the TLB miss exception handling routine, the address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the TLB. After the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the MMUCR.SV bit. In the single virtual memory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined. In the multiple virtual memory system, a number of processes run while sharing the virtual address space, and a particular virtual address may be translated into different physical addresses depending on the process. The only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the TLB address comparison method (see section 3.4.3, Address Translation Method). 3.3.7 Address Space Identifier (ASID) In multiple virtual memory mode, the 8-bit address space identifier (ASID) is used to distinguish between processes running simultaneously while sharing the virtual address space. Software can set the ASID of the currently executing process in PTEH in the MMU. The TLB does not have to be purged when processes are switched by means of ASID. In single virtual memory mode, ASID is used to provide memory protection for processes running simultaneously while using the virtual memory space on an exclusive basis. Notes: 1. In single virtual memory mode of the SH-4, entries with the same virtual page number (VPN) but different ASIDs cannot be set in the TLB simultaneously. 2. When the SH7751 is operating in single virtual memory mode and user mode, the LSI may hang during hardware ITLB miss handling (see section 3.5.4, Hardware ITLB Miss Handling), or an ITLB multiple hit exception may occur, if an ITLB miss occurs and the UTLB contains address translation information including an ITLB miss address R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 77 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group with a different ASID and unshared state (SH bit is 0). To avoid this, use workaround (1) or (2) below. (1) Purge the UTLB when switching the ASID values (PTEH and ASID) of the current processing. (2) Manage the behavior of program instruction addresses in user mode so that no instruction is executed in an address area (including overrun prefetch of an instruction) that is registered in the UTLB with a different ASID and unshared address translation information. Note that accessing a different ASID in single virtual memory mode can only be used to trigger an exception during data access. 3.4 TLB Functions 3.4.1 Unified TLB (UTLB) Configuration The unified TLB (UTLB) is so called because of its use for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the instruction TLB in the event of an ITLB miss Information in the address translation table located in external memory is cached into the UTLB. The address translation table contains virtual page numbers and address space identifiers, and corresponding physical page numbers and page management information. Figure 3.7 shows the overall configuration of the UTLB. The UTLB consists of 64 fully-associative type entries. Figure 3.8 shows the relationship between the address format and page size. Entry 0 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 1 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 2 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Figure 3.7 UTLB Configuration Page 78 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) • 1-Kbyte page Virtual address 10 9 31 VPN 0 Physical address 10 9 28 Offset PPN 0 Offset • 4-Kbyte page Virtual address 12 11 31 VPN 0 Physical address 12 11 28 Offset PPN 0 Offset • 64-Kbyte page Virtual address 16 15 31 VPN 0 Physical address 16 15 28 Offset PPN 0 Offset • 1-Mbyte page Virtual address 20 19 31 VPN 0 Offset Physical address 20 19 28 PPN 0 Offset Figure 3.8 Relationship between Page Size and Address Format • VPN: Virtual page number For 1-Kbyte page: upper 22 bits of virtual address For 4-Kbyte page: upper 20 bits of virtual address For 64-Kbyte page: upper 16 bits of virtual address For 1-Mbyte page: upper 12 bits of virtual address • ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 79 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page 10: 64-Kbyte page 11: 1-Mbyte page • V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. • PPN: Physical page number Upper 22 bits of the physical address. With a 1-Kbyte page, PPN bits [28:10] are valid. With a 4-Kbyte page, PPN bits [28:12] are valid. With a 64-Kbyte page, PPN bits [28:16] are valid. With a 1-Mbyte page, PPN bits [28:20] are valid. The synonym problem must be taken into account when setting the PPN (see section 3.5.5, Avoiding Synonym Problems). • PR: Protection key data 2-bit data expressing the page access right as a code. 00: Can be read only, in privileged mode 01: Can be read and written in privileged mode 10: Can be read only, in privileged or user mode 11: Can be read and written in privileged mode or user mode Page 80 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1. • D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed • WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or clear the C bit to 0. • SA: Space attribute bits Valid only when the page is mapped onto PCMCIA connected to area 5 or 6. 000: Undefined 001: Variable-size I/O space (base size according to IOIS16 signal) 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit common memory space 101: 16-bit common memory space 110: 8-bit attribute memory space 111: 16-bit attribute memory space • TC: Timing control bit Used to select wait control register bits in the bus control unit for areas 5 and 6. 0: WCR2 (A5W2–A5W0) and PCR (A5PCW1–A5PCW0, A5TED2–A5TED0, A5TEH2– A5TEH0) are used 1: WCR2 (A6W2–A6W0) and PCR (A6PCW1–A6PCW0, A6TED2–A6TED0, A6TEH2– A6TEH0) are used R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 81 of 1128 Section 3 Memory Management Unit (MMU) 3.4.2 SH7751 Group, SH7751R Group Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries. The address translation information is almost the same as that in the UTLB, but with the following differences: 1. D and WT bits are not supported. 2. There is only one PR bit, corresponding to the upper of the PR bits in the UTLB. Entry 0 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Entry 1 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Entry 2 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Entry 3 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Figure 3.9 ITLB Configuration 3.4.3 Address Translation Method Figures 3.10 and 3.11 show flowcharts of memory accesses using the UTLB and ITLB. Page 82 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Data access to virtual address (VA) VA is in P4 area VA is in P2 area On-chip I/O access 0 VA is in P1 area VA is in P0, U0, or P3 area No CCR.OCE? MMUCR.AT = 1 1 0 Yes CCR.CB? CCR.WT? 0 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) No Yes No VPNs match and ASIDs match and V=1 No VPNs match and V = 1 Yes Yes No Only one entry matches Data TLB miss exception Yes SR.MD? 0 (User) 1 (Privileged) PR? 00 or 01 W Data TLB multiple hit exception PR? 11 10 R/W? R/W? R R 01 or 11 W W D? 0 Data TLB protection violation exception 1 00 or 10 R/W? R/W? R R W Data TLB protection violation exception Initial page write exception C=1 and CCR.OCE = 1 No Yes Cache access in copy-back mode 0 WT? 1 Cache access in write-through mode Memory access (Non-cacheable) Figure 3.10 Flowchart of Memory Access Using UTLB R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 83 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group Instruction access to virtual address (VA) VA is in P4 area Access prohibited VA is in P2 area VA is in P1 area VA is in P0, U0, or P3 area No 0 CCR.ICE? MMUCR.AT = 1 1 Yes No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) Yes No No VPNs match and V = 1 VPNs match and ASIDs match and V=1 Yes Only one entry matches Hardware ITLB miss handling Search UTLB Yes Match? Yes No Yes Record in ITLB No SR.MD? Instruction TLB miss exception 0 (User) 1 (Privileged) 0 PR? Instruction TLB multiple hit exception 1 Instruction TLB protection violation exception C=1 and CCR.ICE = 1 No Yes Cache access Memory access (Non-cacheable) Figure 3.11 Flowchart of Memory Access Using ITLB Page 84 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 3.5 MMU Functions 3.5.1 MMU Hardware Management Section 3 Memory Management Unit (MMU) The SH-4 supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2. The MMU determines the cache access status on the basis of the page management information read during address translation (C, WT, SA, and TC bits). 3. If address translation cannot be performed normally in a data access or instruction access, the MMU notifies software by means of an MMU exception. 4. If address translation information is not recorded in the ITLB in an instruction access, the MMU searches the UTLB, and if the necessary address translation information is recorded in the UTLB, the MMU copies this information into the ITLB in accordance with MMUCR.LRUI. 3.5.2 MMU Software Management Software processing for the MMU consists of the following: 1. Setting of MMU-related registers. Some registers are also partially updated by hardware automatically. 2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB. ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. For deleting or reading UTLB/ITLB entries, it is possible to access the memory-mapped UTLB/ITLB. 3. MMU exception handling. When an MMU exception occurs, processing is performed based on information set by hardware. 3.5.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH-4 copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 85 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in figure 3.12. MMUCR 31 26 25 24 23 LRUI — 18 17 16 15 URB — 10 9 8 7 URC SV 3 2 1 0 — TI — AT SQMD Entry specification PTEL 31 PTEH 31 10 9 8 7 VPN — 10 9 8 7 6 5 4 3 2 1 0 29 28 — PPN — V SZ PR SZ C D SHWT 0 PTEA ASID 31 4 3 2 — TC 0 SA Write Entry 0 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 1 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 2 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC UTLB Figure 3.12 Operation of LDTLB Instruction 3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH-4 searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB. This procedure is known as hardware ITLB miss handling. If the necessary address translation Page 86 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) information is not found in the UTLB search, an instruction TLB miss exception is generated and processing passes to software. 3.5.5 Avoiding Synonym Problems When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is recorded in a number of cache entries, and it becomes impossible to guarantee data integrity. This problem does not occur with the instruction TLB or instruction cache. In the SH-4, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-Kbyte page, and bits [13:12] of the virtual address in the case of a 4-Kbyte page, are subject to address translation. As a result, bits [13:10] of the physical address after translation may differ from bits [13:10] of the virtual address. Consequently, the following restrictions apply to the recording of address translation information in UTLB entries. 1. When address translation information whereby a number of 1-Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:10] values are the same. 2. When address translation information whereby a number of 4-Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:12] values are the same. 3. Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different page size. 4. Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different page size. The above restrictions apply only when performing accesses using the cache. When cache index mode is used, VPN [25] is used for the entry address instead of VPN [13], and therefore the above restrictions apply to VPN [25]. Note: When multiple items of address translation information use the same physical memory to provide for future SuperH RISC engine family expansion, ensure that the VPN [20:10] values are the same. Also, do not use the same physical address for address translation information of different page sizes. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 87 of 1128 Section 3 Memory Management Unit (MMU) 3.6 SH7751 Group, SH7751R Group MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 3.10 and 3.11 for the conditions under which each of these exceptions occurs. 3.6.1 Instruction TLB Multiple Hit Exception An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the virtual address to which an instruction access has been made. If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling, a data TLB multiple hit exception will result. When an instruction TLB multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. Hardware Processing: In the event of an instruction TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The ITLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 3.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. The instruction TLB miss exception processing carried out by hardware and software is shown below. This is the same as the processing for a data TLB miss exception. Page 88 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. 2. 3. 4. 5. 6. 7. 8. 9. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'040 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the instruction TLB miss exception handling routine. Software Processing (Instruction TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the TLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 89 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group The instruction TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1. 2. 3. 4. 5. 6. 7. 8. 9. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'0A0 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. Set the current R15 value in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the instruction TLB protection violation exception handling routine. Software Processing (Instruction TLB Protection Violation Exception Handling Routine): Resolve the instruction TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling. When a data TLB multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted. Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Page 90 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Software Processing (Reset Routine): The UTLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 3.6.5 Data TLB Miss Exception A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries. The data TLB miss exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write, in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR, and sets the R15 contents at the time in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the data TLB miss exception handling routine. Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 91 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'0A0 in the case of a read, or H'0C0 in the case of a write, in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. Page 92 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 3.6.7 Section 3 Memory Management Unit (MMU) Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. The initial page write exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an initial page write exception, hardware carries out the following processing: 1. 2. 3. 4. 5. 6. 7. 8. 9. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'080 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the initial page write exception handling routine. Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table entry recorded in external memory. If necessary, the values of the SA and TC bits should be written to PTEA. 4. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 5. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 93 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.7 Memory-Mapped TLB Configuration To enable the ITLB and UTLB to be managed by software, their contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in the other area. A branch to an area other than the P2 area should be made at least 8 instructions after this MOV instruction. The ITLB and UTLB are allocated to the P4 area in physical address space. VPN, V, and ASID in the ITLB can be accessed as an address array, PPN, V, SZ, PR, C, and SH as data array 1, and SA and TC as data array 2. VPN, D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and SH as data array 1, and SA and TC as data array 2. V and D can be accessed from both the address array side and the data array side. Only longword access is possible. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. 3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array, and the entry is selected by bits [9:8]. As longword access is used, 0 should be specified for address field bits [1:0]. In the data field, VPN is indicated by bits [31:10], V by bit [8], and ASID by bits [7:0]. The following two kinds of operation can be used on the ITLB address array: 1. ITLB address array read VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB address array write VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. Page 94 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 31 Section 3 Memory Management Unit (MMU) 24 23 10 9 8 7 Address field 1 1 1 1 0 0 1 0 0 E 31 10 9 8 7 Data field VPN Legend: VPN: Virtual page number V: Validity bit E: Entry V 0 ASID ASID: Address space identifier : Reserved bits (0 write value, undefined read value) Figure 3.13 Memory-Mapped ITLB Address Array 3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F30 indicating ITLB data array 1, and the entry is selected by bits [9:8]. In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bit [6], C by bit [3], and SH by bit [1]. The following two kinds of operation can be used on ITLB data array 1: 1. ITLB data array 1 read PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 1 write PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 95 of 1128 Section 3 Memory Management Unit (MMU) 31 SH7751 Group, SH7751R Group 24 23 10 9 8 7 Address field 1 1 1 1 0 0 1 1 0 E 31 30 29 28 Data field 10 9 8 7 6 5 4 3 2 1 0 V PPN Legend: PPN: Physical page number V: Validity bit E: Entry SZ: Page size bits 0 C PR SZ SH PR: Protection key data C: Cacheability bit SH: Share status bit : Reserved bits (0 write value, undefined read value) Figure 3.14 Memory-Mapped ITLB Data Array 1 3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2, and the entry is selected by bits [9:8]. In the data field, SA is indicated by bits [2:0], and TC by bit [3]. The following two kinds of operation can be used on ITLB data array 2: 1. ITLB data array 2 read SA and TC are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 2 write SA and TC specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. Page 96 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) 31 24 23 Address field 1 1 1 1 0 0 1 1 1 10 9 8 7 0 E 31 4 3 2 0 Data field SA Legend: TC: Timing control bit E: Entry TC SA: Space attribute bits : Reserved bits (0 write value, undefined read value) Figure 3.15 Memory-Mapped ITLB Data Array 2 3.7.4 UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, D, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0]. The following three kinds of operation can be used on the UTLB address array: 1. UTLB address array read VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. UTLB address array write (non-associative) VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. UTLB address array write (associative) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 97 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group When a write is performed with the A bit in the address field set to 1, comparison of all the UTLB entries is carried out using the VPN specified in the data field and PTEH.ASID. The usual address comparison rules are followed, but if a UTLB miss occurs, the result is no operation, and an exception is not generated. If the comparison identifies a UTLB entry corresponding to the VPN specified in the data field, D and V specified in the data field are written to that entry. If there is more than one matching entry, a data TLB multiple hit exception results. This associative operation is simultaneously carried out on the ITLB, and if a matching entry is found in the ITLB, V is written to that entry. Even if the UTLB comparison results in no operation, a write to the ITLB side only is performed as long as there is an ITLB match. If there is a match in both the UTLB and ITLB, the UTLB information is also written to the ITLB. 31 24 23 Address field 1 1 1 1 0 1 1 0 10 9 8 7 VPN Legend: VPN: Virtual page number Validity bit V: Entry E: Dirty bit D: 2 1 0 A E 31 30 29 28 Data field 8 7 14 13 D V 0 ASID ASID: Address space identifier A: Association bit : Reserved bits (0 write value, undefined read value) Figure 3.16 Memory-Mapped UTLB Address Array 3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1, and the entry is selected by bits [13:8]. In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bits [6:5], C by bit [3], D by bit [2], SH by bit [1], and WT by bit [0]. The following two kinds of operation can be used on UTLB data array 1: Page 98 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) 1. UTLB data array 1 read PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 1 write PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 1 1 1 0 14 13 10 9 8 7 6 5 4 3 2 1 0 PPN Legend: PPN: Physical page number Validity bit V: Entry E: SZ: Page size bits D: Dirty bit 0 E 31 30 29 28 Data field 8 7 V PR C D SZ SH WT PR: Protection key data C: Cacheability bit SH: Share status bit WT: Write-through bit : Reserved bits (0 write value, undefined read value) Figure 3.17 Memory-Mapped UTLB Data Array 1 3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2, and the entry is selected by bits [13:8]. In the data field, TC is indicated by bit [3], and SA by bits [2:0]. The following two kinds of operation can be used on UTLB data array 2: 1. UTLB data array 2 read SA and TC are read into the data field from the UTLB entry corresponding to the entry set in the address field. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 99 of 1128 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 2. UTLB data array 2 write SA and TC specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 1 1 1 1 14 13 8 7 0 E 31 4 3 2 Data field 0 SA Legend: TC: Timing control bit E: Entry TC SA: Space attribute bits : Reserved bits (0 write value, undefined read value) Figure 3.18 Memory-Mapped UTLB Data Array 2 3.8 Usage Notes 1. Address Space Identifier (ASID) in Single Virtual Memory Mode Refer to the note in 3.3.7, Address Space Identifier (ASID). Page 100 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches Section 4 Caches 4.1 Overview 4.1.1 Features The SH7751 has an on-chip 8-Kbyte instruction cache (IC) for instructions and 16-Kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 Kbytes) can also be used as onchip RAM. The features of these caches are summarized in table 4.1. The SH7751 has an on-chip 16-Kbyte instruction cache (IC) for instructions and 32-Kbyte operand cache (OC) for data. Half of the operand cache memory (16 Kbytes) can also be used as on-chip RAM. When the EMODE bit in the CCR register is cleared to 0 in the SH7751R, both the IC and OC are set to SH7751 compatible mode. When the EMODE bit in the CCR register is set to 1, the cache characteristics are as shown in table 4.2. After a power-on reset or manual reset, the initial value of the EMODE bit is 0. This LSI supports two 32-byte store queues (SQs) for performing high-speed writes to external memory. SQ features are shown in table 4.3. Table 4.1 Cache Features (SH7751) Item Instruction Cache Operand Cache Capacity 8-Kbyte cache 16-Kbyte cache or 8-Kbyte cache + 8-Kbyte RAM Type Direct mapping Direct mapping Line size 32 bytes 32 bytes Entries 256 entry 512 entry Write method R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Copy-back/write-through selectable Page 101 of 1128 Section 4 Caches Table 4.2 SH7751 Group, SH7751R Group Cache Features (SH7751R) Item Instruction Cache Operand Cache Capacity 16-Kbyte cache 32-Kbyte cache or 16-Kbyte cache + 16-Kbyte RAM Type 2-way set-associative 2-way set-associative Line size 32 bytes 32 bytes Entries 256 entry/way 512 entry/way Write method Replace method Table 4.3 Copy-back/write-through selectable LRU (Least Recently Used) algorithm LRU (Least Recently Used) algorithm Store Queue Features Item Store Queues Capacity 2 × 32 bytes Addresses H'E000 0000 to H'E3FF FFFF Write Store instruction (1-cycle write) Write-back Prefetch instruction (PREF instruction) Access right MMU off: according to MMUCR.SQMD MMU on: according to individual page PR 4.1.2 Register Configuration Table 4.4 shows the cache control registers. Table 4.4 Cache Control Registers Name Abbreviation R/W Initial Value*1 P4 Address*2 Area 7 Address*2 Access Size Cache control register CCR R/W H'0000 0000 H'FF00 001C H'1F00 001C 32 Queue address control register 0 QACR0 R/W Undefined H'FF00 0038 H'1F00 0038 32 Queue address control register 1 QACR1 R/W Undefined H'FF00 003C H'1F00 003C 32 Notes: 1. The initial value is the value after a power-on or manual reset. 2. P4 address is the address when using the virtual/physical address space P4 area. The area 7 address is the address used when making an access from physical address space area 7 using the TLB. Page 102 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 4.2 Section 4 Caches Register Descriptions There are three cache and store queue related control registers, as shown in figure 4.1. CCR 31 30 16 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0 CB EMODE* IIX ICI ICE OIX ORA OCI WT OCE QACR0 31 5 4 2 1 0 AREA QACR1 31 5 4 2 1 0 AREA Notes: indicates reserved bits: 0 must be specified in a write; the read value is 0. * SH7751R only Figure 4.1 Cache and Store Queue Control Registers (CCR) (1) Cache Control Register (CCR): CCR contains the following bits: EMODE: IIX: ICI: ICE: OIX: ORA: OCI: CB: WT: OCE: Cache-double-mode (SH7751R only. Reserved bit in SH7751.) IC index enable IC invalidation IC enable OC index enable OC RAM enable OC invalidation Copy-back enable Write-through enable OC enable CCR can be accessed by longword-size access from H'FF00001C in the P4 area and H'1F00001C in area 7. The CCR bits are used for the cache settings described below. Consequently, CCR modifications must only be made by a program in the non-cached P2 area. After CCR is updated, an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 103 of 1128 Section 4 Caches SH7751 Group, SH7751R Group four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or U0 area should be located at least eight instructions after the CCR update instruction. • EMODE: Cache-double-mode bit Indicates whether or not cache-double-mode is used in the SH7751R. This bit is reserved in the SH7751. The EMODE bit cannot be modified while the cache is in use. 0: SH7751-compatible-mode*1 (Initial value) 1: Cache-double-mode Note: 1. Address allocation in OC index mode and RAM mode is not compatible with that in RAM mode. • IIX: IC index enable bit 0: Effective address bits [12:5] used for IC entry selection 1: Effective address bits [25] and [11:5] used for IC entry selection • ICI: IC invalidation bit When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns 0 when read. • ICE: IC enable bit Indicates whether or not the IC is to be used. When address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1. 0: IC not used 1: IC used • OIX: OC index enable bit*2 0: Effective address bits [13:5] used for OC entry selection 1: Effective address bits [25] and [12:5] used for OC entry selection Note: 2. In the SH7751R, clear the OIX bit to 0 when the ORA bit is 1. • ORA: OC RAM enable bit*3 When the OC is enabled (OCE = 1), the ORA bit specifies whether the half of the OC are to be used as RAM. When the OC is not enabled (OCE = 0), the ORA bit should be cleared to 0. 0: Normal mode (the entire OC is used as a cache) 1: RAM mode (half of the OC is used as a cache and the other half is used as RAM) Note: 3. In the SH7751R, clear the ORA bit to 0 when the OIX bit is 1. Page 104 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches • OCI: OC invalidation bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always returns 0 when read. • CB: Copy-back bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode • WT: Write-through bit Indicates the P0, U0, and P3 area cache write mode. When address translation is performed, the value of the WT bit in the page management information has priority. 0: Copy-back mode 1: Write-through mode • OCE: OC enable bit Indicates whether or not the OC is to be used. When address translation is performed, the OC cannot be used unless the C bit in the page management information is also 1. 0: OC not used 1: OC used (2) Queue Address Control Register 0 (QACR0): QACR0 can be accessed by longword-size access from H'FF000038 in the P4 area and H'1F000038 in area 7. QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is off. (3) Queue Address Control Register 1 (QACR1): QACR1 can be accessed by longword-size access from H'FF00003C in the P4 area and H'1F00003C in area 7. QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is off. 4.3 Operand Cache (OC) 4.3.1 Configuration The operand cache in the SH7751 adopts the direct-mapping method, and consists of 512 cache lines. Each cache line is composed of a 19-bit tag, V bit, U bit, and 32-byte data. The operand cache in the SH7751R adopts the 2-way set-associative method, and each way consists of 512 cache lines. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 105 of 1128 Section 4 Caches SH7751 Group, SH7751R Group Figure 4.2 shows the configuration of the operand cache in the SH7751. Figure 4.3 shows the configuration of the operand cache in the SH7751R. Effective address 31 26 25 13 12 11 10 9 RAM area determination OIX [13] ORA [11:5] [12] Longword (LW) selection 22 Entry selection 9 MMU 5 4 3 2 1 0 Address array 0 Tag U Data array 3 V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 19 511 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Write data Read data Hit signal Figure 4.2 Configuration of Operand Cache (SH7751) Page 106 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches Effective address 31 26 25 13 12 10 5 4 RAM area determination [12:5] OIX ORA 2 0 Longword (LW) selection [13] Entry selection 22 Address array (way 0, way 1) 9 Tag 0 U 3 V Data array (way 0, way 1) LRU LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 MMU 19 511 19 bits Compare Compare way-0 way-1 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Read data 1 bit Write data Hit signal Figure 4.3 Configuration of Operand Cache (SH7751R) • Tag Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is not initialized by a power-on or manual reset. • V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 107 of 1128 Section 4 Caches SH7751 Group, SH7751R Group • U bit (dirty bit) The U bit is set to 1 if data is written to the cache line while the cache is being used in copyback mode. That is, the U bit indicates a mismatch between the data in the cache line and the data in external memory. The U bit is never set to 1 while the cache is being used in writethrough mode, unless it is modified by accessing the memory-mapped cache (see section 4.5, Memory-Mapped Cache Configuration (SH7751) and 4.6, Memory-Mapped Cache Configuration (SH7751R)). The U bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. • Data field The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU (SH7751R only) In a 2-way set-associative system, up to two entry addresses can register the same data in cache. The LRU bit indicates to which way the entry is to be registered among the two ways. There is one LRU bit in each entry, and it is controlled by hardware. The LRU (Last Recently Used) algorithm that selects the most recently accessed way is used for way selection. The LRU bit is initialized to 0 by a power-on reset, but is not initialized by a manual reset. The LRU bit cannot be read from or written to by software. 4.3.2 Read Operation When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: → (3a) • If the tag matches and the V bit is 1 → (3b) • If the tag matches and the V bit is 0 → (3b) • If the tag does not match and the V bit is 0 • If the tag does not match, the V bit is 1, and the U bit is 0 → (3b) • If the tag does not match, the V bit is 1, and the U bit is 1 → (3c) 3a. Cache hit The data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13:5] in accordance with the access size (quadword/longword/word/byte). Page 108 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches 3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. 3c. Cache miss (with write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are saved in the write-back buffer. Then data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, 1 is written to the V bit, and 0 to the U bit. The data in the write-back buffer is then written back to external memory. 4.3.3 Write Operation When the OC is enabled (CCR.OCE = 1) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: Copy-back Write-through → (3a) → (3b) • If the tag matches and the V bit is 1 → (3c) → (3d) • If the tag matches and the V bit is 0 → (3c) → (3d) • If the tag does not match and the V bit is 0 → (3d) • If the tag does not match, the V bit is 1, and the U bit is 0 → (3c) → (3d) • If the tag does not match, the V bit is 1, and the U bit is 1 → (3e) 3a. Cache hit (copy-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address and the data field of the cache line indexed by effective address bits [13:5]. Then 1 is set in the U bit. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 109 of 1128 Section 4 Caches SH7751 Group, SH7751R Group 3b. Cache hit (write-through) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data field of the cache line indexed by effective address bits [13:5] and for the data indexed by effective address bits [4:0]. A write is also performed to the corresponding external memory using the specified access size. 3c. Cache miss (copy-back/no write-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data field indexed by effective address bits [13:5] and for the data indexed by effective address bits [4:0]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. 3d. Cache miss (write-through) A write of the specified access size is performed to the external memory corresponding to the effective address. In this case, a write to cache is not performed. 3e. Cache miss (copy-back/with write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are first saved in the write-back buffer, and then a data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. The data in the write-back buffer is then written back to external memory. Page 110 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 4.3.4 Section 4 Caches Write-Back Buffer In order to give priority to data reads to the cache and improve performance, this LSI has a writeback buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination. Physical address bits [28:5] LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 Figure 4.4 Configuration of Write-Back Buffer 4.3.5 Write-Through Buffer This LSI has a 64-bit buffer for holding write data when writing data in write-through mode or writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as the write to the write-through buffer is completed, without waiting for completion of the write to external memory. Physical address bits [28:0] LW0 LW1 Figure 4.5 Configuration of Write-Through Buffer 4.3.6 RAM Mode Setting CCR.ORA to 1 enables 8 Kbytes of the operand cache to be used as RAM. The operand cache entries used as RAM are the 8 Kbytes of entries 128 to 255 and 384 to 511. In SH7751compatible-mode in the SH7751R, the 8 Kbytes of operand cache entries 256 to 511 are used as RAM. In cache-double-mode in the SH7751R, the total 16 Kbytes of entries 256 to 511 in each way of the operand cache are used as RAM. Other entries can still be used as cache. RAM can be accessed using addresses H'7C00 0000 to H'7FFF FFFF. Byte-, word-, longword-, and quadwordsize data reads and writes can be performed in the operand cache RAM area. Instruction fetches cannot be performed in this area. Note that in the SH7751R, OC index mode cannot be used when RAM mode is used. An example of RAM use is shown below. Here, the 4 Kbytes comprising OC entries 128 to 256 are designated as RAM area 1, and the 4 Kbytes comprising OC entries 384 to 511 as RAM area 2. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 111 of 1128 Section 4 Caches SH7751 Group, SH7751R Group • When OC index mode is off (CCR.OIX = 0) H'7C00 0000 to H'7C00 0FFF (4 KB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 KB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 KB): Corresponds to RAM area 2 H'7C00 3000 to H'7C00 3FFF (4 KB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 4FFF (4 KB): Corresponds to RAM area 1 : : : RAM areas 1 and 2 then repeat every 8 Kbytes up to H'7FFF FFFF. Thus, to secure a continuous 8-Kbyte RAM area, the area from H'7C00 1000 to H'7C00 2FFF can be used, for example. • When OC index mode is on (CCR.OIX = 1) H'7C00 0000 to H'7C00 0FFF (4 KB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 KB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 KB): Corresponds to RAM area 1 : : : H'7DFF F000 to H'7DFF FFFF (4 KB): Corresponds to RAM area 1 H'7E00 0000 to H'7E00 0FFF (4 KB): Corresponds to RAM area 2 H'7E00 1000 to H'7E00 1FFF (4 KB): Corresponds to RAM area 2 : : : H'7FFF F000 to H'7FFF FFFF (4 KB): Corresponds to RAM area 2 As the distinction between RAM areas 1 and 2 is indicated by address bit [25], the area from H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-Kbyte RAM area. An example of RAM use in the SH7751R is shown below. • SH7751-compatible-mode (CCR.EMODE = 0) H'7C00 0000 to H'7C00 1FFF (8 KB): Corresponds to RAM area (entries 256 to 511) H'7C00 2000 to H'7C00 3FFF (8 KB): Corresponds to RAM area (entries 256 to 511) : : : A shadow of the RAM area occurs every 8 Kbytes up to H'7FFF FFFF. • Cache-double-mode (CCR.EMODE = 1) The 8 Kbytes of entries 256 to 511 in OC way 0 are used as RAM area 1, and the 8 Kbytes of entries 256 to 511 in OC way 1 are used as RAM area 2. H'7C00 0000 to H'7C00 1FFF (8 KB): Corresponds to RAM area 1 Page 112 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches H'7C00 2000 to H'7C00 3FFF (8 KB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 5FFF (8 KB): Corresponds to RAM area 1 H'7C00 6000 to H'7C00 7FFF (8 KB): Corresponds to RAM area 2 : : : A shadow of the RAM area occurs every 16 Kbytes up to H'7FFF FFFF. 4.3.7 OC Index Mode Setting CCR.OIX to 1 enables OC indexing to be performed using bit [25] of the effective address. This is called OC index mode. In normal mode, with CCR.OIX cleared to 0, OC indexing is performed using bits [13:5] of the effective address. Using index mode allows the OC to be handled as two areas by means of effective address bit [25], providing efficient use of the cache. Note that in the SH7751R, RAM mode cannot be used when OC index mode is used. 4.3.8 Coherency between Cache and External Memory Coherency between cache and external memory should be assured by software. In this LSI, the following four new instructions are supported for cache operations. Details of these instructions are given in the Programming Manual. Invalidate instruction: OCBI @Rn Cache invalidation (no write-back) Purge instruction: OCBP @Rn Cache invalidation (with write-back) Write-back instruction: OCBWB @Rn Cache write-back Allocate instruction: MOVCA.L R0,@Rn Cache allocation 4.3.9 Prefetch Operation This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance. If a prefetch instruction is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or a protection violation, the result is no operation, and an exception is not generated. Details of the prefetch instruction are given in the Programming Manual. Prefetch instruction: R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 PREF @Rn Page 113 of 1128 Section 4 Caches 4.3.10 SH7751 Group, SH7751R Group Notes on Using OC RAM Mode (SH7751R Only) when in Cache Enhanced Mode When in cache enhanced mode (CCR.EMODE = 1) on the SH7751R, and the OC RAM mode, in which half of the operand cache is used as internal RAM, is selected (CCR.ORA = 1), data in RAM may be updated incorrectly. Conditions Under which Problem Occurs: Incorrect data may be written to RAM when the following four conditions are satisfied. Condition 1: Cache enhanced mode (CCR.EMODE = 1) is specified. Condition 2: The RAM mode (CCR.ORA = 1) in which half of the operand cache is used as RAM is specified. Condition 3: An exception or an interrupt occurs. Note: This includes a break triggered by a debugging tool swapping an instruction (a break occurring when a TRAPA instruction or undefined instruction code H'FFFD is swapped for an instruction). Condition 4: A store instruction (MOV, FMOV, AND.B, OR.B, XOR.B, MOVCA.L, STC.L, or STS.L) that accesses internal RAM (H'7C000000 to H'7FFFFFFF) exists within four words after the instruction associated with the exception or interrupt described in condition 3. This includes cases where the store instruction that accesses internal RAM itself generates an exception. Description: When the problem occurs, 8 bytes of incorrect data is written to the 8-byte boundary that includes an address that differs by H'2000 from the address accessed by the store instruction that accesses internal RAM mentioned in condition 4. For example, when a long word is stored at address H'7C000204, the 8 bytes of data in the internal RAM mapped to addresses H'7C002200 to H'7C002207 becomes corrupted. Page 114 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches Examples Example 1 A store instruction accessing internal RAM occurs within four instructions after an instruction generating a TLB miss exception. MOV.L #H'0C400000, R0 R0 is an address causing a TLB miss. MOV.L #H'7C000204, R1 R1 is an address mapped to internal RAM. MOV.L @R0, R2 TLB miss exception occurs. NOP 1st word NOP 2nd word NOP 3rd word MOV.L R3, @R1 Store instruction accessing internal RAM Example 2 A store instruction accessing internal RAM occurs within four instructions after an instruction causing an interrupt to be accepted. MOV.L #H'7C002000, R1 R1 is an address mapped to internal RAM. MOV.L #H'12345678, R0 An interrupt is accepted after this instruction. NOP 1st word NOP 2nd word NOP 3rd word MOV.L R0, @R1 Store instruction accessing internal RAM Example 3 A debugging tool generates a break to swap an instruction. Original Instruction String After Instruction Swap Break MOV.L #H'7C000000, R0 MOV.L #H'7C000000, R0 Contains address corresponding to R0. ADD R0, R0 TRAPA #H'01 R0 address is not a problem in original instruction string. MOV.L R1, @R0 MOV.L R1, @R0 Internal RAM is accessed by a store operation because ADD is not executed. The store is cancelled, but 2LW starting at H'7C002000 is corrupted. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 115 of 1128 Section 4 Caches SH7751 Group, SH7751R Group Workarounds: When RAM mode is specified in cache enhanced mode, either of the following workarounds can be used to avoid the problem. Workaround 1: Use only 8 Kbytes of the 16-Kbyte internal RAM area. In this case, RAM areas for which address bits [12:0] are identical and only bit [13] differs must not be used. For example, the 8-Kbyte RAM area from H'7C000000 to H'7C001FFF or from H'7C001000 to H'7C002FFF may be used. Note: When a break is used to swap instructions by a debugging tool, etc., a memory access address may be changed when an instruction following the instruction generating the break is swapped for another instruction, causing the unused 8-Kbyte RAM area to be accessed. This will result in the problem described above. However, this phenomenon only occurs during debugging when a break is used to swap instructions. Using a break with no instruction swapping will not cause the problem. Workaround 2: Ensure that there are no instructions that generate an interrupt or exception within four instructions after an instruction that accesses internal RAM. For example, the internal RAM area can be used as a data table that is accessed only by load instructions, with writes to the internal RAM area only being performed when the table is generated. In this case, set SR.BL to 1 to disable interrupts while writing to the table. Also take measures to ensure that no exceptions due to TLB misses, etc., occur while writing to the table. Note: The problem still may occur when a break is used to swap instructions by a debugging tool. This phenomenon only occurs during debugging when a break is used to swap instructions. Using a break with no instruction swapping will not cause the problem. 4.4 Instruction Cache (IC) 4.4.1 Configuration The instruction cache consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32byte data (16 instructions). The instruction cache in the SH7751R adopts the 2-way set-associative method, and each way consists of 256 cache lines. Page 116 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches Figure 4.6 shows the configuration of the instruction cache in the SH7751. Figure 4.7 shows the configuration of the instruction cache in the SH7751R. Effective address 31 26 25 13 12 11 10 9 5 4 3 2 1 0 [11:5] IIX [12] Longword (LW) selection 22 MMU Entry selection 8 Address array 0 3 Data array Tag V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 19 255 Compare Read data Hit signal Figure 4.6 Configuration of Instruction Cache (SH7751) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 117 of 1128 Section 4 Caches SH7751 Group, SH7751R Group Effective address 31 25 13 12 11 10 5 4 [11:5] 2 0 Longword (LW) selection IIX [12] Entry selection 22 Address array (way 0, way 1) 8 0 3 Data array (way 0, way 1) LRU Tag V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits MMU 19 255 Compare Compare way-0 way-1 1 bit Read data Hit signal Figure 4.7 Configuration of Instruction Cache (SH7751R) • Tag Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is not initialized by a power-on or manual reset. • V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. Page 118 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU (SH7751R only) In a 2-way set-associative system, up to two entry addresses can register the same data in cache. The LRU bit indicates to which way the entry is to be registered among the two ways. There is one LRU bit in each entry, and it is controlled by hardware. The LRU (Last Recently Used) algorithm that selects the most recently accessed way is used for way selection. The LRU bit is initialized to 0 by a power-on reset, but is not initialized by a manual reset. The LRU bit cannot be read from or written to by software. 4.4.2 Read Operation When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an effective address from a cacheable area, the instruction cache operates as follows: 1. The tag and V bit are read from the cache line indexed by effective address bits [12:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: • If the tag matches and the V bit is 1 → (3a) • If the tag matches and the V bit is 0 → (3b) • If the tag does not match and the V bit is 0 → (3b) • If the tag does not match and the V bit is 1 → (3b) 3a. Cache hit The data indexed by effective address bits [4:2] is read as an instruction from the data field of the cache line indexed by effective address bits [12:5]. 3b. Cache miss Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU as an instruction. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 119 of 1128 Section 4 Caches 4.4.3 SH7751 Group, SH7751R Group IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled as two areas by means of effective address bit [25], providing efficient use of the cache. 4.5 Memory-Mapped Cache Configuration (SH7751) To enable the IC and OC to be managed by software, the IC contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be made at least 8 instructions after this MOV instruction. The OC contents can be read and written by a P1 or P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, or P3 area should be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4 area in physical memory space. Only data accesses can be used on both the IC address array and data array and the OC address array and data array, and the access size is always longword. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified, and read values are undefined. 4.5.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: Page 120 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine. 24 23 31 Address field 1 1 1 1 0 0 0 0 13 12 5 4 3 2 1 0 Entry 10 9 31 Data field Tag A 1 0 V Legend: V: Validity bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.8 Memory-Mapped IC Address Array R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 121 of 1128 Section 4 Caches 4.5.2 SH7751 Group, SH7751R Group IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 0 0 1 13 12 5 4 Entry 31 Data field 2 1 0 L 0 Longword data Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.9 Memory-Mapped IC Data Array Page 122 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 4.5.3 Section 4 Caches OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit is 1, the U bit and V bit specified in the data field are written into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If a UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 123 of 1128 Section 4 Caches SH7751 Group, SH7751R Group not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. 31 24 23 Address field 1 1 1 1 0 1 0 0 14 13 5 4 3 2 1 0 Entry 31 10 9 Data field A 2 1 0 U V Tag Legend: V: Validity bit U: Dirty bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.10 Memory-Mapped OC Address Array 4.5.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding the entry set in the address field. This write does not set the U bit to 1 on the address array side. Page 124 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches 31 24 23 Address field 1 1 1 1 0 1 0 1 14 13 5 4 Entry 31 2 1 0 L 0 Data field Longword data Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.11 Memory-Mapped OC Data Array 4.6 Memory-Mapped Cache Configuration (SH7751R) To enable the IC and OC to be managed by software, IC contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be made at least 8 instructions after this MOV instruction. The OC contents can be read and written by a P1 or P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, or P3 area should be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4 area in physical memory space. Only data accesses can be used on both the IC address array and data array and the OC address array and data array, and the access size is always longword. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified, and read values are undefined. Note that the memory-mapped cache configuration in SH7751-compatible-mode of the SH7751R is the same as that in the SH7751. 4.6.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is specified by bit [13], and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bit [3], that is the association bit (A bit), specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 125 of 1128 Section 4 Caches SH7751 Group, SH7751R Group In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the way and entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the way and entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, each way's tag stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set in bit [13] is ignored. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit in that way is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine. 24 23 31 Address field 1 1 1 1 0 0 0 0 13 12 Way 31 Data field 5 4 3 2 1 0 Entry 10 9 A 1 0 V Tag Legend: V: Validity bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.12 Memory-Mapped IC Address Array Page 126 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 4.6.2 Section 4 Caches IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, the way is specified by bit [13], and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. 31 24 23 13 12 Address field 1 1 1 1 0 0 0 1 5 4 Entry 2 1 0 L Way 31 0 Data field Longword data Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.13 Memory-Mapped IC Data Array R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 127 of 1128 Section 4 Caches 4.6.3 SH7751 Group, SH7751R Group OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, the way is specified by bit [14], and the entry is specified by bits [13:5]. CCR.OIX has no effect on this entry specification. The OC address array access in RAM mode (CCR.ORA = 1) is performed only to cache, and bit [13] specifies the way. For details on address allocation, see section 4.6.5, Summary of Memory-Mapped OC Addresses. Address field bit [3], that is the association bit (A bit), specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the way and entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the way and entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, each way's tag stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set in bit [14] is ignored. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit in that way is 1, the U bit and V bit specified in the data field are written into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If a UTLB miss Page 128 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. 31 24 23 15 1413 Address field 1 1 1 1 0 1 0 0 5 4 3 2 1 0 Entry A Way 31 10 9 Data field Tag 2 1 0 U V Legend: V: Validity bit U: Dirty bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.14 Memory-Mapped OC Address Array 4.6.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is specified by bit [14], and the entry is specified by bits [13:5]. CCR.OIX has no effect on this entry specification. The OC address array access in RAM mode (CCR.ORA = 1) is performed only to cache, and bit [13] specifies the way. For details on address allocation, see section 4.6.5, Summary of Memory-Mapped OC Addresses. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 129 of 1128 Section 4 Caches SH7751 Group, SH7751R Group 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. This write does not set the U bit to 1 on the address array side. 31 24 23 15 1413 Address field 1 1 1 1 0 1 0 1 5 4 Entry 2 1 0 L Way 31 Data field 0 Longword data Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.15 Memory-Mapped OC Data Array 4.6.5 Summary of Memory-Mapped OC Addresses The memory-mapped OC addresses in cache-double-mode in the SH7751R are summarized below using data area access as an example. • Normal mode (CCR.ORA = 0) H'F500 0000 to H'F500 3FFF (16 KB): Way 0 (entries 0 to 511) H'F500 4000 to H'F500 7FFF (16 KB): Way 1 (entries 0 to 511) : : : A shadow of the cache area occurs every 32 Kbytes up to H'F5FF FFFF. • RAM mode (CCR.ORA = 1) H'F500 0000 to H'F500 1FFF (8 KB): Way 0 (entries 0 to 255) H'F500 2000 to H'F500 3FFF (8 KB): Way 1 (entries 0 to 255) : : : A shadow of the cache area occurs every 16 Kbytes up to H'F5FF FFFF. Page 130 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 4.7 Section 4 Caches Store Queues Two 32-byte store queues (SQs) are supported to perform high-speed writes to external memory. When not using the SQs, the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped. See section 9, Power-Down Modes, for the procedure for stopping SQ functions. Note that power-down modes (STBCR2.MSTP6 = 1) that stop SQ functions cannot be used on the SH7751 when using the operand cache for write-back operations.* Note: * Cases where write-back operations are performed: • When the operand cache is used in copy-back mode (determined by the CCR.CB and CCR.WT bits and, if address translation is performed, the WT bit in the page management information) • When the memory allocation cache function is used to write to the OC address array, and an entry is generated when both the V and U bits are set to 1 4.7.1 SQ Configuration There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store queues can be set independently. SQ0 SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7] SQ1 SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7] 4B 4B 4B 4B 4B 4B 4B 4B Figure 4.16 Store Queue Configuration 4.7.2 SQ Writes A write to the SQs can be performed using a store instruction on P4 area H'E000 0000 to H'E3FF FFFC. A longword or quadword access size can be used. The meaning of the address bits is as follows: [31:26]: [25:6]: [5]: 111000 Don't care 0/1 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Store queue specification Used for external memory transfer/access right 0: SQ0 specification 1: SQ1 specification Page 131 of 1128 Section 4 Caches [4:2]: [1:0] 4.7.3 LW specification 00 SH7751 Group, SH7751R Group Specifies longword position in SQ0/SQ1 Fixed at 0 Transfer to External Memory Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is always at a 32-byte boundary. While the contents of one SQ are being transferred to external memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in the transfer to external memory is deferred until the transfer is completed. The SQ transfer destination external address bit [28:0] specification is as shown below, according to whether the MMU is on or off. • When MMU is on The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer destination external address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same meaning as for normal address translation, but the C and WT bits have no meaning with regard to this page. Since burst transfer is prohibited for PCMCIA areas, the SA and TC bits also have no meaning. When a prefetch instruction is issued for the SQ area, address translation is performed and external address bits [28:10] are generated in accordance with the SZ bit specification. For external address bits [9:5], the address prior to address translation is generated in the same way as when the MMU is off. External address bits [4:0] are fixed at 0. Transfer from the SQs to external is performed to this address. • When MMU is off The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address at which a PREF instruction is issued. The meaning of address bits [31:0] is as follows: [31:26]: [25:6]: [5]: 111000 Address 0/1 [4:2]: [1:0] Don't care 00 Store queue specification External address bits [25:6] 0: SQ0 specification 1: SQ1 specification and external address bit [5] No meaning in a prefetch Fixed at 0 External address bits [28:26], which cannot be generated from the above address, are generated from the QACR0/1 registers. Page 132 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group QACR0 [4:2]: QACR1 [4:2]: Section 4 Caches External address bits [28:26] corresponding to SQ0 External address bits [28:26] corresponding to SQ1 External address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. In this LSI, data transfer to a PCMCIA interface area is always performed using the SA and TC bits in the PTEA register. 4.7.4 Determination of SQ Access Exception Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows. If an exception occurs in an SQ write, the SQ contents may be corrupted in the SH7751 (see section 4.7.6, SQ Usage Notes), but the previous values of the SQ contents are guaranteed in the SH7751R. If an exception occurs in transfer from an SQ to external memory, the transfer to external memory will be aborted. • When MMU is on Operation is in accordance with the address translation information recorded in the UTLB, and MMUCR.SQMD. Write type exception judgment is performed for writes to the SQs, and read type for transfer from the SQs to external memory (PREF instruction), and a TLB miss exception, protection violation exception, or initial page write exception is generated. However, if SQ access is enabled, in privileged mode only, by MMUCR.SQMD, an address error will be flagged in user mode even if address translation is successful. • When MMU is off Operation is in accordance with MMUCR.SQMD. 0: Privileged/user access possible 1: Privileged access possible If the SQ area is accessed in user mode when MMUCR.SQMD is set to 1, an address error will be flagged. 4.7.5 SQ Read (SH7751R only) In the SH7751R, the SQ contents can be read by a load instruction for addresses H'FF001000 to H'FF00103C in the P4 area in privileged mode. The access size is always longword. [31:6]: [5]: [4:2]: [1:0]: H'FF001000 (store queue specification) 0/1 (0: SQ0 specification, 1: SQ1 specification) LW specification (specification of longword position in SQ0 or SQ1) 00 (fixed to 0) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 133 of 1128 Section 4 Caches 4.7.6 SH7751 Group, SH7751R Group SQ Usage Notes (SH7751 Only) If an exception occurs within the three instructions preceding an instruction that writes to an SQ in the SH7751, a branch may be made to the exception handling routine after execution of the SQ write that should be suppressed when an exception occurs. This may be due to the bug described in (1) or (2) below. (1) When SQ data is transferred to external memory within a normal program If a PREF instruction for transfer from an SQ to external memory is included in the three instructions preceding an SQ store instruction, the SQ is updated because the SQ write that should be suppressed when a branch is made to the exception handling routine is executed, and after returning from the exception handling routine the execution order of the PREF instruction and SQ store instruction is reversed, so that erroneous data may be transferred to external memory. (2) When SQ data is transferred to external memory in an exception handling routine If store queue contents are transferred to external memory within an exception handling routine, erroneous data may be transferred to external memory. Example 1: When an SQ store instruction is executed after a PREF instruction for transfer from that same SQ to external memory PREF instruction ; PREF instruction for transfer from SQ to external memory ; Address of this instruction is saved to SPC when exception occurs. ; Instruction 1, instruction 2, or instruction 3 may be executed on return from exception handling ; routine. Instruction 1 ; May be executed if an SQ store instruction. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ; May be executed if an SQ store instruction. Instruction 4 ; Not executed even if an SQ store instruction. Page 134 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 4 Caches Example 2: When an instruction at which an exception occurs is a branch instruction and a branch is made Instruction 1 (branch instruction); Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an instruction 1 delay slot instruction and an SQ store instruction. Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7 (instruction 1 branch destination) ; May be executed if an SQ store instruction. Instruction 8 ; May be executed if an SQ store instruction. Example 3: When an instruction at which an exception occurs is a branch instruction but a branch is not made Instruction 1 (branch instruction); Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ; May be executed if an SQ store instruction. Instruction 4 ; May be executed if an SQ store instruction. Instruction 5 Both A and B below must be satisfied in order to prevent this bug. A: When a store queue store instruction is executed after a PREF instruction for transfer from that same store queue (SQ0, SQ1) to external memory, (1) and (2) below must be satisfied. (1) Insert three NOP instructions*1 between the two instructions. (2) Do not place a PREF instruction for transfer from a store queue to external memory in the delay slot of a branch instruction. B: Do not execute a PREF instruction for transfer from a store queue to external memory within an exception handling routine. If the above is executed and there is a store queue store instruction among the four instructions*2 including the instruction at the address indicated by the SPC, the state of the contents transferred to external memory by the PREF instruction may be that when execution of this store instruction is completed. Notes: 1. If there are other instructions between the two instructions, this bug can be prevented if the total number of other instructions plus NOP instructions is at least three. 2. If the instruction at the address indicated by the SPC is a branch instruction, this also applies to two instructions at the branch destination. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 135 of 1128 Section 4 Caches Page 136 of 1128 SH7751 Group, SH7751R Group R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 5 Exceptions Section 5 Exceptions 5.1 Overview 5.1.1 Features Exception handling is processing handled by a special routine, separate from normal program processing, that is executed by the CPU in case of abnormal events. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing. The process of generating an exception handling request in response to abnormal termination, and passing control flow to an exception handling routine, etc., is given the generic name of exception handling. SH-4 exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1. Table 5.1 Exception-Related Registers Abbreviation R/W Initial Value P4 Address*2 TRAPA exception register TRA R/W Undefined H'FF00 0020 H'1F00 0020 32 Exception event register EXPEVT R/W H'0000 0000/ H'0000 0020*1 H'FF00 0024 H'1F00 0024 32 Interrupt event register INTEVT R/W Undefined H'FF00 0028 H'1F00 0028 32 Name Area 7 Address*2 Access Size Notes: 1. H'0000 0000 is set in a power-on reset, and H'0000 0020 in a manual reset. 2. P4 address is the address when using the virtual/physical address space P4 area. When making an access from area 7 in the physical address space using the TLB, the three high most bits of the address are ignored. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 137 of 1128 Section 5 Exceptions 5.2 SH7751 Group, SH7751R Group Register Descriptions There are three registers related to exception handling. Addresses are allocated for these, and can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception is accepted. EXPEVT can also be modified by software. 2. The interrupt event register (INTEVT) resides at P4 address H'FF00 0028, and contains a 14bit exception code. The exception code set in INTEVT is that for an interrupt request. The exception code is set automatically by hardware when an exception is accepted. INTEVT can also be modified by software. 3. The TRAPA exception register (TRA) resides at P4 address H'FF00 0020, and contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. The bit configurations of EXPEVT, INTEVT, and TRA are shown in figure 5.1. EXPEVT 31 12 11 0 0 Exception code 0 INTEVT 31 0 14 13 0 Exception code 0 TRA 31 0 10 9 0 2 1 0 imm 0 0 Legend: 0: Reserved bits. These bits are always read as 0, and should only be written with 0. imm: 8-bit immediate data of the TRAPA instruction Figure 5.1 Register Bit Configurations Page 138 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 5.3 Exception Handling Functions 5.3.1 Exception Handling Flow Section 5 Exceptions In exception handling, the contents of the program counter (PC), status register (SR) and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register 15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address. An exception handling routine is a program written by the user to handle a specific exception. The exception handling routine is terminated and control returned to the original program by executing a return-from-exception instruction (RTE). This instruction restores the PC and SR contents and returns control to the normal processing routine at the point at which the exception occurred. The SGR contents are not written back to R15 by an RTE instruction. The basic processing flow is as follows. See section 2, Programming Model, for the meaning of the individual SR bits. 1. 2. 3. 4. 5. 6. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR. The block bit (BL) in SR is set to 1. The mode bit (MD) in SR is set to 1. The register bank bit (RB) in SR is set to 1. In a reset, the FPU disable bit (FD) in SR is cleared to 0. The exception code is written to bits 11–0 of the exception event register (EXPEVT) or to bits 13–0 of the interrupt event register (INTEVT). 7. The CPU branches to the determined exception handling vector address, and the exception handling routine begins. 5.3.2 Exception Handling Vector Addresses The reset vector address is fixed at H'A000 0000. General exception and interrupt vector addresses are determined by adding the offset for the specific event to the vector base address, which is set by software in the vector base register (VBR). In the case of the TLB miss exception, for example, the offset is H'0000 0400, so if H'9C08 0000 is set in VBR, the exception handling vector address will be H'9C08 0400. If a further exception occurs at the exception handling vector address, a duplicate exception will result, and recovery will be difficult; therefore, fixed physical addresses (P1, P2) should be specified for vector addresses. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 139 of 1128 Section 5 Exceptions 5.4 SH7751 Group, SH7751R Group Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Category Mode Exception Priority Priority Vector Level Order Address Offset Exception Code Reset Power-on reset 1 1 H'A000 0000 — H'000 Manual reset 1 2 H'A000 0000 — H'020 H-UDI reset 1 1 H'A000 0000 — H'000 Instruction TLB multiple-hit exception 1 3 H'A000 0000 — H'140 H'140 General exception Abort type Reexecution type Data TLB multiple-hit exception 1 4 H'A000 0000 — User break before instruction 1 execution* 2 0 (VBR/DBR) H'100/— H'1E0 Instruction address error 2 1 (VBR) H'100 H'0E0 Instruction TLB miss exception 2 2 (VBR) H'400 H'040 Instruction TLB protection violation exception 2 3 (VBR) H'100 H'0A0 General illegal instruction exception 2 4 (VBR) H'100 H'180 Slot illegal instruction exception 2 4 (VBR) H'100 H'1A0 General FPU disable exception 2 4 (VBR) H'100 H'800 Slot FPU disable exception 2 4 (VBR) H'100 H'820 Data address error (read) 2 5 (VBR) H'100 H'0E0 Data address error (write) 2 5 (VBR) H'100 H'100 Data TLB miss exception (read) 2 6 (VBR) H'400 H'040 Data TLB miss exception (write) 2 6 (VBR) H'400 H'060 Data TLB protection violation exception (read) 2 7 (VBR) H'100 H'0A0 Data TLB protection violation exception (write) 2 7 (VBR) H'100 H'0C0 FPU exception 2 8 (VBR) H'100 H'120 Initial page write exception 2 9 (VBR) H'100 H'080 2 4 (VBR) H'100 H'160 2 10 (VBR/DBR) H'100/— H'1E0 Completion Unconditional trap (TRAPA) type User break after instruction 1 execution* Page 140 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 5 Exceptions Exception Category Execution Mode Exception Priority Level Priority Vector Order Address Offset Exception Code Interrupt Completion Nonmaskable interrupt type External IRL3–IRL0 interrupts 3 — (VBR) H'600 H'1C0 4 *2 (VBR) H'600 H'200 0 1 H'220 2 H'240 3 H'260 4 H'280 5 H'2A0 6 H'2C0 7 H'2E0 8 H'300 9 H'320 A H'340 B H'360 C H'380 D H'3A0 E Peripheral TMU0 module TMU1 interrupt (module/ TMU2 source) TUNI0 Sep 24, 2013 *2 (VBR) H'600 H'400 TUNI1 H'420 TUNI2 H'440 TICPI2 H'460 TMU3 TUNI3 H'B00 TMU4 TUNI4 H'B80 RTC ATI H'480 SCI R01UH0457EJ0301 Rev. 3.01 H'3C0 4 PRI H'4A0 CUI H'4C0 ERI H'4E0 RXI H'500 TXI H'520 TEI H'540 WDT ITI H'560 REF RCMI H'580 ROVI H'5A0 Page 141 of 1128 Section 5 Exceptions SH7751 Group, SH7751R Group Exception Category Execution Mode Exception Interrupt Completion Peripheral H-UDI type module GPIO interrupt (module/ DMAC source) H-UDI PCIC Offset Exception Code 4 H'600 H'600 *2 (VBR) GPIOI H'620 DMTE0 H'640 DMTE1 H'660 DMTE2 H'680 DMTE3 SCIF Priority Priority Vector Level Order Address H'6A0 DMTE4* 3 H'780 DMTE5* 3 H'7A0 DMTE6* 3 H'7C0 DMTE7* 3 H'7E0 DMAE H'6C0 ERI H'700 RXI H'720 BRI H'740 TXI H'760 PCISERR H'A00 PCIERR H'AE0 PCIPWDWN H'AC0 PCIPWON H'AA0 PCIDMA0 H'A80 PCIDMA1 H'A60 PCIDMA2 H'A40 PCIDMA3 H'A20 Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest number represents the highest priority). Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases. Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt. IRL: Interrupt request level (pins IRL3–IRL0). Module/source: See the sections on the relevant peripheral modules. Notes: 1. When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100. 2. The priority order of external interrupts and peripheral module interrupts can be set by software. 3. SH7751R only Page 142 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 5.5 Exception Flow 5.5.1 Exception Flow Section 5 Exceptions Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different kinds of exceptions (reset/general exception/interrupt). Register settings in the event of an exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers may be set automatically by hardware, depending on the exception. For details, see section 5.6, Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, and in the case of instructions in which two data accesses are performed. Yes Reset requested? No Execute next instruction General exception requested? Yes No Interrupt requested? No Is highestYes priority exception re-exception type? Cancel instruction execution No result Yes SSR ← SR SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.{MD,RB,BL} ← 111 PC ← (BRCR.UBDE=1 && User_Break? DBR: (VBR + Offset)) EXPEVT ← exception code SR. {MD, RB, BL, FD, IMASK} ← 11101111 PC ← H'A000 0000 Figure 5.2 Instruction Execution and Exception Handling R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 143 of 1128 Section 5 Exceptions 5.5.2 SH7751 Group, SH7751R Group Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—the general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These exceptions therefore all have the same priority. General exceptions are detected in the order of instruction execution. However, exception handling is performed in the order of instruction flow (program order). Thus, an exception for an earlier instruction is accepted before that for a later instruction. An example of the order of acceptance for general exceptions is shown in figure 5.3. Page 144 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 5 Exceptions Pipeline flow: Instruction n Instruction n+1 IF ID EX TLB miss (data access) MA WB IF ID EX MA WB General illegal instruction exception Instruction n+2 TLB miss (instruction access) IF ID EX MA WB Instruction n+3 IF ID EX MA Order of detection: WB Legend: IF: Instruction fetch ID: Instruction decode EX: Instruction execution MA: Memory access WB: Write-back General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling: Program order TLB miss (instruction n) 1 Re-execution of instruction n General illegal instruction exception (instruction n+1) 2 Re-execution of instruction n+1 TLB miss (instruction n+2) 3 Re-execution of instruction n+2 Execution of instruction n+3 4 Figure 5.3 Example of General Exception Acceptance Order R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 145 of 1128 Section 5 Exceptions 5.5.3 SH7751 Group, SH7751R Group Exception Requests and BL Bit When the BL bit in SR is 0, general exceptions and interrupts are accepted. When the BL bit in SR is 1 and a general exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their post-reset state, and the CPU branches to the same address as in a reset (H'A000 0000). For the operation in the event of a user break, see section 20, User Break Controller (UBC). If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable multiple exception state acceptance. 5.5.4 Return from Exception Handling The RTE instruction is used to return from exception handling. When the RTE instruction is executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns from the exception handling routine by branching to the SPC address. If SPC and SSR were saved to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and issuing the RTE instruction. 5.6 Description of Exceptions The various exception handling operations are described here, covering exception sources, transition addresses, and processor operation when a transition is made. Page 146 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 5.6.1 Section 5 Exceptions Resets (1) Power-On Reset • Sources: ⎯ RESET pin low level ⎯ When the watchdog timer overflows while the WT/IT bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. For some CPU functions, the TRST pin and RESET pin must be driven low. It is therefore essential to execute a power-on reset and drive the TRST pin low when powering on. If the RESET pin is driven high before the MRESET pin while both these pins are low, a manual reset may occur after the power-on reset operation. The RESET pin must be driven high at the same time as, or after, the MRESET pin. Power_on_reset() { EXPEVT = H'00000000; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD=0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A0000000; } R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 147 of 1128 Section 5 Exceptions SH7751 Group, SH7751R Group (2) Manual Reset • Sources: ⎯ MRESET pin low level and RESET pin high level ⎯ When a general exception other than a user break occurs while the BL bit is set to 1 in SR ⎯ When the watchdog timer overflows while the RSTS bit is set to 1 in WTCSR. For details, see section 10, Clock Oscillation Circuits. • Transition address: H'A000 0000 • Transition operations: Exception code H'020 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. Manual_reset() { EXPEVT = H'00000020; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Table 5.3 Types of Reset Reset State Transition Conditions Internal States Type MRESET RESET CPU On-Chip Peripheral Modules Power-on reset — Low Initialized Manual reset Low High Initialized See Register Configuration in each section Page 148 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 5 Exceptions (3) H-UDI Reset • Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. H-UDI_reset() { EXPEVT = H'00000000; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A0000000; } R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 149 of 1128 Section 5 Exceptions SH7751 Group, SH7751R Group (4) Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'00000140; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Page 150 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 5 Exceptions (5) Data TLB Multiple-Hit Exception • Source: Multiple UTLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'00000140; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 151 of 1128 Section 5 Exceptions 5.6.2 SH7751 Group, SH7751R Group General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'040 (for a read access) or H'060 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions. Data_TLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'00000040 : H'00000060; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000400; } Page 152 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 5 Exceptions (2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'040 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions. ITLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000040; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000400; } R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 153 of 1128 Section 5 Exceptions SH7751 Group, SH7751R Group (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'080 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Initial_write_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000080; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Page 154 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 5 Exceptions (4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. PR Privileged Mode User Mode 00 Only read access possible Access not possible 01 Read/write access possible Access not possible 10 Only read access possible Only read access possible 11 Read/write access possible Read/write access possible • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Data_TLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'000000A0 : H'000000C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 155 of 1128 Section 5 Exceptions SH7751 Group, SH7751R Group (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. PR Privileged Mode User Mode 0 Access possible Access not possible 1 Access possible Access possible • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'000000A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Page 156 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 5 Exceptions (6) Data Address Error • Sources: ⎯ Word data access from other than a word boundary (2n +1) ⎯ Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) ⎯ Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) ⎯ Access to area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit (MMU). Data_address_error() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access? H'000000E0: H'00000100; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 157 of 1128 Section 5 Exceptions SH7751 Group, SH7751R Group (7) Instruction Address Error • Sources: ⎯ Instruction fetch from other than a word boundary (2n +1) ⎯ Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in the SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit (MMU). Instruction_address_error() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'000000E0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Page 158 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 5 Exceptions (8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'0000 0100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. TRAPA_exception() { SPC = PC + 2; SSR = SR; SGR = R15; TRA = imm Rm (unsigned), 1→T Otherwise, 0 → T 0011nnnnmmmm0110 — Comparison result CMP/GT Rm,Rn When Rn > Rm (signed), 1 → T 0011nnnnmmmm0111 — Otherwise, 0 → T Comparison result CMP/PZ Rn When Rn ≥ 0, 1 → T Otherwise, 0 → T 0100nnnn00010001 — Comparison result CMP/PL Rn When Rn > 0, 1 → T Otherwise, 0 → T 0100nnnn00010101 — Comparison result CMP/STR Rm,Rn When any bytes are equal, 1→T Otherwise, 0 → T 0010nnnnmmmm1100 — Comparison result DIV1 Rm,Rn 1-step division (Rn ÷ Rm) 0011nnnnmmmm0100 — Calculation result DIV0S Rm,Rn MSB of Rn → Q, MSB of Rm → M, M^Q → T 0010nnnnmmmm0111 — Calculation result 0 → M/Q/T 0000000000011001 — 0 Signed, Rn × Rm → MAC, 32 × 32 → 64 bits 0011nnnnmmmm1101 — — DMULU.L Rm,Rn Unsigned, Rn × Rm → MAC, 32 × 32 → 64 bits 0011nnnnmmmm0101 — — DT Rn Rn – 1 → Rn; when Rn = 0, 1→T When Rn ≠ 0, 0 → T 0100nnnn00010000 — Comparison result EXTS.B Rm,Rn Rm sign-extended from byte → Rn 0110nnnnmmmm1110 — — DIV0U DMULS.L Rm,Rn Page 198 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Instruction Section 7 Instruction Set Operation Instruction Code Privileged T Bit EXTS.W Rm,Rn Rm sign-extended from word → Rn 0110nnnnmmmm1111 — — EXTU.B Rm,Rn Rm zero-extended from byte → Rn 0110nnnnmmmm1100 — — EXTU.W Rm,Rn Rm zero-extended from word → Rn 0110nnnnmmmm1101 — — MAC.L @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 4 → Rn, Rm + 4 → Rm 32 × 32 + 64 → 64 bits 0000nnnnmmmm1111 — — MAC.W @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 2 → Rn, Rm + 2 → Rm 16 × 16 + 64 → 64 bits 0100nnnnmmmm1111 — — MUL.L Rm,Rn Rn × Rm → MACL 32 × 32 → 32 bits 0000nnnnmmmm0111 — — MULS.W Rm,Rn Signed, Rn × Rm → MACL 16 × 16 → 32 bits 0010nnnnmmmm1111 — — MULU.W Rm,Rn Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 0010nnnnmmmm1110 — — NEG Rm,Rn 0 – Rm → Rn 0110nnnnmmmm1011 — — NEGC Rm,Rn 0 – Rm – T → Rn, borrow → T 0110nnnnmmmm1010 — Borrow SUB Rm,Rn Rn – Rm → Rn 0011nnnnmmmm1000 — — SUBC Rm,Rn Rn – Rm – T → Rn, borrow → T 0011nnnnmmmm1010 — Borrow SUBV Rm,Rn Rn – Rm → Rn, underflow → T 0011nnnnmmmm1011 — Underflow R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 199 of 1128 Section 7 Instruction Set Table 7.5 SH7751 Group, SH7751R Group Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 — — AND #imm,R0 R0 & imm → R0 AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + GBR) 11001001iiiiiiii — — 11001101iiiiiiii — — NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 — — OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 — — OR #imm,R0 R0 | imm → R0 — OR.B #imm,@(R0,GBR) (R0 + GBR) | imm → (R0 + GBR) TAS.B 11001011iiiiiiii — 11001111iiiiiiii — @Rn When (Rn) = 0, 1 → T 0100nnnn00011011 Otherwise, 0 → T In both cases, 1 → MSB of (Rn) — Test result TST Rm,Rn Rn & Rm; when result = 0, 1→T Otherwise, 0 → T 0010nnnnmmmm1000 — Test result TST #imm,R0 R0 & imm; when result = 0, 1→T Otherwise, 0 → T 11001000iiiiiiii — Test result TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; when result 11001100iiiiiiii = 0, 1 → T Otherwise, 0 → T — Test result XOR Rm,Rn Rn ∧ Rm → Rn 0010nnnnmmmm1010 — — XOR #imm,R0 R0 ∧ imm → R0 11001010iiiiiiii — — 11001110iiiiiiii — — XOR.B #imm,@(R0,GBR) (R0 + GBR) ∧ imm → (R0 + GBR) Page 200 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Table 7.6 Section 7 Instruction Set Shift Instructions Instruction Operation Instruction Code Privileged T Bit ROTL Rn T ← Rn ← MSB 0100nnnn00000100 — MSB ROTR Rn LSB → Rn → T 0100nnnn00000101 — LSB ROTCL Rn T ← Rn ← T 0100nnnn00100100 — MSB ROTCR Rn T → Rn → T 0100nnnn00100101 — LSB SHAD Rm,Rn When Rn ≥ 0, Rn > Rm → [MSB → Rn] — SHAL Rn T ← Rn ← 0 0100nnnn00100000 — MSB 0100nnnn00100001 — SHAR Rn MSB → Rn → T SHLD Rm,Rn When Rn ≥ 0, Rn > Rm → [0 → Rn] — SHLL Rn T ← Rn ← 0 0100nnnn00000000 — MSB SHLR Rn 0 → Rn → T 0100nnnn00000001 — LSB SHLL2 Rn Rn > 2 → Rn 0100nnnn00001001 — — SHLL8 Rn Rn > 8 → Rn 0100nnnn00011001 — — SHLL16 Rn Rn > 16 → Rn 0100nnnn00101001 — — R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 LSB Page 201 of 1128 Section 7 Instruction Set Table 7.7 SH7751 Group, SH7751R Group Branch Instructions Instruction Operation Instruction Code Privileged T Bit BF label When T = 0, disp × 2 + PC + 4 → PC When T = 1, nop 10001011dddddddd — — BF/S label Delayed branch; when T = 0, disp × 2 + PC + 4 → PC When T = 1, nop 10001111dddddddd — — BT label When T = 1, disp × 2 + PC + 4 → PC When T = 0, nop 10001001dddddddd — — BT/S label Delayed branch; when T = 1, disp × 2 + PC + 4 → PC When T = 0, nop 10001101dddddddd — — BRA label Delayed branch, disp × 2 + PC + 4 → PC 1010dddddddddddd — — BRAF Rn Rn + PC + 4 → PC 0000nnnn00100011 — — BSR label Delayed branch, PC + 4 → PR, 1011dddddddddddd — disp × 2 + PC + 4 → PC — BSRF Rn Delayed branch, PC + 4 → PR, 0000nnnn00000011 — Rn + PC + 4 → PC — JMP @Rn Delayed branch, Rn → PC 0100nnnn00101011 — — JSR @Rn Delayed branch, PC + 4 → PR, 0100nnnn00001011 — Rn → PC — Delayed branch, PR → PC — RTS Page 202 of 1128 0000000000001011 — R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Table 7.8 Section 7 Instruction Set System Control Instructions Instruction Operation Instruction Code Privileged T Bit CLRMAC 0 → MACH, MACL 0000000000101000 — — CLRS 0→S 0000000001001000 — — CLRT 0→T 0000000000001000 — 0 Rm → SR 0100mmmm00001110 Privileged LSB LDC Rm,SR LDC Rm,GBR Rm → GBR 0100mmmm00011110 — — LDC Rm,VBR Rm → VBR 0100mmmm00101110 Privileged — LDC Rm,SSR Rm → SSR 0100mmmm00111110 Privileged — LDC Rm,SPC Rm → SPC 0100mmmm01001110 Privileged — LDC Rm,DBR Rm → DBR 0100mmmm11111010 Privileged — LDC Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 Privileged — LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 Privileged LSB LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 — — LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 Privileged — LDC.L @Rm+,SSR (Rm) → SSR, Rm + 4 → Rm 0100mmmm00110111 Privileged — LDC.L @Rm+,SPC (Rm) → SPC, Rm + 4 → Rm 0100mmmm01000111 Privileged — LDC.L @Rm+,DBR (Rm) → DBR, Rm + 4 → Rm 0100mmmm11110110 Privileged — LDC.L @Rm+,Rn_BANK (Rm) → Rn_BANK, Rm + 4 → Rm 0100mmmm1nnn0111 Privileged — LDS Rm,MACH Rm → MACH 0100mmmm00001010 — — LDS Rm,MACL Rm → MACL 0100mmmm00011010 — — LDS Rm,PR Rm → PR 0100mmmm00101010 — — LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 — — LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 — — LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 — — PTEH/PTEL → TLB 0000000000111000 Privileged — R0,@Rn R0 → (Rn) (without fetching cache block) 0000nnnn11000011 — — No operation 0000000000001001 — — OCBI @Rn Invalidates operand cache block 0000nnnn10010011 — — OCBP @Rn Writes back and invalidates operand cache block 0000nnnn10100011 — — OCBWB @Rn Writes back operand cache block 0000nnnn10110011 — — PREF @Rn (Rn) → operand cache 0000nnnn10000011 — — LDTLB MOVCA. L NOP R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 203 of 1128 Section 7 Instruction Set SH7751 Group, SH7751R Group Instruction Operation Instruction Code Privileged T Bit RTE Delayed branch, SSR/SPC → SR/PC 0000000000101011 Privileged — SETS 1→S 0000000001011000 — — SETT 1→T 0000000000011000 — 1 SLEEP Sleep or standby 0000000000011011 Privileged — STC SR,Rn SR → Rn 0000nnnn00000010 Privileged — STC GBR,Rn GBR → Rn 0000nnnn00010010 — — STC VBR,Rn VBR → Rn 0000nnnn00100010 Privileged — STC SSR,Rn SSR → Rn 0000nnnn00110010 Privileged — STC SPC,Rn SPC → Rn 0000nnnn01000010 Privileged — STC SGR,Rn SGR → Rn 0000nnnn00111010 Privileged — STC DBR,Rn DBR → Rn 0000nnnn11111010 Privileged — STC Rm_BANK,Rn Rm_BANK → Rn (m = 0 to 7) 0000nnnn1mmm0010 Privileged — STC.L SR,@-Rn Rn – 4 → Rn, SR → (Rn) 0100nnnn00000011 Privileged — STC.L GBR,@-Rn Rn – 4 → Rn, GBR → (Rn) 0100nnnn00010011 — — STC.L VBR,@-Rn Rn – 4 → Rn, VBR → (Rn) 0100nnnn00100011 Privileged — STC.L SSR,@-Rn Rn – 4 → Rn, SSR → (Rn) 0100nnnn00110011 Privileged — STC.L SPC,@-Rn Rn – 4 → Rn, SPC → (Rn) 0100nnnn01000011 Privileged — STC.L SGR,@-Rn Rn – 4 → Rn, SGR → (Rn) 0100nnnn00110010 Privileged — STC.L DBR,@-Rn Rn – 4 → Rn, DBR → (Rn) 0100nnnn11110010 Privileged — STC.L Rm_BANK,@-Rn Rn – 4 → Rn, 0100nnnn1mmm0011 Privileged Rm_BANK → (Rn) (m = 0 to 7) — STS MACH,Rn MACH → Rn 0000nnnn00001010 — — STS MACL,Rn MACL → Rn 0000nnnn00011010 — — STS PR,Rn PR → Rn 0000nnnn00101010 — — STS.L MACH,@-Rn Rn – 4 → Rn, MACH → (Rn) 0100nnnn00000010 — — STS.L MACL,@-Rn Rn – 4 → Rn, MACL → (Rn) 0100nnnn00010010 — — STS.L PR,@-Rn Rn – 4 → Rn, PR → (Rn) 0100nnnn00100010 — — TRAPA #imm PC + 2 → SPC, SR → SSR, #imm CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 0 1 CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1 1 0 CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7 1 1 Round robin mode (Initial value) Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0. Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be cleared by writing 0 after reading 1. For details of the settings, see the description of the AE bit in section 14.2.5, DMA Operation Register (DMAOR). Page 594 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing 0 after reading 1. For details of the settings, see the description of the NMIF bit in section 14.2.5, DMA Operation Register (DMAOR). Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are suspended. Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or when the NMI or AE bit in DMAOR is 1. For details of the settings, see the description of the DME bit in section 14.2.5, DMA Operation Register (DMAOR). 14.8 Operation (SH7751R) Operation specific to the SH7751R is described here. For details of operation, see section 14.3, Operation. 14.8.1 Channel Specification for a Normal DMA Transfer In normal DMA transfer mode, the DMAC always operates with eight channels, and external requests are only accepted on channel 0 (DREQ0) and channel 1 (DREQ1). After setting the registers of the channels in use, including CHCR, SAR, DAR, and DMATCR, DMA transfer is started on receiving a DMA transfer request in the transfer-enabled state (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), in the order of predetermined priority. The transfer ends when the transfer-end condition is satisfied. There are three modes for transfer requests: autorequest, external request, and on-chip peripheral module request. The addressing modes for DMA transfer are the single-address mode and the dual-address mode. Bus mode is selectable between burst mode and cycle steal mode. 14.8.2 Channel Specification for DDT-Mode DMA Transfer For DMA transfer in DDT mode, the DMAOR.DBL setting selects either four or eight channels. External requests are accepted on channels 0−3 when DMAOR.DBL = 0, and on channels 0−7 when DMAOR.DBL = 1. For further information on these settings, see the entry on the DBL bit in section 14.7.5, DMA Operation Register (DMAOR). R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 595 of 1128 Section 14 Direct Memory Access Controller (DMAC) 14.8.3 SH7751 Group, SH7751R Group Transfer Channel Notification in DDT Mode When the DMAC is set up for four-channel external request acceptance in DDT mode (DMAOR.DBL = 0), the ID [1:0] bits are used to notify the external device of the DMAC channel that is to be used. For more details, see section 14.5, On-Demand Data Transfer Mode (DDT Mode). When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), the ID [1:0] bits and the simultaneous (on the timing of TDACK assertion) assertion of ID2 from the BAVL (data bus available) pin are used to notify the external device of the DMAC channel that is to be used (see table 14.16, Notification of Transfer Channel in EightChannel DDT Mode). When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), it is important to note that the BAVL pin has the two functions as shown in table 14.17. Table 14.16 Notification of Transfer Channel in Eight-Channel DDT Mode BAVL/ID2 ID[1:0] Transfer Channel 1 00 CH0 01 CH1 10 CH2 11 CH3 00 CH4 01 CH5 10 CH6 11 CH7 0 Table 14.17 Function of BAVL Function of BAVL TDACK = High Bus available TDACK = Low Notification of channel number (ID2) Page 596 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 14.8.4 Section 14 Direct Memory Access Controller (DMAC) Clearing Request Queues by DTR Format In DDT mode, the request queues of any channel can be cleared by using DTR.ID, DTR.MD, DTR.SZ, and DTR.COUNT [7:4] in a DTR format. This function is only available when DMAOR.DBL = 1. Table 14.18 shows the DTR format settings for clearing request queues. Table 14.18 DTR Format for Clearing Request Queues DMAOR.DBL DTR.ID DTR.MD DTR.SZ DTR.COUNT[7:4] Description 0 10 110 * Clear the request queues of all channels (1−7). 00 Clear the CH0 request-accepted flag 11 1 00 10 Setting prohibited 110 * Clear the request queues of all channels (1−7). Clear the CH0 request-accepted flag. 11 0001 Clear the CH0 request-accepted flag 0010 Clear the CH1 request queues. 0011 Clear the CH2 request queues. 0100 Clear the CH3 request queues. 0101 Clear the CH4 request queues. 0110 Clear the CH5 request queues. 0111 Clear the CH6 request queues. 1000 Clear the CH7 request queues. Note: (SH7751R) DTR.SZ = DTR[31:29], DTR.ID = DTR[27:26], DTR.MD = DTR[25:24], DTR.COUNT[7:4] = DTR[23:20] 14.8.5 Interrupt-Request Codes When the number of transfers specified in DMATCR has been finished and the interrupt request is enabled (CHCR.IE = 1), a transfer-end interrupt request can be sent to the CPU from each channel. Table 14.19 lists the interrupt-request codes that are associated with these transfer-end interrupts. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 597 of 1128 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Table 14.19 DMAC Interrupt-Request Codes Source of the Interrupt Description INTEVT Code Priority DMTE0 CH0 transfer-end interrupt H'640 High DMTE1 CH1 transfer-end interrupt H'660 DMTE2 CH2 transfer-end interrupt H'680 DMTE3 CH3 transfer-end interrupt H'6A0 DMTE4 CH4 transfer-end interrupt H'780 DMTE5 CH5 transfer-end interrupt H'7A0 DMTE6 CH6 transfer-end interrupt H'7C0 DMTE7 CH7 transfer-end interrupt H'7E0 DMAE Address error interrupt H'6C0 Low DMTE4–DMTE7: These codes are not used in the SH7751. CKIO DBREQ BAVL/ID2 TR RA A25–A0 D63–D0 RAS, CAS, WE CA DTR D0 BA D1 D2 RD TDACK ID1, ID0 00 Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Page 598 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ BAVL/ID2 TR RA A25–A0 D63–D0 RAS, CAS, WE CA DTR D0 BA D1 D2 RD TDACK ID1, ID0 00 Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus → External Device/32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 599 of 1128 Section 14 Direct Memory Access Controller (DMAC) 14.9 SH7751 Group, SH7751R Group Usage Notes 1. When modifying SAR0–SAR3, DAR0–DAR3, DMATCR0–DMATCR3, and CHCR0– CHCR3 in the SH7751 or when modifying SAR0–SAR7, DAR0–DAR7, DMATCR0– DMATCR7, and CHCR0–CHCR7 in the SH7751R, first clear the DE bit for the relevant channel to 0. 2. The NMIF bit in DMAOR is set when an NMI interrupt is input even if the DMAC is not operating. Confirmation method when DMA transfer is not executed correctly: With the SH7751, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0–CHCR3, and DMATCR0–DMATCR3. With the SH7751R, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0–CHCR7, and DMATCR0–DMATCR7. If NMIF was set before the transfer, the DMATCR transfer count will remain at the set value. If NMIF was set during the transfer, when the DE bit is 1 and the TE bit is 0 in CHCR0–CHCR3 in the SH7751 or CHCR0– CHCR7 in the SH7751R, the DMATCR value will indicate the remaining number of transfers. Also, the next addresses to be accessed can be found by reading SAR0–SAR3 and DAR0– DAR3 in the SH7751 or SAR0–SAR7 and DAR0–DAR7 in the SH7751R. If the AE bit has been set, an address error has occurred. Check the set values in CHCR, SAR, and DAR. 3. Check that DMA transfer is not in progress before making a transition to the module standby state, standby mode, or deep sleep mode. Either check that TE = 1 in the SH7751's CHCR0–CHCR3 or in the SH7751R's CHCR0– CHCR7, or clear DME to 0 in DMAOR to terminate DMA transfer. When DME is cleared to 0 in DMAOR, transfer halts at the end of the currently executing DMA bus cycle. Note, therefore, that transfer may not end immediately, depending on the transfer data size. DMA operation is not guaranteed if the module standby state, standby mode, or deep sleep mode is entered without confirming that DMA transfer has ended. 4. Do not specify a DMAC, CCN, BSC, UBC, or PCIC control register as the DMAC transfer source or destination. 5. When activating the DMAC, make the SAR, DAR, and DMATCR register settings for the relevant channel before setting DE to 1 in CHCR, or make the register settings with DE cleared to 0 in CHCR, then set DE to 1. It does not matter whether setting of the DME bit to 1 in DMAOR is carried out first or last. To operate the relevant channel, DME and DE must both be set to 1. The DMAC may not operate normally if the SAR, DAR, and DMATCR settings are not made (with the exception of the unused register in single address mode). 6. After the DMATCR count reaches 0 and DMA transfer ends normally, always write 0 to DMATCR even when executing the maximum number of transfers on the same channel. Page 600 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 7. When falling edge detection is used for external requests, keep the external request pin high when making DMAC settings. 8. When using the DMAC in single address mode, set an external address as the address. All channels will halt due to an address error if an on-chip peripheral module address is set. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 601 of 1128 Section 14 Direct Memory Access Controller (DMAC) Page 602 of 1128 SH7751 Group, SH7751R Group R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) 15.1 Overview This LSI is equipped with a single-channel serial communication interface (SCI) and a singlechannel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF). The SCI can handle both asynchronous and synchronous serial communication. The SCI supports a smart card interface. This is a serial communication function supporting a subset of the ISO/IEC 7816-3 (identification cards) standard. For details, see section 17, Smart Card Interface. The SCIF is a dedicated asynchronous communication serial interface with built-in 16-stage FIFO registers for both transmission and reception. For details, see section 16, Serial Communication Interface with FIFO (SCIF). 15.1.1 Features SCI features are listed below. • Choice of synchronous or asynchronous serial communication mode ⎯ Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A multiprocessor communication function is also provided that enables serial data communication with a number of processors. There is a choice of 12 serial data transfer formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even/odd/none Multiprocessor bit: 1 or 0 Receive error detection: Parity, overrun, and framing errors Break detection: A break can be detected by reading the RxD pin level directly from the serial port register (SCSPTR1) when a framing error occurs. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 603 of 1128 Section 15 Serial Communication Interface (SCI) • • • • • SH7751 Group, SH7751R Group ⎯ Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. There is a single serial data transfer format. Data length: 8 bits Receive error detection: Overrun errors Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. On-chip baud rate generator allows any bit rate to be selected. Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin Four interrupt sources There are four interrupt sources—transmit-data-empty, transmit-end, receive-data-full, and receive-error—that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute a data transfer. When not in use, the SCI can be stopped by halting its clock supply to reduce power consumption. Page 604 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 15.1.2 Section 15 Serial Communication Interface (SCI) Block Diagram Bus interface Figure 15.1 shows a block diagram of the SCI. Module data bus RxD SCRDR1 SCTDR1 SCRSR1 SCTSR1 TxD Parity generation SCSSR1 SCSCR1 SCSMR1 SCSPTR1 Transmission/ reception control Internal data bus SCBRR1 Pck Baud rate generator Pck/4 Pck/16 Pck/64 Clock Parity check External clock SCK TEI TXI RXI ERI SCI Legend: SCRSR1: SCRDR1: SCTSR1: SCTDR1: SCSMR1: SCSCR1: SCSSR1: SCBRR1: SCSPTR1: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Figure 15.1 Block Diagram of SCI R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 605 of 1128 Section 15 Serial Communication Interface (SCI) 15.1.3 SH7751 Group, SH7751R Group Pin Configuration Table 15.1 shows the SCI pin configuration. Table 15.1 SCI Pins Pin Name Abbreviation I/O Function Serial clock pin Receive data pin SCK I/O Clock input/output RxD Input Receive data input Transmit data pin TxD Output Transmit data output Note: They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/A bit in SCSMR1. Break state transmission and detection, can be set in the SCI's SCSPTR1 register. 15.1.4 Register Configuration The SCI has the internal registers shown in table 15.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to perform transmitter/receiver control. With the exception of the serial port register, the SCI registers are initialized in standby mode and in the module standby state as well as after a power-on reset or manual reset. When recovering from standby mode or the module standby state, the registers must be set again. Table 15.2 SCI Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Serial mode register SCSMR1 R/W H'00 H'FFE00000 H'1FE00000 8 Bit rate register SCBRR1 R/W H'FF H'FFE00004 H'1FE00004 8 Serial control register SCSCR1 R/W H'00 H'FFE00008 H'1FE00008 8 Transmit data register SCTDR1 R/W H'FF H'FFE0000C H'1FE0000C 8 1 Serial status register SCSSR1 R/(W)* H'84 H'FFE00010 H'1FE00010 8 Receive data register SCRDR1 R H'00 H'FFE00014 H'1FE00014 8 Serial port register SCSPTR1 R/W H'00*2 H'FFE0001C H'1FE0001C 8 Notes: 1. Only 0 can be written, to clear flags. 2. The value of bits 2 and 0 is undefined Page 606 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 15.2 Register Descriptions 15.2.1 Receive Shift Register (SCRSR1) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCRSR1 is the register used to receive serial data. The SCI sets serial data input from the RxD pin in SCRSR1 in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to SCRDR1 automatically. SCRSR1 cannot be directly read or written to by the CPU. 15.2.2 Receive Data Register (SCRDR1) Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R SCRDR1 is the register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received data from SCRSR1 to SCRDR1 where it is stored, and completes the receive operation. SCRSR1 is then enabled for reception. Since SCRSR1 and SCRDR1 function as a double buffer in this way, it is possible to receive data continuously. SCRDR1 is a read-only register, and cannot be written to by the CPU. SCRDR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 607 of 1128 Section 15 Serial Communication Interface (SCI) 15.2.3 SH7751 Group, SH7751R Group Transmit Shift Register (SCTSR1) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCTSR1 is the register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from SCTDR1 to SCTSR1, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCTDR1 to SCTSR1, and transmission started, automatically. However, data transfer from SCTDR1 to SCTSR1 is not performed if the TDRE flag in the serial status register (SCSSR1) is set to 1. SCTSR1 cannot be directly read or written to by the CPU. 15.2.4 Transmit Data Register (SCTDR1) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: SCTDR1 is an 8-bit register that stores data for serial transmission. When the SCI detects that SCTSR1 is empty, it transfers the transmit data written in SCTDR1 to SCTSR1 and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to SCTDR1 during serial transmission of the data in SCTSR1. SCTDR1 can be read or written to by the CPU at all times. SCTDR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state. Page 608 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 15.2.5 Section 15 Serial Communication Interface (SCI) Serial Mode Register (SCSMR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SCSMR1 is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SCSMR1 can be read or written to by the CPU at all times. SCSMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7—Communication Mode (C/A): Selects asynchronous mode or synchronous mode as the SCI operating mode. Bit 7: C/A Description 0 Asynchronous mode 1 Synchronous mode (Initial value) Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting, Bit 6: CHR Description 0 8-bit data 1 Note: (Initial value) 7-bit data* * When 7-bit data is selected, the MSB (bit 7) of SCTDR1 is not transmitted. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 609 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5: PE Description 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * (Initial value) When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4: O/E Description 0 Even parity*1 1 Odd parity* (Initial value) 2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set, the STOP bit setting is invalid since stop bits are not added. Bit 3: STOP Description 0 1 stop bit*1 1 (Initial value) 2 2 stop bits* Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. Page 610 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor Communication Function. Bit 2: MP Description 0 Multiprocessor function disabled 1 Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. The clock source can be selected from Pck, Pck/4, Pck/16, and Pck/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.9, Bit Rate Register (SCBRR1). Bit 1: CKS1 Bit 0: CKS0 Description 0 0 Pck clock 1 Pck/4 clock 0 Pck/16 clock 1 Pck/64 clock 1 (Initial value) Note: Pck: Peripheral clock 15.2.6 Serial Control Register (SCSCR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The SCSCR1 register performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 611 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group SCSCR1 can be read or written to by the CPU at all times. SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and the TDRE flag in SCSSR1 is set to 1. Bit 7: TIE Description 0 Transmit-data-empty interrupt (TXI) request disabled* 1 Transmit-data-empty interrupt (TXI) request enabled Note: * (Initial value) TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0. Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1. Bit 6: RIE Description 0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled* (Initial value) 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Note: * RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5: TE Description 0 Transmission disabled* 1 Transmission enabled*2 1 (Initial value) Notes: 1. The TDRE flag in SCSSR1 is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to SCTDR1 and the TDRE flag in SCSSR1 is cleared to 0. SCSMR1 setting must be performed to decide the transmit format before setting the TE bit to 1. Page 612 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4: RE Description 0 Reception disabled*1 1 Reception enabled* (Initial value) 2 Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SCSMR1 setting must be performed to decide the receive format before setting the RE bit to 1. Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR1 is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE Description 0 Multiprocessor interrupts disabled (normal reception performed) (Initial value) [Clearing conditions] 1 Note: • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received Multiprocessor interrupts enabled* * When receive data including MPB = 1 is received, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCSCR1 are set to 1) and FER and ORER flag setting is enabled. Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables transmit-end interrupt (TEI) request generation when there is no valid transmit data in SCTDR1 at the time for MSB data transmission. Bit 2: TEIE Description 0 Transmit-end interrupt (TEI) request disabled* 1 Transmit-end interrupt (TEI) request enabled* Note: * (Initial value) TEI interrupt requests can be cleared by reading 1 from the TDRE flag in SCSSR1, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 613 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining the SCI's operating mode with SCSMR1. For details of clock source selection, see table 15.9 in section 15.3, Operation. Bit 1: CKE1 Bit 0: CKE0 Description 0 0 Asynchronous mode Internal clock/SCK pin functions as input pin (input signal ignored)*1 Synchronous mode Internal clock/SCK pin functions as serial clock output*1 Asynchronous mode Internal clock/SCK pin functions as 2 clock output* Synchronous mode Internal clock/SCK pin functions as serial clock output Asynchronous mode External clock/SCK pin functions as clock input*3 Synchronous mode External clock/SCK pin functions as serial clock input Asynchronous mode External clock/SCK pin functions as clock input*3 Synchronous mode External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. Page 614 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 15.2.7 Serial Status Register (SCSSR1) Bit: Initial value: R/W: Note: Section 15 Serial Communication Interface (SCI) * 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 — 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Only 0 can be written, to clear the flag. SCSSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SCSSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SCSSR1 is initialized to H'84 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1. Bit 7: TDRE 0 Description Valid transmit data has been written to SCTDR1 [Clearing conditions] 1 • When 0 is written to TDRE after reading TDRE = 1 • When data is written to SCTDR1 by the DMAC There is no valid transmit data in SCTDR1 (Initial value) [Setting conditions] • Power-on reset, manual reset, standby mode, or module standby • When the TE bit in SCSCR1 is 0 • When data is transferred from SCTDR1 to SCTSR1 and data can be written to SCTDR1 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 615 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Bit 6—Receive Data Register Full (RDRF): Indicates that the received data has been stored in SCRDR1. Bit 6: RDRF Description 0 There is no valid receive data in SCRDR1 (Initial value) [Clearing conditions] 1 • Power-on reset, manual reset, standby mode, or module standby • When 0 is written to RDRF after reading RDRF = 1 • When data in SCRDR1 is read by the DMAC There is valid receive data in SCRDR1 [Setting condition] When serial reception ends normally and receive data is transferred from SCRSR1 to SCRDR1 Note: SCRDR1 and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCSCR1 is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5: ORER Description 0 Reception in progress, or reception has ended normally*1 (Initial value) [Clearing conditions] 1 • Power-on reset, manual reset, standby mode, or module standby • When 0 is written to ORER after reading ORER = 1 An overrun error occurred during reception*2 [Setting condition] When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. 2. The receive data prior to the overrun error is retained in SCRDR1, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued either. Page 616 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4: FER Description 0 Reception in progress, or reception has ended normally*1 (Initial value) [Clearing conditions] 1 • Power-on reset, manual reset, standby mode, or module standby • When 0 is written to FER after reading FER = 1 A framing error occurred during reception [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0*2 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set to 1. Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception with parity addition in asynchronous mode, causing abnormal termination. Bit 3: PER Description 0 Reception in progress, or reception has ended normally*1 (Initial value) [Clearing conditions] 1 • Power-on reset, manual reset, standby mode, or module standby • When 0 is written to PER after reading PER = 1 A parity error occurred during reception*2 [Setting condition] When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR1 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. 2. If a parity error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is not set. Serial reception cannot be continued while the PER flag is set to 1. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 617 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Bit 2—Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2: TEND Description 0 Transmission is in progress [Clearing conditions] 1 • When 0 is written to TDRE after reading TDRE = 1 • When data is written to SCTDR1 by the DMAC Transmission has been ended (Initial value) [Setting conditions] • Power-on reset, manual reset, standby mode, or module standby • When the TE bit in SCSCR1 is 0 • When TDRE = 1 on transmission of the last bit of a 1-byte serial transmit character Bit 1—Multiprocessor Bit (MPB): This bit is read-only and cannot be written to. The read value is undefined. Note: This bit is prepared for storing a multi-processor bit in the received data when the receipt is carried out with a multi-processor format in asynchronous mode, however, this does not function correctly in this LSI. Do not use the read value from this bit. Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used, and when the operation is not transmission. Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether transmission has been completed before changing its value. Bit 0: MPBT Description 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Page 618 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 15.2.8 Section 15 Serial Communication Interface (SCI) Serial Port Register (SCSPTR1) Bit: Initial value: R/W: 7 6 5 4 EIO — — — 3 2 1 0 0 0 0 0 0 — 0 — R/W — — — R/W R/W R/W R/W SPB1IO SPB1DT SPB0IO SPB0DT SCSPTR1 is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt. SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. SCSPTR1 is not initialized in the module standby state or standby mode. Bit 7—Error Interrupt Only (EIO): When the EIO bit is 1, an RXI interrupt request is not sent to the CPU even if the RIE bit is set to 1. When the DMAC is used, this setting means that only ERI interrupts are handled by the CPU. The DMAC transfers read data to memory or another peripheral module. This bit specifies enabling or disabling of the RXI interrupt. Bit 7: EIO Description 0 When the RIE bit is 1, RXI and ERI interrupts are sent to INTC (Initial value) 1 When the RIE bit is 1, only ERI interrupts are sent to INTC Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO Description 0 SPB1DT bit value is not output to the SCK pin 1 SPB1DT bit value is output to the SCK pin R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 (Initial value) Page 619 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on or manual reset is undefined. Bit 2: SPB1DT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 1—Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR1 should be cleared to 0. Bit 1: SPB0IO Description 0 SPB0DT bit value is not output to the TxD pin 1 SPB0DT bit value is output to the TxD pin (Initial value) Bit 0—Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on or manual reset is undefined. Bit 0: SPB0DT Description 0 Input/output data is low-level 1 Input/output data is high-level Page 620 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) SCI I/O port block diagrams are shown in figures 15.2 to 15.4. Reset R Q D SPB1IO C SPTRW Internal data bus Reset SCK Q R D SPB1DT C SPTRW SCI Clock output enable signal Serial clock output signal * Serial clock input signal Clock input enable signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/A bit in SCSMR1. Figure 15.2 SCK Pin R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 621 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Reset R Q D SPB0IO C Internal data bus SPTRW Reset TxD R Q D SPB0DT C SPTRW SCI Transmit enable signal Serial transmit data Legend: SPTRW: Write to SPTR Figure 15.3 TxD Pin SCI RxD Serial receive data Internal data bus SPTRR Legend: SPTRR: Read SPTR Figure 15.4 RxD Pin Page 622 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 15.2.9 Section 15 Serial Communication Interface (SCI) Bit Rate Register (SCBRR1) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: SCBRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR1. SCBRR1 can be read or written to by the CPU at all times. SCBRR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state. The SCBRR1 setting is found from the following equations. Asynchronous mode: N= Pck 64 × 22n – 1 × B × 106 – 1 Synchronous mode: N= Pck 8 × 22n – 1 × B × 106 – 1 Where B: Bit rate (bits/s) N: SCBRR1 setting for baud rate generator (0 ≤ N ≤ 255) Pck: Peripheral module operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR1 Setting n Clock CKS1 CKS0 0 Pck 0 0 1 Pck/4 0 1 2 Pck/16 1 0 3 Pck/64 1 1 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 623 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group The bit rate error in asynchronous mode is found from the following equation: Error (%) = Pck × 106 (N + 1) × B × 64 × 22n – 1 – 1 × 100 Table 15.3 shows sample SCBRR1 settings in asynchronous mode, and table 15.4 shows sample SCBRR1 settings in synchronous mode. Page 624 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode Pck (MHz) 2 2.097152 2.4576 3 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34 9600 0 6 –6.99 0 6 –2.48 0 7 0.00 0 9 –2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 –2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 –18.62 0 1 –14.67 0 1 0.00 Pck (MHz) 3.6864 4 4.9152 5 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 –6.99 0 7 0.00 0 7 1.73 31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 625 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Pck (MHz) 6 6.144 7.37288 8 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 –2.34 0 4 0.00 0 5 0.00 0 6 –6.99 Pck (MHz) 9.8304 10 12 12.288 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 0.16 0 19 0.00 31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00 Page 626 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Pck (MHz) 14.7456 16 19.6608 20 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 31250 0 14 –1.70 0 15 0.00 0 19 –1.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 Pck (MHz) 24 24.576 28.7 30 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 106 –0.44 3 108 0.08 3 126 0.31 3 132 0.13 150 3 77 0.16 3 79 0.00 3 92 0.46 3 97 –0.35 300 2 155 0.16 2 159 0.00 2 186 –0.08 2 194 0.16 600 2 77 0.16 2 79 0.00 2 92 0.46 2 97 –0.35 1200 1 155 0.16 1 159 0.00 1 186 –0.08 1 194 0.16 2400 1 77 0.16 1 79 0.00 1 92 0.46 1 97 –0.35 4800 0 155 0.16 0 159 0.00 0 186 –0.08 0 194 –1.36 9600 0 77 0.16 0 79 0.00 0 92 0.46 0 97 –0.35 19200 0 38 0.16 0 39 0.00 0 46 –0.61 0 48 –0.35 31250 0 23 0.00 0 24 –1.70 0 28 –1.03 0 29 0.00 38400 0 19 –2.34 0 19 0.00 0 22 1.55 0 23 1.73 Legend: Blank: No setting is available. —: A setting is available but error occurs. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 627 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode Pck (MHz) 4 Bit Rate (bits/s) n N 8 16 28.7 30 n N n N n N n N 10 — — — — — — — — — — 250 2 249 3 124 3 249 — — — — 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 0 9 0 19 0 39 0 71 0 74 250k 0 3 0 7 0 15 — — 0 29 500k 0 1 0 3 0 7 — — 0 14 1M 0 0* 0 1 0 3 — — — — 0 0* 0 1 — — — — 2M Legend: Blank: No setting is available. —: A setting is available but error occurs. Notes: As far as possible, the setting should be made so that the error is within 1%. * Continuous transmission/reception is not possible. Page 628 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pck (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 629 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pck (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) Pck (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 24 4.0000 4000000.0 28.7 4.7833 4783333.3 30 5.0000 5000000.0 Page 630 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 15.3 Operation 15.3.1 Overview Section 15 Serial Communication Interface (SCI) The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SCSMR1 as shown in table 15.8. The SCI clock source is determined by a combination of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1, as shown in table 15.9. • Asynchronous mode ⎯ Data length: Choice of 7 or 8 bits ⎯ Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ⎯ Detection of framing, parity, and overrun errors, and breaks, during reception ⎯ Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output. When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). • Synchronous mode ⎯ Transfer format: Fixed 8-bit data ⎯ Detection of overrun errors during reception ⎯ Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip. When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 631 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection SCSMR1 Settings SCI Transfer Format Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: C/A CHR MP PE STOP Mode 0 0 0 0 0 1 1 Asynchronous mode Data Length Multiprocessor Parity Stop Bit Bit Bit Length 8-bit data No No 2 bits 0 Yes 1 1 0 0 7-bit data No 1 * Yes 0 0 1 1 0 * * * * 1 bit 2 bits Asynchronous 8-bit data mode (multiprocessor 7-bit data format) Yes No 1 bit 2 bits 1 bit 1 1 1 bit 2 bits 1 0 1 bit 2 bits 1 1 1 bit 2 bits Synchronous mode 8-bit data No None Note: An asterisk in the table means “Don't care.” Page 632 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection SCSMR1 SCSCR1 Setting Bit 7: C/A Bit 1: CKE1 Bit 0: CKE0 0 0 0 1 1 SCI Transmit/Receive Clock Mode Asynchronous mode 0 Clock Source SCK Pin Function Internal SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Internal Outputs serial clock External Inputs serial clock 1 1 0 0 1 1 Synchronous mode 0 1 15.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.5 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the eighth pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 633 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Idle state (mark state) 1 Serial data (LSB) 0 D0 Start bit 1 bit 1 (MSB) D1 D2 D3 D4 D5 D6 D7 Transmit/receive data 7 or 8 bits 0/1 1 1 Parity bit Stop bit(s) 1 bit, or none 1 or 2 bits One unit of transfer data (character or frame) Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Data Transfer Format Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR1 setting. Page 634 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Table 15.10 Serial Transfer Formats (Asynchronous Mode) SCSMR1 Settings Serial Transfer Format and Frame Length CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 * 1 0 S 8-bit data MPB STOP 0 * 1 1 S 8-bit data MPB STOP STOP 1 * 1 0 S 7-bit data MPB STOP 1 * 1 1 S 7-bit data MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 635 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group MPB: Multiprocessor bit Note: An asterisk in the table means “Don't care.” Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.6. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 One frame Figure 15.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Figure 15.7 shows a sample SCI initialization flowchart. Page 636 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 1. Set the clock selection in SCSCR1. Initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCSCR1 to 0 When clock output is selected in asynchronous mode, it is output immediately after SCSCR1 settings are made. Set CKE1 and CKE0 bits in SCSCR1 (leaving TE and RE bits cleared to 0) 2. Set the data transfer format in SCSMR1. 3. Write a value corresponding to the bit rate into SCBRR1. (Not necessary if an external clock is used.) Set data transfer format in SCSMR1 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Set value in SCBRR1 Wait 1-bit interval elapsed? Yes Set TE and RE bits in SCSCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits No Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCI will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. End Figure 15.7 Sample SCI Initialization Flowchart Serial Data Transmission (Asynchronous Mode): Figure 15.8 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 637 of 1128 Section 15 Serial Communication Interface (SCI) 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Start of transmission Read TDRE flag in SCSSR1 TDRE = 1? No Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 All data transmitted? No Yes Read TEND flag in SCSSR1 TEND = 1? SH7751 Group, SH7751R Group No 2. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) 3. Break output at the end of serial transmission: To output a break in serial transmission, clear the SPB0DT bit to 0 and set the SPB0IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR1 to 0. Yes Break output? No Yes Clear SPB0DT to 0 and set SPB0IO to 1 Clear TE bit in SCSCR1 to 0 End of transmission Figure 15.8 Sample Serial Transmission Flowchart Page 638 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. (A format in which neither a parity bit nor a multiprocessor bit is output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. If the TEIE bit in SCSCR1 is set to 1 at this time, a TEI interrupt request is generated. Figure 15.9 shows an example of the operation for transmission in asynchronous mode. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 639 of 1128 Section 15 Serial Communication Interface (SCI) Start bit 1 Serial data 0 Data D0 D1 SH7751 Group, SH7751R Group Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt TXI interrupt request request Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler TEI interrupt request One frame Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. Page 640 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Start of reception Read ORER, PER, and FER flags in SCSSR1 PER or FER or ORER = 1? No Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 Yes Error handling 1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SCSSR1 to identify the error. After performing the appropriate error handling, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the RxD pin. 2. SCI status check and receive data read : Read SCSSR1 and check that RDRF = 1, then read the receive data in SCRDR1 and clear the RDRF flag to 0. 3. Serial reception continuation procedure: To continue serial reception, complete zeroclearing of the RDRF flag before the stop bit for the current frame is received. (The RDRF flag is cleared automatically when the direct memory access controller (DMAC) is activated by an RXI interrupt and the SCRDR1 value is read.) End of reception Figure 15.10 Sample Serial Reception Flowchart (1) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 641 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling No Clear RE bit in SCSCR1 to 0 PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SCSSR1 to 0 End Figure 15.10 Sample Serial Reception Flowchart (2) Page 642 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. a. Parity check: The SCI checks whether the number of 1-bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SCSMR1. b. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. c. Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from SCRSR1 to SCRDR1. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If a receive error is detected in the error check, the operation is as shown in table 15.11. Note: No further receive operations can be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. 4. If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated. A receive-data-full request is always output to the DMAC when the RDRF flag changes to 1. Table 15.11 Receive Error Conditions Receive Error Abbreviation Condition Data Transfer Overrun error ORER Reception of next data is completed while RDRF flag in SCSSR1 is set to 1 Receive data is not transferred from SCRSR1 to SCRDR1 Framing error FER Stop bit is 0 Receive data is transferred from SCRSR1 to SCRDR1 Parity error PER Received data parity differs from that (even or odd) set in SCSMR1 Receive data is transferred from SCRSR1 to SCRDR1 Figure 15.11 shows an example of the operation for reception in asynchronous mode. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 643 of 1128 Section 15 Serial Communication Interface (SCI) 1 Serial data Start bit 0 Data D0 D1 SH7751 Group, SH7751R Group Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 0 0/1 RDRF FER RXI interrupt request One frame SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler ERI interrupt request generated by framing error Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 15.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a serial transmission line. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with the multiprocessor bit set to 1. It then sends transmit data as data with the multiprocessor bit cleared to 0. The receiving station skips the data until data with the multiprocessor bit set to 1 is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Page 644 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Figure 15.12 shows an example of inter-processor communication using a multiprocessor format. Note: Even when this LSI has received data with a 0 multiprocessor bit that was meant to be sent to another station, the RDRF flag in SCSSR1 is set to 1. When the RDRF flag in SCSSR1 is set to 1, the exception handling routine reads the MPIE bit in SCSCR1, and skips the receive data if the MPIE bit is 1. Skipping of unnecessary data is achieved by collaborative operation with the exception handling routine. Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle: Receiving station specification Legend: (MPB = 0) Data transmission cycle: Data transmission to receiving station specified by ID MPB: Multiprocessor bit Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 645 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Data Transfer Formats There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 15.10. Clock See the description under Clock in section 15.3.2, Operation in Asynchronous Mode. Data Transfer Operations Multiprocessor Serial Data Transmission: Figure 15.13 shows a sample flowchart for multiprocessor serial data transmission. Use the following procedure for multiprocessor serial data transmission after enabling the SCI for transmission. Page 646 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Start of transmission Read TEND flag in SCSSR1 TEND = 1? No 2. Preparation for data transfer: Read SCSSR1 and check that the TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1. Yes Set MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1 3. Serial data transmission: Write the first transmit data to SCTDR1, then clear the TDRE flag to 0. Clear TDRE flag to 0 Read TEND flag in SCSSR1 TEND = 1? 1. SCI status check and ID data write: Read SCSSR1 and check that the TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1. Finally, clear the TDRE flag to 0. No Yes Clear MPBT bit in SCSSR1 to 0 To continue data transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) Write data to SCTDR1 Clear TDRE flag to 0 Read TDRE flag in SCSSR1 TDRE = 1? No Yes No All data transmitted? Yes End of transmission Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 647 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. The SCI monitors the TDRE flag. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 5. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE bit) in SCSCR1 is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. The order of transmission is the same as in step 2. Figure 15.14 shows an example of SCI operation for transmission using a multiprocessor format. Page 648 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Start bit 1 Serial data 0 Multiproces- Stop sor bit bit Data D0 D1 Section 15 Serial Communication Interface (SCI) D7 1 Start bit 1 0 Data D0 D1 Multiproces- Stop Start bit sor bit bit D7 0 1 0 Data D0 D1 Multiproces- Stop sor bit bit D7 0 1 Idle state (mark state) TDRE TEND One frame Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler TXI interrupt request TEI interrupt request MPBT bit cleared to 0, data written to SCTDR1, and TDRE flag cleared to 0 by TEI interrupt handler Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Multiprocessor Serial Data Reception 1. Method for determining whether an interrupt generated during receive operation is a multiprocessor interrupt When an interrupt such as RXI occurs during receive operation using the on-chip SCI multiprocessor communication function, check the state of the MPIE bit in the SCSCR1 register as part of the interrupt handling routine. a. If the MPIE bit in the SCSCR1 register is set to 1 Ignore the received data. Data with the multiprocessor bit (MPB) set to 0 and intended for another station was received, and the RDRF bit in the SCSCR1 register was set to 1. Therefore, clear the RDRF bit in the SCSCR1 register to 0. b. If the MPIE bit in the SCSCR1 register is cleared to 0 A multiprocessor interrupt indicating that data (ID) with the multiprocessor bit (MPB) set to 1 was received, or a receive data full interrupt (RXI) occurred when data with the multiprocessor bit (MPB) set to 0 and intended for this station was received. 2. Method for determining whether received data is ID or data Do not use the MPB bit in the SCSSR1 register for software processing. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 649 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group When using software processing to determine whether received data is ID (MPB = 1) or data (MPB = 0), use a procedure such as saving a user-defined flag in memory to indicate receive start. Figure 15.15 shows a flowchart of a sample software workaround. Page 650 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Receive data full interrupt generated Yes User-defined receive start flag = 1? No Read ORER and FER flags in SCSSR1 FER or ORER = 1 ? Yes No Read RDRF flag in SCSSR1 No MPIE = 0 ? Yes Read receive data in SCRDR1 No This station's ID? Yes Set RDRF = 0 and MPIE = 1 Set user-defined receive start flag to 1 End of ID reception handling Read ORER and FER flags in SCSSR1 FER or ORER = 1? Yes No Read receive data in SCRDR1 No All data received? Yes Clear user-defined receive start flag to 0 RTE End of data reception Error handling Figure 15.15 Sample Flowchart of Multiprocessor Serial Reception with Interrupt Generation Figure 15.16 shows a sample flowchart of multiprocessor serial reception. To perform multiprocessor serial reception, first enable the SCI for data reception and then follow the procedure shown below. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 651 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Start of reception Set MPIE bit to 1 RXI = 1 ? No Yes Yes User-defined receive start flag = 1? No Read ORER and FER flags in SCSSR1 FER or ORER = 1 ? Yes No Read RDRF flag in SCSSR1 No MPIE = 0 ? Yes Read receive data in SCRDR1 No This station's ID? Yes Set RDRF = 0 and MPIE = 1 Set user-defined receive start flag to 1 End of ID reception handling Read ORER and FER flags in SCSSR1 FER or ORER = 1 ? Yes No Read receive data in SCRDR1 No All data received? Yes Clear user-defined receive start flag to 0 RTE End of data reception Error handling Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (1) Page 652 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling Clear RE bit in SCSCR1 to 0 Clear ORER and FER flags in SCSSR1 to 0 End Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (2) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 653 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Figure 15.17 shows an example of SCI operation for multiprocessor format reception. 1 Start Data (ID1) bit Serial data 0 D0 D1 Stop Start MPB bit bit D7 1 1 0 Data (Data1) D0 D1 Stop MPB bit D7 0 1 Idle state (mark state) 1 MPIE RDRF SCRDR1 value ID1 RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data is not this station's ID, MPIE bit is set to 1 again RXI interrupt request The RDRF flag is cleared to 0 by is the RXI interrupt handler (a) Data does not match station's ID 1 Start Data (ID2) bit Serial data 0 D0 D1 Stop Start MPB bit bit D7 1 1 0 Data (Data2) D0 D1 Stop MPB bit D7 0 1 Idle state (mark state) 1 MPIE RDRF SCRDR1 value RXI interrupt request (multiprocessor interrupt) MPIE = 0 Data2 ID2 ID1 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data matches this station's ID, reception continues and data is received by RXI interrupt handler MPIE bit set to 1 again (b) Data matches station's ID Figure 15.17 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Page 654 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) In multiprocessor mode serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3. If the MPIE bit is 1, MPIE is cleared to 0 when a 1 is received in the multiprocessor bit position. If the multiprocessor bit is 0, the MPIE bit is not changed. 4. If the MPIE bit is 0, RDRF is checked at the stop bit position, and if RDRF is 1 the overrun error bit is set. If the stop bit is not 0, the framing error bit is set. If RDRF is 0, the value in SCRSR1 is transferred to SCRDR1, and if the stop bit is 0, RDRF is set to 1. 15.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.18 shows the general format for synchronous serial communication. One unit of transfer data (character or frame) * * Serial clock LSB Serial data Don't care Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transfer Figure 15.18 Data Format in Synchronous Communication R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 655 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group In synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the falling edge of the serial clock. Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. In reception only, if an on-chip clock source is selected, clock pulses are output while RE = 1. When the last data is received, RE should be cleared to 0 before the end of bit 7. Data Transfer Operations SCI Initialization (Synchronous Mode): Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1. Figure 15.19 shows a sample SCI initialization flowchart. Page 656 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 1. Set the clock selection in SCSCR1. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Initialization Clear TE and RE bits in SCSCR1 to 0 2. Set the data transfer format in SCSMR1. 3. Write a value corresponding to the bit rate into SCBRR1. (Not necessary if an external clock is used.) Set RIE, TIE, TEIE, MPIE, CKE1 and CKE0 bits in SCSCR1 (leaving TE and RE bits cleared to 0) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set data transfer format in SCSMR1 Set value in SCBRR1 Wait 1-bit interval elapsed? No Yes Set TE and RE bits in SCSCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits End Figure 15.19 Sample SCI Initialization Flowchart R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 657 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Serial Data Transmission (Synchronous Mode): Figure 15.20 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Start of transmission Read TDRE flag in SCSSR1 TDRE = 1? No Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 All data transmitted? No Yes 2. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) Read TEND flag in SCSSR1 TEND = 1? No Yes Clear TE bit in SCSCR1 to 0 End Figure 15.20 Sample Serial Transmission Flowchart Page 658 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). 3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. After completion of serial transmission, the SCK pin is fixed high. Figure 15.21 shows an example of SCI operation in transmission. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 659 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Transfer direction Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request Data written to SCTDR1 and TDRE flag cleared to 0 in TXI interrupt handler TXI interrupt request TEI interrupt request One frame Figure 15.21 Example of SCI Transmit Operation Serial Data Reception (Synchronous Mode): Figure 15.22 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. Page 660 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Start of reception Read ORER flag in SCSSR1 Yes ORER = 1? No Error handling Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 End of reception 1. Receive error handling: If a receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. 2. SCI status check and receive data read: Read SCSSR1 and check that the RDRF flag is set to 1, then read the receive data in SCRDR1 and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, finish reading the RDRF flag, reading SCRDR1, and clearing the RDRF flag to 0, before the MSB (bit 7) of the current frame is received. (The RDRF flag is cleared automatically when the direct memory access controller (DMAC) is activated by a receive-data-full interrupt (RXI) request and the SCRDR1 value is read.) Figure 15.22 Sample Serial Reception Flowchart (1) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 661 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCSSR1 to 0 End Figure 15.22 Sample Serial Reception Flowchart (2) In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from SCRSR1 to SCRDR1. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If a receive error is detected in the error check, the operation is as shown in table 15.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. Also, as the RDRF flag is not set to 1 when receiving, the flag must be cleared to 0. 3. If the RIE bit in SCRSR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCRSR1 is set to 1 when the ORER flag changes to 1, a receive-error interrupt (ERI) request is generated. Figure 15.23 shows an example of SCI operation in reception. Page 662 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request Data read from SCRDR1 and RDRF flag cleared to 0 in RXI interrupt handler RXI interrupt request ERI interrupt request due to overrun error One frame Figure 15.23 Example of SCI Receive Operation Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.24 shows a sample flowchart for simultaneous serial transmit and receive operations. Use the following procedure for simultaneous serial data transmit and receive operations after enabling the SCI for transmission and reception. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 663 of 1128 Section 15 Serial Communication Interface (SCI) Start of transmission/reception Read TDRE flag in SCSSR1 No TDRE = 1? Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 SH7751 Group, SH7751R Group 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. 2. Receive error handling: If a receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. 3. SCI status check and receive data read: Read ORER flag in SCSSR1 Read SCSSR1 and check that the RDRF flag is set to 1, then read the receive data in SCRDR1 and clear the Yes ORER = 1? RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Error handling No Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data transferred? Yes Clear TE and RE bits in SCRSR1 to 0 End of transmission/reception 4. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, finish reading the RDRF flag, reading SCRDR1, and clearing the RDRF flag to 0, before the MSB (bit 7) of the current frame is received. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1 and clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the DMAC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1. Similarly, the RDRF flag is cleared automatically when the DMAC is activated by a receive-data-full interrupt (RXI) request and the SCRDR1 value is read.) Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1. Figure 15.24 Sample Flowchart for Serial Data Transmission and Reception Page 664 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 15.4 Section 15 Serial Communication Interface (SCI) SCI Interrupt Sources and DMAC The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCRSR1, and the EIO bit in SCSPTR1. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in the serial status register (SCSSR1) is set to 1, a TDR-empty request is generated separately from the interrupt request. A TDR-empty request can activate the direct memory access controller (DMAC) to perform data transfer. The TDRE flag is cleared to 0 automatically when a write to the transmit data register (SCTDR1) is performed by the DMAC. When the RDRF flag in SCSSR1 is set to 1, an RDR-full request is generated separately from the interrupt request. An RDR-full request can activate the DMAC to perform data transfer. The RDRF flag is cleared to 0 automatically when a receive data register (SCRDR1) read is performed by the DMAC. When the ORER, FER, or PER flag in SCSSR1 is set to 1, an ERI interrupt request is generated. The DMAC cannot be activated by an ERI interrupt request. When receive data processing is to be carried out by the DMAC and receive error handling is to be performed by means of an interrupt to the CPU, set the RIE bit to 1 and also set the EIO bit in SCSPTR1 to 1 so that an interrupt error occurs only for a receive error. If the EIO bit is cleared to 0, interrupts to the CPU will be generated even during normal data reception. When the TEND flag in SCSSR1 is set to 1, a TEI interrupt request is generated. The DMAC cannot be activated by a TEI interrupt request. A TXI interrupt indicates that transmit data can be written, and a TEI interrupt indicates that the transmit operation has ended. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 665 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Table 15.12 SCI Interrupt Sources Interrupt Source Description DMAC Activation Priority on Reset Release ERI Receive error (ORER, FER, or PER) Not possible High RXI Receive data register full (RDRF) Possible TXI Transmit data register empty (TDRE) Possible TEI Transmit end (TEND) Not possible Low See section 5, Exceptions, for the priority order and relation to non-SCI interrupts. 15.5 Usage Notes The following points should be noted when using the SCI. SCTDR1 Writing and the TDRE Flag: The TDRE flag in SCSSR1 is a status flag that indicates that transmit data has been transferred from SCTDR1 to SCTSR1. When the SCI transfers data from SCTDR1 to SCTSR1, the TDRE flag is set to 1. Data can be written to SCTDR1 regardless of the state of the TDRE flag. However, if new data is written to SCTDR1 when the TDRE flag is cleared to 0, the data stored in SCTDR1 will be lost since it has not yet been transferred to SCTSR1. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to SCTDR1. Simultaneous Multiple Receive Errors: If a number of receive errors occur at the same time, the state of the status flags in SCSSR1 is as shown in table 15.13. If there is an overrun error, data is not transferred from SCRSR1 to SCRDR1, and the receive data is lost. Page 666 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data SCSSR1 Status Flags Receive Errors RDRF ORER FER PER Receive Data Transfer SCRSR1 → SCRDR1 Overrun error 1 1 0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error + framing error 1 1 1 0 X Overrun error + parity error 1 1 0 1 X Framing error + parity error 0 0 1 1 O Overrun error + framing error + parity error 1 1 1 1 X Legend: O: Receive data is transferred from SCRSR1 to SCRDR1. X: Receive data is not transferred from SCRSR1 to SCRDR1. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that the SCI receiver continues to operate in the break state, so if the FER flag is cleared to 0 it will be set to 1 again. Sending a Break Signal: The input/output condition and level of the TxD pin are determined by bits SPB0IO and SPB0DT in the serial port register (SCSPTR1). This feature can be used to send a break signal. After the serial transmitter is initialized, the TxD pin function is not selected and the value of the SPB0DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB0IO and SPB0DT bits should therefore be set to 1 (designating output and high level) beforehand. To send a break signal during serial transmission, clear the SPB0DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of its current state, and the TxD pin becomes an output port outputting the value 0. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 667 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Handling of TEND Flag and TE Bit: The TEND flag is set to 1 when the stop bit of the final data segment is transmitted. If the TE bit is cleared immediately after confirming that the TEND flag was set, transmission may not complete properly because stop bit transmission processing is still underway. Therefore, wait at least 0.5 serial clock cycles (1.5 cycles if two stop bits are used) after confirming that the TEND flag was set before clearing the TE bit. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is set to 1. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: The SCI operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 15.25. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks Receive data (RxD) Start bit +7.5 clocks D0 D1 Synchronization sampling timing Data sampling timing Figure 15.25 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = (0.5 – Page 668 of 1128 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% ................ (1) 2N N R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group M: N: D: L: F: Section 15 Serial Communication Interface (SCI) Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 – 1/(2 × 16)) × 100% = 46.875% ............................................ (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. When Using the DMAC: When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 peripheral operating clock cycles after SCTDR1 is updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 cycles after SCTDR1 is updated. (See figure 15.26) SCK t TDRE TxD D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4. Figure 15.26 Example of Synchronous Transmission by DMAC When SCRDR1 is read by the DMAC, be sure to set the SCI receive-data-full interrupt (RXI) as the activation source with bits RS3 to RS0 in CHCR. When Using Synchronous External Clock Mode: • Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock SCK has changed from 0 to 1. • Only set both TE and RE to 1 when external clock SCK is 1. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 669 of 1128 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group • In reception, note that if RE is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input, RDRF will be set to 1 but copying to SCRDR1 will not be possible. When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero 1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDRF will be set to 1 but copying to SCRDR1 will not be possible. When Using DMAC: When using the DMAC for transmission/reception, make a setting to suppress output of RXI and TXI interrupt requests to the interrupt controller. Even if a setting is made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by the DMAC independently of the interrupt handling program. Page 670 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview This LSI is equipped with a single-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous serial communication. Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1.1 Features SCIF features are listed below. • Asynchronous serial communication Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 8 serial data transfer formats. ⎯ Data length: 7 or 8 bits ⎯ Stop bit length: 1 or 2 bits ⎯ Parity: Even/odd/none ⎯ Receive error detection: Parity, framing, and overrun errors ⎯ Break detection: If the receive data following that in which a framing error occurred is also at the space “0” level, and there is a frame error, a break is detected. When a framing error occurs, a break can also be detected by reading the RxD2 pin level directly from the serial port register (SCSPTR2). • Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and continuous serial data transmission and reception. • On-chip baud rate generator allows any bit rate to be selected. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 671 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group • Choice of serial clock source: internal clock from baud rate generator or external clock from SCK2 pin • Four interrupt sources There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error—that can issue requests independently. • The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt. • When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption. • Modem control functions (RTS2 and CTS2) are provided. • The amount of data in the transmit/receive FIFO registers, and the number of receive errors in the receive data in the receive FIFO register, can be ascertained. • A timeout error (DR) can be detected during reception. Page 672 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 16.1.2 Section 16 Serial Communication Interface with FIFO (SCIF) Block Diagram Bus interface Figure 16.1 shows a block diagram of the SCIF. Module data bus RxD2 SCFRDR2 (16-stage) SCFTDR2 (16-stage) SCRSR2 SCTSR2 SCSMR2 SCLSR2 SCFDR2 SCFCR2 SCFSR2 SCSCR2 SCSPTR2 SCBRR2 Pck Baud rate generator Parity generation Pck/4 Pck/16 Transmission/ reception control TxD2 Internal data bus Pck/64 Clock Parity check External clock SCK2 TXI RXI ERI BRI CTS2 RTS2 SCIF Legend: SCRSR2: SCFRDR2: SCTSR2: SCFTDR2: SCSMR2: SCSCR2: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register SCFSR2: SCBRR2: SCSPTR2: SCFCR2: SCFDR2: SCLSR2: Serial status register Bit rate register Serial port register FIFO control register FIFO data count register Line status register Figure 16.1 Block Diagram of SCIF R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 673 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) 16.1.3 SH7751 Group, SH7751R Group Pin Configuration Table 16.1 shows the SCIF pin configuration. Table 16.1 SCIF Pins Pin Name Abbreviation I/O Function Serial clock pin MD0/SCK2 I/O Clock input/output Receive data pin MD2/RxD2 Input Receive data input Transmit data pin MD1/TxD2 Output Transmit data output Modem control pin MD7/CTS2 I/O Transmission enabled Modem control pin MD8/RTS2 I/O Transmission request Note: These pins function as the MD0, MD1, MD2, MD7, and MD8 mode input pins after a poweron reset. These pins are made to function as serial pins by performing SCIF operation settings with the TE, RE, CKE1, and CKE0 bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF's SCSPTR2 register. 16.1.4 Register Configuration The SCIF has the internal registers shown in table 16.2. These registers are used to specify the data format and bit rate, and to perform transmitter/receiver control. Table 16.2 SCIF Registers Name Abbreviation R/W Initial Value P4 Address Serial mode register SCSMR2 R/W H'0000 H'FFE80000 H'IFE80000 16 Bit rate register SCBRR2 R/W H'FF H'FFE80004 H'IFE80004 8 Serial control register SCSCR2 R/W H'0000 H'FFE80008 H'IFE80008 16 Transmit FIFO data register SCFTDR2 W Serial status register SCFSR2 Area 7 Address Access Size Undefined H'FFE8000C H'IFE8000C 8 R/(W)*1 H'0060 H'FFE80010 H'IFE80010 16 Receive FIFO data register SCFRDR2 R Undefined H'FFE80014 H'IFE80014 8 FIFO control register H'0000 SCFCR2 R/W FIFO data count register SCFDR2 R Serial port register SCSPTR2 R/W Line status register SCLSR2 H'FFE80018 H'IFE80018 16 H'0000 H'FFE8001C H'IFE8001C 16 H'0000*2 H'FFE80020 H'IFE80020 16 R/(W)*3 H'0000 H'FFE80024 H'IFE80024 16 Notes: 1. Only 0 can be written, to clear flags. Bits 15 to 8, 3, and 2 are read-only, and cannot be modified. 2. The value of bits 6, 4, 2, and 0 is undefined. 3. Only 0 can be written, to clear flags. Bits 15 to 1 are read-only, and cannot be modified. Page 674 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 16.2 Register Descriptions 16.2.1 Receive Shift Register (SCRSR2) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCRSR2 is the register used to receive serial data. The SCIF sets serial data input from the RxD2 pin in SCRSR2 in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to the receive FIFO register, SCFRDR2, automatically. SCRSR2 cannot be directly read or written to by the CPU. 16.2.2 Receive FIFO Data Register (SCFRDR2) Bit: 7 6 5 4 3 2 1 0 R/W: R R R R R R R R SCFRDR2 is a 16-stage FIFO register that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR2 to SCFRDR2 where it is stored, and completes the receive operation. SCRSR2 is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO register is full (16 data bytes). SCFRDR2 is a read-only register, and cannot be written to by the CPU. If a read is performed when there is no receive data in the receive FIFO register, an undefined value will be returned. When the receive FIFO register is full of receive data, subsequent serial data is lost. The contents of SCFRDR2 are undefined after a power-on reset or manual reset. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 675 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.3 SH7751 Group, SH7751R Group Transmit Shift Register (SCTSR2) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCTSR2 is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR2 to SCTSR2, then sends the data to the TxD2 pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR2 to SCTSR2, and transmission started, automatically. SCTSR2 cannot be directly read or written to by the CPU. 16.2.4 Transmit FIFO Data Register (SCFTDR2) Bit: 7 6 5 4 3 2 1 0 R/W: W W W W W W W W SCFTDR2 is a 16-stage FIFO register that stores 8-bit data for serial transmission. If SCTSR2 is empty when transmit data has been written to SCFTDR2, the SCIF transfers the transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission. SCFTDR2 is a write-only register, and cannot be read by the CPU. The next data cannot be written when SCFTDR2 is filled with 16 bytes of transmit data. Data written in this case is ignored. The contents of SCFTDR2 are undefined after a power-on reset or manual reset. Page 676 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 16.2.5 Section 16 Serial Communication Interface with FIFO (SCIF) Serial Mode Register (SCSMR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — CHR PE O/E STOP — CKS1 CKS0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R R/W R/W SCSMR2 is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate generator clock source. SCSMR2 can be read or written to by the CPU at all times. SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0. Bit 6—Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length. Bit 6: CHR Description 0 8-bit data 1 7-bit data* Note: * (Initial value) When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted. Bit 5—Parity Enable (PE): Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. Bit 5: PE Description 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * (Initial value) When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 677 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking. The O/E bit setting is invalid when parity addition and checking is disabled. Bit 4: O/E Description 0 Even parity*1 1 Odd parity*2 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length. Bit 3: STOP Description 0 1 stop bit*1 1 (Initial value) 2 2 stop bits* Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Reserved: This bit is always read as 0, and should only be written with 0. Page 678 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. The clock source can be selected from Pck, Pck/4, Pck/16, and Pck/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.8, Bit Rate Register (SCBRR2). Bit 1: CKS1 0 1 Bit 0: CKS0 Description 0 Pck clock 1 Pck/4 clock 0 Pck/16 clock 1 Pck/64 clock (Initial value) Note: Pck: Peripheral clock 16.2.6 Serial Control Register (SCSCR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 TIE RIE TE RE REIE — CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R/W R/W Initial value: R/W: The SCSCR2 register performs enabling or disabling of SCIF transfer operations, serial clock output, and interrupt requests, and selection of the serial clock source. SCSCR2 can be read or written to by the CPU at all times. SCSCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 8, and 2—Reserved: These bits are always read as 0, and should only be written with 0. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 679 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR2 to SCTSR2, the number of data bytes in the transmit FIFO register falls to or below the transmit trigger set number, and the TDFE flag in the serial status register (SCFSR2) is set to 1. Bit 7: TIE Description 0 Transmit-FIFO-data-empty interrupt (TXI) request disabled* 1 Note: (Initial value) Transmit-FIFO-data-empty interrupt (TXI) request enabled * TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to SCFTDR2 after reading 1 from the TDFE flag, then clearing it to 0, or by clearing the TIE bit to 0. Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR2 is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR2 is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1. Bit 6: RIE Description 0 Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request disabled* (Initial value) 1 Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request enabled Note: * An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF. Bit 5: TE Description 0 Transmission disabled 1 Transmission enabled* Note: * (Initial value) Serial transmission is started when transmit data is written to SCFTDR2 in this state. Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1. Page 680 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF. Bit 4: RE Description 0 Reception disabled*1 1 Reception enabled* (Initial value) 2 Notes: 1. Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their states. 2. Serial transmission is started when a start bit is detected in this state. Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be made, the reception format decided, and the receive FIFO reset, before the RE bit is set to 1. Bit 3—Receive Error Interrupt Enable (REIE): Enables or disables generation of receive-error interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the RIE bit is 0. Bit 3: REIE Description 0 Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled* (Initial value) 1 Note: Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled * Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will be generated even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is to be notified of ERI and BRI interrupt requests. Bits 1 and 0—Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCIF clock source and enable/disable clock output from the SCK2 pin. The combination of CKE1 and CKE0 determine whether the SCK2 pin functions as serial clock output pin or the serial clock input pin. Note, however, that the setting of the CKE0 bit is valid only when CKE1 = 0 (internal clock operation). When CKE1 = 1 (external clock), CKE0 is ignored. Also, be sure to set CKE1 and CKE0 prior to determining the SCIF operating mode with SCSMR2. Bit 1: CKE1 Bit 0: CKE0 Description 0 0 Internal clock/SCK pin functions as port (Initial value) 1 Internal clock/SCK2 pin functions as clock output*1 0 External clock/SCK2 pin functions as clock input*2 1 External clock/SCK2 pin functions as clock input*2 1 Notes: 1. Outputs a clock with a frequency 16 times the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 681 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.7 SH7751 Group, SH7751R Group Serial Status Register (SCFSR2) Bit: 15 14 13 12 11 10 9 8 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ER TEND TDFE BRK FER PER RDF DR 0 1 1 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R R R/(W)* R/(W)* Initial value: R/W: Note: * Only 0 can be written, to clear the flag. SCFSR2 is a 16-bit register. The lower 8 bits consist of status flags that indicate the operating status of the SCIF, and the upper 8 bits indicate the number of receive errors in the data in the receive FIFO register. SCFSR2 can be read or written to by the CPU at all times. However, 1 cannot be written to flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified. SCFSR2 is initialized to H'0060 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 12—Number of Parity Errors (PER3–PER0): These bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR2. After the ER bit in SCFSR2 is set, the value indicated by bits 15 to 12 is the number of data bytes in which a parity error occurred. If all 16 bytes of receive data in SCFRDR2 have parity errors, the value indicated by bits PER3 to PER0 will be 0. Bits 11 to 8—Number of Framing Errors (FER3–FER0): These bits indicate the number of data bytes in which a framing error occurred in the receive data stored in SCFRDR2. After the ER bit in SCFSR2 is set, the value indicated by bits 11 to 8 is the number of data bytes in which a framing error occurred. Page 682 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) If all 16 bytes of receive data in SCFRDR2 have framing errors, the value indicated by bits FER3 to FER0 will be 0. Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during reception.* Note: * The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR2, and reception continues. The FER and PER bits in SCFSR2 can be used to determine whether there is a receive error in the data read from SCFRDR2. Bit 7: ER Description 0 No framing error or parity error occurred during reception (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When 0 is written to ER after reading ER = 1 A framing error or parity error occurred during reception [Setting conditions] Note: * • When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0* • When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR2 In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 683 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR2 when the last bit of the transmit character is sent, and transmission has been ended. Bit 6: TEND Description 0 Transmission is in progress [Clearing conditions] 1 • When transmit data is written to SCFTDR2, and 0 is written to TEND after reading TEND = 1 • When data is written to SCFTDR2 by the DMAC Transmission has been ended (Initial value) [Setting conditions] Page 684 of 1128 • Power-on reset or manual reset • When the TE bit in SCSCR2 is 0 • When there is no transmit data in SCFTDR2 on transmission of the last bit of a 1-byte serial transmit character R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and new transmit data can be written to SCFTDR2. Bit 5: TDFE Description 0 A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR2 [Clearing conditions] 1 • When transmit data exceeding the transmit trigger set number is written to SCFTDR2 after reading TDFE = 1, and 0 is written to TDFE • When transmit data exceeding the transmit trigger set number is written to SCFTDR2 by the DMAC The number of transmit data bytes in SCFTDR2 does not exceed the transmit trigger set number (Initial value) [Setting conditions] Note: * • Power-on reset or manual reset • When the number of SCFTDR2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation* As SCFTDR2 is a 16-byte FIFO register, the maximum number of bytes that can be written when TDFE = 1 is 16 - (transmit trigger set number). Data written in excess of this will be ignored. The number of data bytes in SCFTDR2 is indicated by the upper bits of SCFDR2. Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected. Bit 4: BRK 0 Description A break signal has not been received (Initial value) [Clearing conditions] • Power-on reset or manual reset • When 0 is written to BRK after reading BRK = 1 1 A break signal has been received* [Setting condition] When data with a framing error is received, followed by the space “0” level (low level ) for at least one frame length Note: * When a break is detected, the receive data (H'00) following detection is not transferred to SCFRDR2. When the break ends and the receive signal returns to mark “1”, receive data transfer is resumed. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 685 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 3—Framing Error (FER): Indicates whether or not a framing error has been found in the data that is to be read from the receive FIFO data register (SCFRDR2). Bit 3: FER Description 0 There is no framing error in the receive data that is to be read from SCFRDR2 (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When there is no framing error in the data that is to be read next from SCFRDR2 There is a framing error in the receive data that is to be read from SCFRDR2 [Setting condition] When there is a framing error in the data that is to be read next from SCFRDR2 Bit 2—Parity Error (PER): Indicates whether or not a parity error has been found in the data that is to be read from the receive FIFO data register (SCFRDR2). Bit 2: PER Description 0 There is no parity error in the receive data that is to be read from SCFRDR2 (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When there is no parity error in the data that is to be read next from SCFRDR2 There is a parity error in the receive data that is to be read from SCFRDR2 [Setting condition] When there is a parity error in the data that is to be read next from SCFRDR2 Page 686 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 1—Receive FIFO Data Full (RDF): Indicates that the received data has been transferred from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2). Bit 1: RDF Description 0 The number of receive data bytes in SCFRDR2 is less than the receive trigger set number (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When SCFRDR2 is read until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number after reading RDF = 1, and 0 is written to RDF • When SCFRDR2 is read by the DMAC until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number The number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger set number [Setting condition] When SCFRDR2 contains at least the receive trigger set number of receive data bytes* Note: * SCFRDR2 is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in SCFRDR2 is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCFRDR2 is indicated by the lower bits of SCFDR2. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 687 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop bit of the last data received. Bit 0: DR Description 0 Reception is in progress or has ended normally and there is no receive data left in SCFRDR2 (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When all the receive data in SCFRDR2 has been read after reading DR = 1, and 0 is written to DR • When all the receive data in SCFRDR2 has been read by the DMAC No further receive data has arrived [Setting condition] When SCFRDR2 contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received* Note: 16.2.8 * Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. etu: Elementary time unit (time for transfer of 1 bit) Bit Rate Register (SCBRR2) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: SCBRR2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR2. SCBRR2 can be read or written to by the CPU at all times. SCBRR2 is initialized to H'FF by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Page 688 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) The SCBRR2 setting is found from the following equation. Asynchronous mode: N= Pck 64 × 22n – 1 × B × 106 – 1 Where B: Bit rate (bits/s) N: SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255) Pck: Peripheral module operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR2 Setting n Clock CKS1 CKS0 0 Pck 0 0 1 Pck/4 0 1 2 Pck/16 1 0 3 Pck/64 1 1 The bit rate error in asynchronous mode is found from the following equation: Error (%) = 16.2.9 Pck × 106 (N + 1) × B × 64 × 22n – 1 – 1 × 100 FIFO Control Register (SCFCR2) Bit: 15 14 13 12 11 — — — — — 10 9 8 RSTRG2 RSTRG1 RSTRG0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 689 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR2 can be read or written to by the CPU at all times. SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 11—Reserved: These bits are always read as 0, and should only be written with 0. Bits 10, 9 and 8—RTS2 Output Active Trigger (RSTRG2, RSTG1, and RSTG0): These bits output the high level to the RTS2 signal when the number of received data stored in the receive FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the table below. Bit 10: RSTRG2 Bit 9: RSTRG1 Bit 8: RSTRG0 RTS2 Output Active Trigger 0 0 0 15 1 1 0 4 1 6 0 8 1 10 0 12 1 14 1 1 0 1 (Initial value) Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status register (SCFSR2). The RDF flag is set when the number of receive data bytes in SCFRDR2 is equal to or greater than the trigger set number shown in the following table. Bit 7: RTRG1 Bit 6: RTRG0 Receive Trigger Number 0 0 1 1 4 0 8 1 14 1 Page 690 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the following table. Bit 5: TTRG1 Bit 4: TTRG0 Transmit Trigger Number 0 0 8 (8) 1 4 (12) 0 2 (14) 1 1 (15) 1 (Initial value) Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set. Bit 3—Modem Control Enable (MCE): Enables the CTS2 and RTS2 modem control signals. Bit 3: MCE Description 0 Modem signals disabled* 1 Modem signals enabled Note: * (Initial value) CTS2 is fixed at active-0 regardless of the input value, and RTS2 output is also fixed at 0. Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. Bit 2: TFRST Description 0 Reset operation disabled* 1 Reset operation enabled Note: * (Initial value) A reset operation is performed in the event of a power-on reset or manual reset. Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive FIFO data register and resets it to the empty state. Bit 1: RFRST Description 0 Reset operation disabled* 1 Reset operation enabled Note: * (Initial value) A reset operation is performed in the event of a power-on reset or manual reset. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 691 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive input pin (RxD2), and the RTS2 pin and CTS2 pin, enabling loopback testing. Bit 0: LOOP Description 0 Loopback test disabled 1 Loopback test enabled (Initial value) 16.2.10 FIFO Data Count Register (SCFDR2) SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and SCFRDR2. The upper 8 bits show the number of transmit data bytes in SCFTDR2, and the lower 8 bits show the number of receive data bytes in SCFRDR2. SCFDR2 can be read by the CPU at all times. Bit: 15 14 13 12 11 10 9 8 — — — T4 T3 T2 T1 T0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R These bits show the number of untransmitted data bytes in SCFTDR2. A value of H'00 indicates that there is no transmit data, and a value of H'10 indicates that SCFTDR2 is full of transmit data. Bit: 7 6 5 4 3 2 1 0 — — — R4 R3 R2 R1 R0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R These bits show the number of receive data bytes in SCFRDR2. A value of H'00 indicates that there is no receive data, and a value of H'10 indicates that SCFRDR2 is full of receive data. Page 692 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.11 Serial Port Register (SCSPTR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT 0 — 0 — 0 — 0 — R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: SPB2IO SPB2DT SCSPTR2 is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface with FIFO (SCIF) pins. Input data can be read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. Data can be read from, and output data written to, the SCK2 pin by means of bits 3 and 2. Data can be read from, and output data written to, the CTS2 pin by means of bits 5 and 4. Data can be read from, and output data written to, the RTS2 pin by means of bits 6 and 7. SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, 2, and 0 is undefined. SCSPTR2 is not initialized in standby mode or in the module standby state. Bits 15 to 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Serial Port RTS Port I/O (RTSIO): Specifies the serial port RTS2 pin input/output condition. When the RTS2 pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 7: RTSIO Description 0 RTSDT bit value is not output to RTS2 pin 1 RTSDT bit value is output to RTS2 pin R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 (Initial value) Page 693 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port RTS2 pin input/output data. Input or output is specified by the RTSIO bit (see the description of bit 7, RTSIO, for details). In output mode, the RTSDT bit value is output to the RTS2 pin. The RTS2 pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 6: RTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 5—Serial Port CTS Port I/O (CTSIO): Specifies the serial port CTS2 pin input/output condition. When the CTS2 pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 5: CTSIO Description 0 CTSDT bit value is not output to CTS2 pin 1 CTSDT bit value is output to CTS2 pin (Initial value) Bit 4—Serial Port CTS Port Data (CTSDT): Specifies the serial port CTS2 pin input/output data. Input or output is specified by the CTSIO bit (see the description of bit 5, CTSIO, for details). In output mode, the CTSDT bit value is output to the CTS2 pin. The CTS2 pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 4: CTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 3—Serial Port Clock Port I/O (SCKIO): Sets the I/O for the SCK2 pin serial port. To actually set the SCK2 pin as the port output pin and output the value set in the SCKDT bit, set the CKE1 and CKE0 bits of the SCSCR2 register to 0. Bit 3: SCKIO Description 0 Shows that the value of the SCKDT bit is not output to the SCK2 pin (Initial value) 1 Shows that the value of the SCKDT bit is output to the SCK2 pin. Page 694 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 2—Serial Port Clock Port Data (SCKDT): Specifies the I/O data for the SCK2 pin serial port. The SCKIO bit specified input or output. (See bit 3: SCKIO, for details.) When set for output, the value of the SCKDT bit is output to the SCK2 pin. Regardless of the value of the SCKIO bit, the value of the SCK2 pin is fetched from the SCKDT bit. The initial value after a power-on reset or manual reset is undefined. Bit 2: SCKDT Description 0 Shows I/O data level is LOW 1 Shows I/O data level is HIGH Bit 1—Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0. Bit 1: SPB2IO Description 0 SPB2DT bit value is not output to the TxD2 pin 1 SPB2DT bit value is output to the TxD2 pin (Initial value) Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB2DT Description 0 Input/output data is low-level 1 Input/output data is high-level R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 695 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group SCIF I/O port block diagrams are shown in figures 16.2 to 16.6. Reset R D7 Q D RTSIO C Internal data bus SPTRW Reset MD8/RTS2 R D6 Q D RTSDT C SPTRW SCIF Modem control enable signal* RTS2 signal Mode setting register SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The RTS2 pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.2 MD8/RTS2 Pin Page 696 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Reset R Q D CTSIO C D5 Internal data bus SPTRW Reset MD7/CTS2 R Q D CTSDT C D4 SCIF SPTRW Mode setting register CTS2 signal Modem control enable signal* SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.3 MD7/CTS2 Pin R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 697 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Reset R Q D SPB2IO C D1 Internal data bus SPTRW Reset MD1/TxD2 R Q D SPB2DT C D0 SPTRW Mode setting register SCIF Transmit enable signal Serial transmit data Legend: SPTRW: Write to SPTR Figure 16.4 MD1/TxD2 Pin SCIF MD2/RxD2 Serial receive data Mode setting register D0 Internal data bus SPTRR Legend: SPTRR: Read SPTR Figure 16.5 MD2/RxD2 Pin Page 698 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Reset R Q D SCKIO C Internal data bus SPTRW Reset MD0/SCK2 Q R D SCKDT C SPTRW SCIF Clock output enable signal Serial clock output signal Mode setting register * Serial clock input signal Clock input enable signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK2 pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR2. Figure 16.6 MD0/SCK2 Pin R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 699 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group 16.2.12 Line Status Register (SCLSR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — ORER Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R (R/W)* Note: * Only 0 can be written, to clear the flag. Bits 15 to 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 0: ORER Description 0 Reception in progress, or reception has ended normally*1 (Initial value) [Clearing conditions] 1 • Power-on reset or manual reset • When 0 is written to ORER after reading ORER = 1 An overrun error occurred during reception*2 [Setting condition] When the next serial reception is completed while the receive FIFO is full Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0. 2. The receive data prior to the overrun error is retained in SCFRDR2, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. Page 700 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 16.3 Operation 16.3.1 Overview Section 16 Serial Communication Interface with FIFO (SCIF) The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character. See section 15.3.2, Operation in Asynchronous Mode, for details. Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed. RTS2 and CTS2 signals are also provided as modem control signals. The transmission format is selected using the serial mode register (SCSMR2), as shown in table 16.3. The SCIF clock source is determined by the CKE1 bit in the serial control register (SCSCR2), as shown in table 16.4. • Data length: Choice of 7 or 8 bits • Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) • Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receivedata-ready state, and breaks, during reception • Indication of the number of data bytes stored in the transmit and receive FIFO registers • Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock, and a clock with a frequency of 16 times the bit rate must be output When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 701 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection SCSMR2 Settings SCIF Transfer Format Bit 6: CHR Bit 5: PE Bit 3: STOP Mode Data Length Multiprocessor Parity Bit Bit 0 0 0 Asynchronous mode 8-bit data No No 1 1 Yes 0 0 1 bit 2 bits 7-bit data 0 No 1 1 1 bit 2 bits 1 1 Stop Bit Length 1 bit 2 bits Yes 0 1 1 bit 2 bits Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection SCSCR2 Setting SCIF Transmit/Receive Clock Bit 1: CKE1 Bit 0: CKE0 Mode Clock Source SCK2 Pin Function 0 Internal SCIF does not use SCK2 pin 0 Asynchronous mode 1 1 0 1 Page 702 of 1128 Output clock with frequency of 16 times the bit rate External Inputs clock with frequency of 16 times the bit rate R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 16.3.2 Section 16 Serial Communication Interface with FIFO (SCIF) Serial Operation Data Transfer Format Table 16.5 shows the data transfer formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR2 settings. Table 16.5 Serial Transfer Formats SCSMR2 Settings Serial Transfer Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 S 8-bit data STOP 0 0 1 S 8-bit data STOP STOP 0 1 0 S 8-bit data P STOP 0 1 1 S 8-bit data P STOP STOP 1 0 0 S 7-bit data STOP 1 0 1 S 7-bit data STOP STOP 1 1 0 S 7-bit data P STOP 1 1 1 S 7-bit data P STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 703 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK2 pin can be selected as the SCIF's serial clock, according to the setting of the CKE1 bit in SCSCR2. For details of SCIF clock source selection, see table 16.4. When an external clock is input at the SCK2 pin, the clock frequency should be 16 times the bit rate used. When operating using the internal clock, the clock can be output via the SCK2 pin. The frequency of this clock is 16 times the bit rate. Data Transfer Operations SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR2 to 0, then initialize the SCIF as described below. When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR2 is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR2, SCFTDR2, or SCFRDR2. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in SCFSR2 has been set. TEND can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after the clearance. Before setting TE again to start transmission, the TFRST bit in SCFCR2 should first be set to 1 to reset SCFTDR2. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Figure 16.7 shows a sample SCIF initialization flowchart. Page 704 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 1. Set the clock selection in SCSCR2. Initialization Be sure to clear bits RIE and TIE, and bits TE and RE, to 0. Clear TE and RE bits in SCSCR2 to 0 2. Set the data transfer format in SCSMR2. 3. Write a value corresponding to the bit rate into SCBRR2. (Not necessary if an external clock is used.) Set TFRST and RFRST bits in SCFCR2 to 1 Set CKE1 and CKE0 bits in SCSCR2 (leaving TE and RE bits cleared to 0) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR2 to 1. Also set the RIE, REIE, and TIE bits. Set data transfer format in SCSMR2 Setting the TE and RE bits enables the TxD2 and RxD2 pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. Set value in SCBRR2 Wait 1-bit interval elapsed? No Yes Set RTRG1–0, TTRG1–0, and MCE bits in SCFCR2 Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR2 to 1, and set RIE, TIE, and REIE bits End Figure 16.7 Sample SCIF Initialization Flowchart R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 705 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Serial Data Transmission: Figure 16.8 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. SCIF status check and transmit data write: Start of transmission Read TDFE flag in SCFSR2 TDFE = 1? No The number of transmit data bytes that can be written is 16− (transmit trigger set number). Yes Write transmit data (16 − transmit trigger set number) to SCFTDR2, read 1 from TDFE flag and TEND flag in SCFSR2, then clear to 0 All data transmitted? 2. Serial transmission continuation procedure: No Yes No Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1 To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR2, and then clear the TDFE flag to 0. 3. Break output at the end of serial transmission: Read TEND flag in SCFSR2 TEND = 1? Read SCFSR2 and check that the TDFE flag is set to 1, then write transmit data to SCFTDR2, read 1 from the TDFE and TEND flags, then clear these flags to 0. No To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR2, then clear the TE bit in SCSCR2 to 0. In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR2 indicated by the upper 8 bits of SCFDR2. Clear TE bit in SCSCR2 to 0 End of transmission Figure 16.8 Sample Serial Transmission Flowchart Page 706 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR2, the SCIF transfers the data from SCFTDR2 to SCTSR2 and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR2) is set to 1 before writing transmit data to SCFTDR2. The number of data bytes that can be written is at least 16− (transmit trigger set number). 2. When data is transferred from SCFTDR2 to SCTSR2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR2. When the number of transmit data bytes in SCFTDR2 falls to or below the transmit trigger number set in the FIFO control register (SCFCR2), the TDFE flag is set. If the TIE bit in SCSCR2 is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD2 pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR2 transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR2 to SCTSR2, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. Figure 16.9 shows an example of the operation for transmission in asynchronous mode. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 707 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) Start bit 1 Serial data Data 0 D0 D1 SH7751 Group, SH7751R Group Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 Idle state (mark state) 1 TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR2 and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame Figure 16.9 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS2 input value. When CTS2 is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS2 is set to 0, the next transmit data is output starting from the start bit. Figure 16.10 shows an example of the operation when modem control is used. Start bit Serial data TxD2 0 Parity Stop bit bit D0 D1 D7 0/1 1 Start bit 0 D0 D1 D7 0/1 CTS2 Drive high before stop bit Figure 16.10 Example of Operation Using Modem Control (CTS2) Page 708 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Reception: Figure 16.11 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception Read ER, DR, BRK flags in SCFSR2 and ORER flag in SCLSR2 ER or DR or BRK or ORER = 1? No Read RDF flag in SCFSR2 No RDF = 1? Yes Read receive data in SCFRDR2, and clear RDF flag in SCFSR2 to 0 No All data received? Yes Clear RE bit in SCSCR2 to 0 End of reception Yes Error handling 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR2, and the ORER flag in SCLSR2, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD2 pin. 2. SCIF status check and receive data read : Read SCFSR2 and check that RDF = 1, then read the receive data in SCFRDR2, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR2, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR2 can be ascertained by reading the lower bits of SCFDR2. Figure 16.11 Sample Serial Reception Flowchart (1) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 709 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling No ER = 1? SH7751 Group, SH7751R Group 1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in SCFSR2. 2. When a break signal is received, receive data is not transferred to SCFRDR2 while the BRK flag is set. However, note that the last data in SCFRDR2 is H'00 (the break data in which a framing error occurred is stored). Yes Receive error handling No BRK = 1? Yes Break handling No DR = 1? Yes Read receive data in SCFRDR2 Clear DR, ER, BRK flags in SCFSR2, and ORER flag in SCLSR2, to 0 End Figure 16.11 Sample Serial Reception Flowchart (2) Page 710 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR2 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. b. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR2) to SCFRDR2. c. Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun error has occurred. d. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the b, c, and d checks are passed, the receive data is stored in SCFRDR2. Note: Reception continues when parity error, framing error occurs. 4. If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or REIE bit in SCSCR2 is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or REIE bit in SCSCR2 is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 711 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Figure 16.12 shows an example of the operation for reception. 1 Serial data Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 Parity Stop bit bit D1 D7 0/1 0 0/1 RDF FER RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error Figure 16.12 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the RTS2 signal is output when SCFRDR2 is empty. When RTS2 is 0, reception is possible. When RTS2 is 1, this indicates that SCFRDR2 contains a number of data bytes equal to or greater than the RTS2 output active trigger set number. The RTS2 output active trigger value is specified by bits 10 to 8 in the FIFO control register (SCFCR2), described in section 16.2.9, FIFO Control Register (SCFCR2). RTS2 also goes to 1 when bit 4 (RE) in SCSCR2 is 0. Figure 16.13 shows an example of the operation when modem control is used. Parity Stop bit bit Start bit Serial data RxD2 0 D0 D1 D2 D7 0/1 1 Start bit 0 RTS2 Figure 16.13 Example of Operation Using Modem Control (RTS2) Page 712 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 16.4 Section 16 Serial Communication Interface with FIFO (SCIF) SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receiveerror interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 16.6 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR2. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When transmission/reception is carried out using the DMAC, output of interrupt requests to the interrupt controller can be inhibited by clearing the RIE bit in SCSCR2 to 0. By setting the REIE bit to 1 while the RIE bit is cleared to 0, it is possible to output ERI and BRI interrupt requests, but not RXI interrupt requests. When the TDFE flag in the serial status register (SCFSR2) is set to 1, a transmit-FIFO-data-empty request is generated separately from the interrupt request. A transmit-FIFO-data-empty request can activate the DMAC to perform data transfer. When the RDF flag or DR flag in SCFSR2 is set to 1, a receive-FIFO-data-full request is generated separately from the interrupt request. A receive-FIFO-data-full request can activate the DMAC to perform data transfer. When using the DMAC for transmission/reception, set and enable the DMAC before making the SCIF settings. See section 14, Direct Memory Access Controller (DMAC), for details of the DMAC setting procedure. When the BRK flag in SCFSR2 or the ORER flag in the line status register (SCLSR2) is set to 1, a BRI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR2. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 713 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Table 16.6 SCIF Interrupt Sources Interrupt Source Description DMAC Activation Priority on Reset Release ERI Interrupt initiated by receive error flag (ER) Not possible High RXI Interrupt initiated by receive FIFO data full flag (RDF) or receive data ready flag (DR) Possible BRI Interrupt initiated by break flag (BRK) or overrun Not possible error flag (ORER) TXI Interrupt initiated by transmit FIFO data empty flag (TDFE) Possible Low See section 5, Exceptions, for priorities and the relationship with non-SCIF interrupts. 16.5 Usage Notes Note the following when using the SCIF. SCFTDR2 Writing and the TDFE Flag: The TDFE flag in the serial status register (SCFSR2) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR2) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR2 can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR2 is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR2 contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR2 can be found from the upper 8 bits of the FIFO data count register (SCFDR2). SCFRDR2 Reading and the RDF Flag: The RDF flag in the serial status register (SCFSR2) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR2) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR2, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR2 is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read. Page 714 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the FIFO data count register (SCFDR2). Break Detection and Processing: Break signals can be detected by reading the RxD2 pin directly when a framing error (FER) is detected. In the break state the input from the RxD2 pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Although the SCIF stops transferring receive data to SCFRDR2 after receiving a break, the receive operation continues. Sending a Break Signal: The input/output condition and level of the TxD2 pin are determined by bits SPB2IO and SPB2DT in the serial port register (SCSPTR2). This feature can be used to send a break signal. After the serial transmitter is initialized, the TxD2 pin function is not selected and the value of the SPB2DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level) beforehand. To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized, regardless of its current state, and 0 is output from the TxD2 pin. Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.14. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 715 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks Receive data (RxD2) Start bit +7.5 clocks D0 D1 Synchronization sampling timing Data sampling timing Figure 16.14 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = (0.5 – 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% ...................... (1) 2N N Legend: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ............................................... (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Page 716 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) When Using the DMAC: When using the DMAC for transmission/reception, inhibit output of RXI and TXI interrupt requests to the interrupt controller. If interrupt request output is enabled, interrupt requests to the interrupt controller will be cleared by the DMAC without regard to the interrupt handler. Serial Ports: Note that, when the SCIF pin value is read using a serial port, the value read will be the value two peripheral clock cycles earlier. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 717 of 1128 Section 16 Serial Communication Interface with FIFO (SCIF) Page 718 of 1128 SH7751 Group, SH7751R Group R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface Section 17 Smart Card Interface 17.1 Overview The serial communication interface (SCI) supports a subset of the ISO/IEC 7816-3 (identification cards) standard as an extended function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 17.1.1 Features Features of the smart card interface are listed below. • Asynchronous mode ⎯ Data length: 8 bits ⎯ Parity bit generation and checking ⎯ Transmission of error signal (parity error) in receive mode ⎯ Error signal detection and automatic data retransmission in transmit mode ⎯ Direct convention and inverse convention both supported • On-chip baud rate generator allows any bit rate to be selected • Three interrupt sources There are three interrupt sources—transmit-data-empty, receive-data-full, and transmit/receive error—that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute data transfer. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 719 of 1128 Section 17 Smart Card Interface 17.1.2 SH7751 Group, SH7751R Group Block Diagram Bus interface Figure 17.1 shows a block diagram of the smart card interface. Module data bus RxD SCRDR1 SCTDR1 SCRSR1 SCTSR1 SCSCMR1 SCSSR1 SCSCR1 SCSMR1 SCSPTR1 SCBRR1 Pck Baud rate generator Parity generation Pck/4 Pck/16 Transmission/ reception control TxD Internal data bus Pck/64 Clock Parity check External clock SCK TXI RXI ERI SCI Legend: SCSCMR1: SCRSR1: SCRDR1: SCTSR1: SCTDR1: SCSMR1: SCSCR1: SCSSR1: SCBRR1: SCSPTR1: Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Figure 17.1 Block Diagram of Smart Card Interface Page 720 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 17.1.3 Section 17 Smart Card Interface Pin Configuration Table 17.1 shows the smart card interface pin configuration. Table 17.1 Smart Card Interface Pins Pin Name Abbreviation Serial clock pin Receive data pin Transmit data pin 17.1.4 I/O Function SCK I/O Clock input/output RxD Input Receive data input TxD Output Transmit data output Register Configuration The smart card interface has the internal registers shown in table 17.2. Details of the SCBRR1, SCTDR1, SCRDR1, and SCSPTR1 registers are the same as for the normal SCI function: see the register descriptions in section 15, Serial Communication Interface (SCI). With the exception of the serial port register, the smart card interface registers are initialized in standby mode and in the module standby state as well as by a power-on reset or manual reset. When recovering from standby mode or the module standby state, the registers must be set again. Table 17.2 Smart Card Interface Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Acces s Size Serial mode register SCSMR1 R/W H'00 H'FFE00000 H'1FE00000 8 Bit rate register SCBRR1 R/W H'FF H'FFE00004 H'1FE00004 8 Serial control register SCSCR1 R/W H'00 H'FFE00008 H'1FE00008 8 Transmit data register SCTDR1 R/W H'FF H'FFE0000C H'1FE0000C 8 H'84 H'FFE00010 H'1FE00010 8 1 Serial status register SCSSR1 R/(W)* Receive data register SCRDR1 R H'00 H'FFE00014 H'1FE00014 8 Smart card mode register SCSCMR1 R/W H'00 H'FFE00018 H'1FE00018 8 Serial port register SCSPTR1 R/W H'00*2 H'FFE0001C H'1FE0001C 8 Notes: 1. Only 0 can be written, to clear flags. 2. The value of bits 2 and 0 is undefined. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 721 of 1128 Section 17 Smart Card Interface 17.2 SH7751 Group, SH7751R Group Register Descriptions Only registers that have been added, and bit functions that have been modified, for the smart card interface are described here. 17.2.1 Smart Card Mode Register (SCSCMR1) SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function. SCSCMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit: 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value: — — — — 0 0 — 0 R/W: — — — — R/W R/W — R/W Bits 7 to 4 and 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3: SDIR 0 Description SCTDR1 contents are transmitted LSB-first (Initial value) Receive data is stored in SCRDR1 LSB-first 1 SCTDR1 contents are transmitted MSB-first Receive data is stored in SCRDR1 MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the bit 3 function for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 17.3.4, Register Settings. Bit 2: SINV 0 Description SCTDR1 contents are transmitted as they are (Initial value) Receive data is stored in SCRDR1 as it is 1 SCTDR1 contents are inverted before being transmitted Receive data is stored in SCRDR1 in inverted form Page 722 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0: SMIF Description 0 Smart card interface function is disabled 1 Smart card interface function is enabled 17.2.2 (Initial value) Serial Mode Register (SCSMR1) Bit 7 of SCSMR1 has a different function in smart card interface mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 GM(C/A) CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. With the normal smart card interface, this bit is cleared to 0. Setting this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the TEND flag that indicates completion of transmission, and the type of clock output used. The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register (SCSCR1). In GSM mode, the pulse width is guaranteed when SCK start/stop specifications are made by CKE1 and CKE0. Bit 7: GM Description 0 Normal smart card interface mode operation 1 (Initial value) • The TEND flag is set 12.5 etu after the beginning of the start bit • Clock output on/off control only GSM mode smart card interface mode operation • The TEND flag is set 11.0 etu after the beginning of the start bit • Clock output on/off and fixed-high/fixed-low control (set in SCSCR1) Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 6 to 0: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. With the smart card interface, the following settings should be used: CHR = 0, PE = 1, STOP = 1, MP = 0. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 723 of 1128 Section 17 Smart Card Interface 17.2.3 SH7751 Group, SH7751R Group Serial Control Register (SCSCR1) Bits 1 and 0 of SCSCR1 have a different function in smart card interface mode. Bit: 7 6 5 4 3 2 1 0 TIE RIE TE RE — — CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bits 7 to 4: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Bits 3 and 2—Reserved: Not used with the smart card interface. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits specify the function of the SCK pin. In smart card interface mode, an internal clock is always used as the clock source. In smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. GM CKE1 CKE0 SCK Pin Function 0 0 0 Port I/O pin 1 Clock output as SCK output pin 0 Invalid setting: must not be used 1 Invalid setting: must not be used 0 Output pin with output fixed low 1 Clock output as output pin 0 Output pin with output fixed high 1 Clock output as output pin 1 1 0 1 Page 724 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 17.2.4 Section 17 Smart Card Interface Serial Status Register (SCSSR1) Bit 4 of SCSSR1 has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2 (TEND) are also different. Bit: Initial value: R/W: Note: * 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER/ ERS PER TEND — — 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Only 0 can be written, to clear the flag. Bits 7 to 5: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Bit 4—Error Signal Status (ERS): In smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4: ERS Description 0 Normal reception, no error signal (Initial value) [Clearing conditions] 1 • Power-on reset, manual reset, standby mode, or module standby • When 0 is written to ERS after reading ERS = 1 An error signal has been sent from the receiving side indicating detection of a parity error [Setting condition] When the low level of the error signal is detected Note: Clearing the TE bit in SCSCR1 to 0 does not affect the ERS flag, which retains its previous state. Bit 3—Parity Error (PER): Operates in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 725 of 1128 Section 17 Smart Card Interface SH7751 Group, SH7751R Group Bit 2—Transmit End (TEND): The setting conditions for the TEND flag are as follows. Bit 2: TEND Description 0 Transmission in progress [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 1 Transmission has been ended (Initial value) [Setting conditions] • Power-on reset, manual reset, standby mode, or module standby • When the TE bit in SCSCR1 is 0 and the FER/ERS bit is also 0 • When the GM bit in SCSMR1 is 0, and TDRE = 1 and FER/ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character • When the GM bit in SCSMR1 is 1, and TDRE = 1 and FER/ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 1 and 0—Reserved: Not used with the smart card interface. 17.3 Operation 17.3.1 Overview The main functions of the smart card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. • If a parity error is detected during reception, a low error signal level is output for a 1-etu period 10.5 etu after the start bit. • If an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. • Only asynchronous communication is supported; there is no synchronous communication function. Page 726 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 17.3.2 Section 17 Smart Card Interface Pin Connections Figure 17.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected outside the chip. The data transmission line should be pulled up on the VCC power supply side with a resistor. When the clock generated on the smart card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. Chip port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. Note: If an IC card is not connected, and both TE and RE are set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. VCC TxD IO Data line RxD SH7751/ SH7751R SCK Clock line Px (port) Reset line CLK RST IC card Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 727 of 1128 Section 17 Smart Card Interface 17.3.3 SH7751 Group, SH7751R Group Data Format Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting side to request retransmission of the data. If an error signal is detected during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 DE Transmitting station output Legend: Ds: D0–D7: Dp: DE: Receiving station output Start bit Data bits Parity bit Error signal Figure 17.3 Smart Card Interface Data Format The operation sequence is as follows. 1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. 2. The transmitting station starts transmission of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). 3. With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. 4. The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. Page 728 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. 5. If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it receives an error signal, however, it returns to step 2 and retransmits the erroneous data. 17.3.4 Register Settings Table 17.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 17.3 Smart Card Interface Register Settings Bit Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCSMR1 GM 0 1 O/E 1 0 CKS1 CKS0 SCBRR1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCSCR1 TIE RIE TE RE 0 0 CKE1 CKE0 SCTDR1 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCSSR1 TDRE RDRF ORER FER/ERS PER TEND 0 0 SCRDR1 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 SCSCMR1 — — — — SDIR SINV — SMIF SCSPTR1 — — — SPB1IO SPB1DT SPB0IO EIO SPB0DT Note: A dash indicates an unused bit. Serial Mode Register (SCSMR1) Settings: The GM bit is used to select the timing of TEND flag setting, and, together with the CKE1 and CKE0 bits in the serial control register (SCSCR1), to select the clock output state. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 17.3.5, Clock. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 729 of 1128 Section 17 Smart Card Interface I/O data Ds Da SH7751 Group, SH7751R Group Db Dc Dd De Df Dg Dh Dp DE Guard time TXI (TEND interrupt) 12.5 etu GM = 0 11.0 etu GM = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Figure 17.4 TEND Generation Timing Bit Rate Register (SCBRR1) Setting: SCBRR1 is used to set the bit rate. See section 17.3.5, Clock, for the method of calculating the value to be set. Serial Control Register (SCSCR1) Settings: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. The CKE1 and CKE0 bits specify the clock output state. See section 17.3.5, Clock, for details. Smart Card Mode Register (SCSCMR1) Settings: The SDIR bit and SINV bit are both cleared to 0 if the IC card is of the direct convention type, and both set to 1 if of the inverse convention type. The SMIF bit is set to 1 when the smart card interface is used. Figure 17.5 shows examples of register settings and the waveform of the start character for the two types of IC card (direct convention and inverse convention). With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data in this case is H'3B. The parity bit is 1 since even parity is stipulated for the smart card. With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data in this case is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card. Page 730 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface Inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SCSMR1 is set to odd parity mode. (This applies to both transmission and reception). (Z) A Z Z A Z Z Z A A Z Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (Z) State (Z) State (a) Direct convention (SDIR = SINV = O/E = 0) (Z) A Z Z A A A A A A Z Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp (b) Inverse convention (SDIR = SINV = O/E = 1) Figure 17.5 Sample Start Character Waveforms 17.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (SCBRR1) and the CKS1 and CKS0 bits in the serial mode register (SCSMR1). The equation for calculating the bit rate is shown below. Table 17.5 shows some sample bit rates. If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= Pck × 106 1488 × 22n – 1 × (N + 1) Where: N = Value set in SCBRR1 (0 ≤ N ≤ 255) B = Bit rate (bits/s) Pck = Peripheral module operating frequency (MHz) n = 0 to 3 (See table 17.4) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 731 of 1128 Section 17 Smart Card Interface SH7751 Group, SH7751R Group Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings n CKS1 CKS0 0 0 0 1 0 1 2 1 0 3 1 1 Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) Pck (MHz) N 7.1424 10.00 10.7136 14.2848 25.0 33.0 50.0 0 9600.0 13440.9 14400.0 19200.0 33602.2 44354.8 67204.3 1 4800.0 6720.4 7200.0 9600.0 16801.1 22177.4 33602.2 2 3200.0 4480.3 4800.0 6400.0 11200.7 14784.9 22401.4 Note: Bit rates are rounded to one decimal place. The method of calculating the value to be set in the bit rate register (SCBRR1) from the peripheral module operating frequency and bit rate is shown below. Here, N is an integer in the range 0 ≤ N ≤ 255, and the smaller error is specified. N= Pck × 106 – 1 1488 × 22n – 1 × B Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) Pck (MHz) 7.1424 10.00 10.7136 14.2848 25.00 33.00 50.00 Bits/s N Error N Error N Error N Error N Error N Error N Error 9600 0 0.00 1 30.00 1 25.00 1 8.99 3 14.27 4 8.22 6 0.01 Page 732 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) Pck (MHz) Maximum Bit Rate (bits/s) N n 7.1424 19200 0 0 10.00 26882 0 0 10.7136 28800 0 0 16.00 43010 0 0 20.00 53763 0 0 25.0 67204 0 0 30.0 80645 0 0 33.0 88710 0 0 50.0 67204 0 0 The bit rate error is given by the following equation: Pck Error (%) = 1488 × 22n – 1 × B × (N + 1) × 106 – 1 × 100 Table 17.8 shows the relationship between the smart card interface transmit/receive clock register settings and the output state. Table 17.8 Register Settings and SCK Pin State Register Values Setting 1* 1 2* 2 3* 2 SCK Pin SMIF GM CKE1 CKE0 Output State 1 0 0 0 Port Determined by setting of SPB1IO and SPB1DT bits in SCSPTR1 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 SCK (serial clock) output state Low output Low-level output state SCK (serial clock) output state High output High-level output state SCK (serial clock) output state Notes: 1. The SCK output state changes as soon as the CKE0 bit setting is changed. Clear the CKE1 bit to 0. 2. Stopping and starting the clock by changing the CKE0 bit setting does not affect the clock duty cycle. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 733 of 1128 Section 17 Smart Card Interface SH7751 Group, SH7751R Group Width is undefined Port value Width is undefined Port value SCK (a) When GM = 0 CKE1 value Specified width Specified width CKE1 value SCK (b) When GM = 1 Figure 17.6 Difference in Clock Output According to GM Bit Setting 17.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. Figure 17.7 shows a sample initialization processing flowchart. 1. Clear the TE and RE bits in the serial control register (SCSCR1) to 0. 2. Clear error flags FER/ERS, PER, and ORER in the serial status register (SCSSR1) to 0. 3. Set the GM bit, parity bit (O/E), and baud rate generator select bits (CKS1 and CKS0) in the serial mode register (SCSMR1). Clear the CHR and MP bits to 0, and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR1). When the SMIF bit is set to 1, the TxD pin and RxD pin both go to the high-impedance state. 5. Set the value corresponding to the bit rate in the bit rate register (SCBRR1). 6. Set the clock source select bits (CKE1 and CKE0) in SCSCR1. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCSCR1. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Page 734 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface Initialization Clear TE and RE bits in SCSCR1 to 0 1 Clear FER/ERS, PER, and ORER flags in SCSCR1 to 0 2 In SCSMR1, set parity in O/E bit, clock in CKS1 and CKS0 bits, and set GM 3 Set SMIF, SDIR, and SINV bits in SCSCMR1 4 Set value in SCBRR1 5 In SCSCR1, set clock in CKE1 and CKE0 bits, and clear TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. 6 Wait 1-bit interval elapsed? No Yes Set TIE, RIE, TE, and RE bits in SCSCR1 7 End Figure 17.7 Sample Initialization Flowchart R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 735 of 1128 Section 17 Smart Card Interface SH7751 Group, SH7751R Group Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17.8 shows a sample transmission processing flowchart. 1. 2. 3. 4. Perform smart card interface mode initialization as described in Initialization above. Check that the FER/ERS error flag in SCSSR1 is cleared to 0. Repeat steps 2 and 3 until it can be confirmed that the TEND flag in SCSSR1 is set to 1. Write the transmit data to SCTDR1, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. 5. To continue transmitting data, go back to step 2. 6. To end transmission, clear the TE bit to 0. With the above processing, interrupt handling is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (ERI) request will be generated. See Interrupt Operation below for details. Page 736 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface Start Initialization 1 Start of transmission 2 FER/ERS = 0? No Yes Error handling No TEND = 1? 3 Yes Write transmit data to SCTDR1, and clear TDRE flag in SCSSR1 to 0 4 All data transmitted? 5 No Yes FER/ERS = 0? No Yes Error handling No TEND = 1? Yes Clear TE bit in SCSCR1 to 0 6 End of transmission Figure 17.8 Sample Transmission Processing Flowchart R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 737 of 1128 Section 17 Smart Card Interface SH7751 Group, SH7751R Group Serial Data Reception: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 17.9 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ORER flag and PER flag in SCSSR1 are cleared to 0. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0. 3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1. 4. Read the receive data from SCRDR1. 5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2. 6. To end reception, clear the RE bit to 0. With the above processing, interrupt handling is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated. See Interrupt Operation below for details. If a parity error occurs during reception and the PER flag is set to 1, the received data is still transferred to SCRDR1, and therefore this data can be read. Page 738 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface Start 1 Initialization Start of reception 2 ORER = 0 and PER = 0? No Yes Error handling No RDRF = 1? 3 Yes Read receive data from SCRDR1 and clear RDRF flag in SCSSR1 to 0 4 All data received? 5 No Yes Clear RE bit in SCSCR1 to 0 6 End of reception Figure 17.9 Sample Reception Processing Flowchart Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE to 0 and setting TE to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND flag can be used to check that the transmit operation has been completed. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 739 of 1128 Section 17 Smart Card Interface SH7751 Group, SH7751R Group Interrupt Operation: There are three interrupt sources in smart card interface mode, generating transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request cannot be used in this mode. When the TEND flag in SCSSR1 is set to 1, a TXI interrupt request is generated. When the RDRF flag in SCSSR1 is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and FER/ERS in SCSSR1 is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 17.9. Table 17.9 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit mode Receive mode Flag Mask Bit Interrupt Source Normal operation TEND TIE TXI Error FER/ERS RIE ERI Normal operation RDRF RIE RXI Error PER, ORER RIE ERI Data Transfer Operation by DMAC: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC. In a transmit operation, when the TEND flag in SCSSR1 is set to 1, a TXI interrupt is requested. If the TXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TEND flag is automatically cleared to 0 when data transfer is performed by the DMAC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically, including retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and therefore the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SCSSR1 is set to 1. If the RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC. If an error occurs, an error flag is set but the RDRF flag is not. The DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. The error flag must therefore be cleared. Page 740 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface When performing data transfer using the DMAC, it is essential to set and enable the DMAC before carrying out SCI settings. For details of the DMAC setting procedures, see section 14, Direct Memory Access Controller (DMAC). 17.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. (1) Receive Data Sampling Timing and Receive Margin In asynchronous mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing is shown in figure 17.10. 372 clocks 186 clocks 0 185 371 0 185 371 0 Base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 17.10 Receive Data Sampling Timing in Smart Card Mode R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 741 of 1128 Section 17 Smart Card Interface SH7751 Group, SH7751R Group The receive margin in smart card mode can therefore be expressed as shown in the following equation. M = (0.5 – 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% 2N N Legend: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 372) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L =10) F: Absolute deviation of clock frequency From the above equation, if F = 0 and D = 0.5, the receive margin is 49.866%, as given by the following equation. When D = 0.5 and F = 0: M = (0.5 – 1/2 × 372) × 100% = 49.866% (2) Retransfer Operations Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. Retransfer Operation when SCI is in Receive Mode: Figure 17.11 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated. The PER bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled. 2. The RDRF bit in SCSSR1 is not set for a frame in which an error has occurred. 3. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is not set to 1. 4. If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF bit in SCSSR1 is automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an RXI interrupt request is generated. 5. When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. Page 742 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface nth transfer frame Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer frame n+1 (DE) 5 Ds D0 D1 D2 D3 D4 RDRF 2 4 1 3 PER Figure 17.11 Retransfer Operation in SCI Receive Mode Retransfer Operation when SCI is in Transmit Mode: Figure 17.12 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving side after transmission of one frame is completed, the FER/ERS bit in SCSSR1 is set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated. The FER/ERS bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled. 2. The TEND bit in SCSSR1 is not set for a frame for which an error signal indicating an error is received. 3. If an error signal is not sent back from the receiving side, the FER/ERS bit in SCSSR1 is not set. 4. If an error signal is not sent back from the receiving side, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SCSSR1 is set to 1. If the TIE bit in SCSCR1 is enabled at this time, a TXI interrupt request is generated. nth transfer frame Retransferred frame Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer from SCTDR1 to SCTSR1 TEND Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 Transfer from SCTDR1 to SCTSR1 Transfer from SCTDR1 to SCTSR1 4 2 FER/ERS 1 3 Figure 17.12 Retransfer Operation in SCI Transmit Mode R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 743 of 1128 Section 17 Smart Card Interface SH7751 Group, SH7751R Group (3) Standby Mode and Clock When switching between smart card interface mode and standby mode, the following procedures should be used to maintain the clock duty cycle. Switching from Smart Card Interface Mode to Standby Mode: 1. Set the SBP1IO and SBP1DT bits in SCSPTR1 to the values for the fixed output state in standby mode. 2. Write 0 to the TE and RE bits in the serial control register (SCSCR1) to stop transmit/receive operations. At the same time, set the CKE1 bit to the value for the fixed output state in standby mode. 3. Write 0 to the CKE0 bit in SCSCR1 to stop the clock. 4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. Write H'00 to the serial mode register (SCSMR1) and smart card mode register (SCSMR1). 6. Make the transition to the standby state. Returning from Standby Mode to Smart Card Interface Mode: 7. Clear the standby state. 8. Set the CKE1 bit in SCSCR1 to the value for the fixed output state at the start of standby (the current SCK pin state). 9. Set smart card interface mode and output the clock. Clock signal generation is started with the normal duty cycle. Standby mode Normal operation 123 4 56 Normal operation 7 89 Figure 17.13 Procedure for Stopping and Restarting the Clock Page 744 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 17 Smart Card Interface (4) Power-On and Clock The following procedure should be used to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential. 2. Fix at the output specified by the CKE1 bit in the serial control register (SCSCR1). 3. Set the serial mode register (SCSMR1) and smart card mode register (SCSCMR1), and switch to smart card mode operation. 4. Set the CKE0 bit in SCSCR1 to 1 to start clock output. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 745 of 1128 Section 17 Smart Card Interface Page 746 of 1128 SH7751 Group, SH7751R Group R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 18 I/O Ports Section 18 I/O Ports 18.1 Overview This LSI has a 32-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port. 18.1.1 Features The features of the general-purpose I/O port are as follows: • • • • Available only in PCI-disabled mode. 32-bit I/O port with input/output direction independently specifiable for each bit. Pull-up can be specified independently for each bit. The 32 bits of the general-purpose I/O port are divided into 16-bit port A and 16-bit port B. Interrupts can be input to 16-bit port A. • Use or non-use of the I/O port can be selected with the PORTEN bit in bus control register 2 (BCR2). (Do not set PORTEN = 1 when in PCI-enabled mode.) The features of the SCI I/O port are as follows: • Data can be output when the I/O port is designated for output and SCI enabling has not been set. This allows break function transmission. • The RxD pin value can be read at all times, allowing break state detection. • SCK pin control is possible when the I/O port is designated for output and SCI enabling has not been set. • The SCK pin value can be read at all times. The features of the SCIF I/O port are as follows: • Data can be output when the I/O port is designated for output and SCIF enabling has not been set. This allows break function transmission. • The RxD2 pin value can be read at all times, allowing break state detection. • SCK2, CTS2, and RTS2 pin control is possible when the I/O port is designated for output and SCIF enabling has not been set. • The SCK2, CTS2, and RTS2 pin values can be read at all times. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 747 of 1128 Section 18 I/O Ports 18.1.2 SH7751 Group, SH7751R Group Block Diagrams Figure 18.1 is a block diagram of the 16-bit general-purpose I/O port A with interrupt function. PBnPUP PORTEN Pull-up resistor Internal bus PDTRW Port 15 (input/ output)/AD15 to Port 0 (input/ output)/AD0 1 D Q C MPX 0 ADn output data BCK 0 1 MPX ADnDIR PBnIO MPX 0 Interrupt controller PTIRENn PORTEN PBnPuP DnDIR PBnIO PTIRENn 0: Port not available 0: Pull-up 0: Input 0: Input 0: Interrupt input disabled Data input strobe 1 Q C D BCK 1: Port available 1: Pull-up off 1: Output 1: Output 1: Interrupt input enabled Figure 18.1 16-Bit Port A Page 748 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 18 I/O Ports Figure 18.2 is a block diagram of the 16-bit general-purpose I/O port B, which has no interrupt function. PBnPUP Pull-up resistor PORTEN Internal bus PDTRW Port 31 (input/ output)/AD31 to Port 16 (input/ output)/AD16 1 D Q C MPX 0 ADn output data BCK 0 1 PBnIO Data input strobe 0 MPX MPX ADnDIR 1 C Q D BCK PORTEN PBnPuP DnDIR PBnIO 0: Port not available 0: Pull-up 0: Input 0: Input 1: Port available 1: Pull-up off 1: Output 1: Output Figure 18.2 16-Bit Port B R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 749 of 1128 Section 18 I/O Ports SH7751 Group, SH7751R Group SCI I/O port block diagrams are shown in figures 18.3 to 18.5. Reset R Q D SPB1IO C Internal data bus SPTRW Reset SCK Q R D SPB1DT C SPTRW SCI Clock output enable signal Serial clock output signal * Serial clock input signal Clock input enable signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/A bit in SCSMR1. Figure 18.3 SCK Pin Page 750 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 18 I/O Ports Reset R Q D SPB0IO C Internal data bus SPTRW Reset TxD R Q D SPB0DT C SPTRW SCI Transmit enable signal Serial transmit data Legend: SPTRW: Write to SPTR Figure 18.4 TxD Pin SCI RxD Serial receive data Internal data bus SPTRR Legend: Read SPTR Figure 18.5 RxD Pin R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 751 of 1128 Section 18 I/O Ports SH7751 Group, SH7751R Group SCIF I/O port block diagrams are shown in figures 18.6 to 18.10. Reset R Q D SPB2IO C Internal data bus SPTRW Reset MD1/TxD2 R Q D SPB2DT C SPTRW Mode setting register SCIF Transmit enable signal Serial transmit data Legend: SPTRW: Write to SPTR Figure 18.6 MD1/TxD2 Pin SCIF MD2/RxD2 Serial receive data Mode setting register Internal data bus SPTRR Legend: SPTRR: Read SPTR Figure 18.7 MD2/RxD2 Pin Page 752 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 18 I/O Ports Reset R Q D SCKIO C Internal data bus SPTRW Reset MD0/SCK2 Q R D SCKDT C SPTRW Mode setting register SCIF Clock output enable signal Serial clock output signal * Serial clock input signal Clock input enable signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK2 pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR2. Figure 18.8 MD0/SCK2 Pin R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 753 of 1128 Section 18 I/O Ports SH7751 Group, SH7751R Group Reset R Q D CTSIO C Internal data bus SPTRW Reset MD7/CTS2 R Q D CTSDT C SCIF SPTRW Mode setting register CTS2 signal Modem control enable signal* SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the CTS2 pin function. Figure 18.9 MD7/CTS2 Pin Page 754 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 18 I/O Ports Reset R Q D RTSIO C Internal data bus SPTRW Reset MD8/RTS2 R Q D RTSDT C SCIF Modem control enable signal* SPTRW Mode setting register RTS2 signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the RTS2 pin function. Figure 18.10 MD8/RTS2 Pin 18.1.3 Pin Configuration Table 18.1 shows the 32-bit general-purpose I/O port pin configuration. Table 18.1 32-Bit General-Purpose I/O Port Pins Pin Name Signal I/O Function Port 31 pin AD31/PORT31 I/O I/O port Port 30 pin AD30/PORT30 I/O I/O port Port 29 pin AD29/PORT29 I/O I/O port Port 28 pin AD28/PORT28 I/O I/O port Port 27 pin AD27/PORT27 I/O I/O port Port 26 pin AD26/PORT26 I/O I/O port Port 25 pin AD25/PORT25 I/O I/O port R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 755 of 1128 Section 18 I/O Ports SH7751 Group, SH7751R Group Pin Name Signal I/O Function Port 24 pin AD24/PORT24 I/O I/O port Port 23 pin AD23/PORT23 I/O I/O port Port 22 pin AD22/PORT22 I/O I/O port Port 21 pin AD21/PORT21 I/O I/O port Port 20 pin AD20/PORT20 I/O I/O port Port 19 pin AD19/PORT19 I/O I/O port Port 18 pin AD18/PORT18 I/O I/O port Port 17 pin AD17/PORT17 I/O I/O port Port 16 pin AD16/PORT16 I/O I/O port Port 15 pin AD15/PORT15 I/O* I/O port / GPIO interrupt Port 14 pin AD14/PORT14 I/O* I/O port / GPIO interrupt Port 13 pin AD13/PORT13 I/O* I/O port / GPIO interrupt Port 12 pin AD12/PORT12 I/O* I/O port / GPIO interrupt Port 11 pin AD11/PORT11 I/O* I/O port / GPIO interrupt Port 10 pin AD10/PORT10 I/O* I/O port / GPIO interrupt Port 9 pin AD9/PORT9 I/O* I/O port / GPIO interrupt Port 8 pin AD8/PORT8 I/O* I/O port / GPIO interrupt Port 7 pin AD7/PORT7 I/O* I/O port / GPIO interrupt Port 6 pin AD6/PORT6 I/O* I/O port / GPIO interrupt Port 5 pin AD5/PORT5 I/O* I/O port / GPIO interrupt Port 4 pin AD4/PORT4 I/O* I/O port / GPIO interrupt Port 3 pin AD3/PORT3 I/O* I/O port / GPIO interrupt Port 2 pin AD2/PORT2 I/O* I/O port / GPIO interrupt Port 1 pin AD1/PORT1 I/O* I/O port / GPIO interrupt Port 0 pin AD0/PORT0 I/O* I/O port / GPIO interrupt Note: * When port pins are used as GPIO interrupts, they must be set to input mode. The input setting can be made in the PCTRA register. Page 756 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 18 I/O Ports Table 18.2 shows the SCI I/O port pin configuration. Table 18.2 SCI I/O Port Pins Pin Name Abbreviation I/O Function Serial clock pin SCK I/O Clock input/output Receive data pin RxD Input Receive data input Transmit data pin TxD Output Transmit data output Note: They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/A bit in SCSMR1. Break state transmission and detection can be performed by means of a setting in the SCI's SCSPTR1 register. Table 18.3 shows the SCIF I/O port pin configuration. Table 18.3 SCIF I/O Port Pins Pin Name Abbreviation I/O Function Serial clock pin MD0/SCK2 I/O Clock input/output Receive data pin MD2/RxD2 Input Receive data input Transmit data pin MD1/TxD2 Output Transmit data output Modem control pin MD7/CTS2 I/O Transmission enabled Modem control pin MD8/RTS2 I/O Transmission request Note: These pins function as the MD0, MD1, MD2, MD7, and MD8 mode input pins after a poweron reset. These pins are made to function as serial pins by performing SCIF operation settings with the TE, RE, CKE1, and CKE0 bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF's SCSPTR2 register. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 757 of 1128 Section 18 I/O Ports 18.1.4 SH7751 Group, SH7751R Group Register Configuration The 32-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port have seven registers, as shown in table 18.4. Table 18.4 I/O Port Registers Abbreviation R/W Area 7 Initial Value* P4 Address Address Port control register A PCTRA R/W H'00000000 H'FF80002C H'1F80002C 32 Port data register A PDTRA R/W Undefined H'FF800030 H'1F800030 16 Port control register B PCTRB R/W H'00000000 H'FF800040 H'1F800040 32 Port data register B PDTRB R/W Undefined H'FF800044 H'1F800044 16 GPIO interrupt control register GPIOIC R/W H'00000000 H'FF800048 H'1F800048 16 Serial port register SCSPTR1 R/W Undefined H'FFE0001C H'1FE0001C 8 Serial port register SCSPTR2 R/W Undefined H'FFE80020 H'1FE80020 16 Name Note: * Access Size Initialized by a power-on reset. Page 758 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 18 I/O Ports 18.2 Register Descriptions 18.2.1 Port Control Register A (PCTRA) Port control register A (PCTRA) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port A (port 15 pin to port 0 pin). As the initial value of port data register A (PDTRA) is undefined, all the bits in the 16-bit port A should be set to output with PCTRA after writing a value to the PDTRA register. PCTRA is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 PB15PUP PB15IO PB14PUP PB14IO PB13PUP PB13IO PB12PUP PB12IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 PB11PUP PB11IO PB10PUP PB10IO PB9PUP PB9IO PB8PUP PB8IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PB7PUP PB7IO PB6PUP PB6IO PB5PUP PB5IO PB4PUP PB4IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB3PUP PB3IO PB2PUP PB2IO PB1PUP PB1IO PB0PUP PB0IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 759 of 1128 Section 18 I/O Ports SH7751 Group, SH7751R Group Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16bit port A is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP Description 0 Bit m (m = 0–15) of 16-bit port A is pulled up 1 Bit m (m = 0–15) of 16-bit port A is not pulled up (Initial value) Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port A is an input or an output. Bit 2n: PBnIO Description 0 Bit m (m = 0–15) of 16-bit port A is an input 1 Bit m (m = 0–15) of 16-bit port A is an output 18.2.2 (Initial value) Port Data Register A (PDTRA) Port data register A (PDTRA) is a 16-bit readable/writable register used as a data latch for each bit in the 16-bit port A. When a bit is set as an output, the value written to the PDTRA register is output from the external pin. When a value is read from the PDTRA register while a bit is set as an input, the external pin value sampled on the external bus clock is read. When a bit is set as an output, the value written to the PDTRA register is read. PDTRA is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. Bit: 15 14 13 12 11 10 PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT Initial value: R/W: Bit: Initial value: R/W: Page 760 of 1128 9 8 PB9DT PB8DT — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 18.2.3 Section 18 I/O Ports Port Control Register B (PCTRB) Port control register B (PCTRB) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port B (port 31 pin to port 16 pin). As the initial value of port data register B (PDTRB) is undefined, each bit in the 16-bit port B should be set to output with PCTRB after writing a value to the PDTRB register. PCTRB is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Bit: 31 30 29 28 27 26 25 24 PB31PUP PB31IO PB30PUP PB30IO PB29PUP PB29IO PB28PUP PB28IO Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 PB27PUP PB27IO PB26PUP PB26IO PB25PUP PB25IO PB24PUP PB24IO Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 PB23PUP PB23IO PB22PUP PB22IO PB21PUP PB21IO PB20PUP PB20IO Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 PB19PUP PB19IO PB18PUP PB18IO PB17PUP PB17IO PB16PUP PB16IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 761 of 1128 Section 18 I/O Ports SH7751 Group, SH7751R Group Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16bit port B is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP Description 0 Bit m (m = 16–31) of 16-bit port B is pulled up 1 Bit m (m = 16–31) of 16-bit port B is not pulled up (Initial value) Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port B is an input or an output. Bit 2n: PBnIO Description 0 Bit m (m = 16–31) of 16-bit port B is an input 1 Bit m (m = 16–31) of 16-bit port B is an output 18.2.4 (Initial value) Port Data Register B (PDTRB) Port data register B (PDTRB) is a 16-bit readable/writable register used as a data latch for each bit in the 16-bit port B. When a bit is set as an output, the value written to the PDTRB register is output from the external pin. When a value is read from the PDTRB register while a bit is set as an input, the external pin value sampled on the external bus clock is read. When a bit is set as an output, the value written to the PDTRB register is read. PDTRB is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. Bit: 15 14 13 12 11 10 9 8 PB31DT PB30DT PB29DT PB28DT PB27DT PB26DT PB25DT PB24DT Initial value: R/W: Bit: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB23DT PB22DT PB21DT PB20DT PB19DT PB18DT PB17DT PB16DT Initial value: R/W: Page 762 of 1128 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 18.2.5 Section 18 I/O Ports GPIO Interrupt Control Register (GPIOIC) The GPIO interrupt control register (GPIOIC) is a 16-bit readable/writable register that performs 16-bit interrupt input control. GPIOIC is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. GPIO interrupts are active-low level interrupts. Bit-by-bit masking is possible, and the OR of all the bits set as GPIO interrupts is used for interrupt detection. Which bits interrupts are input to can be identified by reading the PDTRA register. Bit: 15 14 13 12 11 10 9 PTIREN15 PTIREN14 PTIREN13 PTIREN12 PTIREN11 PTIREN10 PTIREN9 Initial value: 8 PTIREN8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PTIREN7 PTIREN6 PTIREN5 PTIREN4 PTIREN3 PTIREN2 PTIREN1 PTIREN0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: Bit: Initial value: R/W: Bit n (n = 0–15)—Port Interrupt Enable (PTIRENn): Specifies whether interrupt input is performed for each bit. Bit n: PTIRENn Description 0 Port m (m = 0–15) of 16-bit port A is used as a normal I/O port (Initial value) 1 Port m (m = 0–15) of 16-bit port A is used as a GPIO interrupt* Note: * When using an interrupt, set the corresponding port to input in the PCTRA register before making the PTIRENn setting. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 763 of 1128 Section 18 I/O Ports 18.2.6 SH7751 Group, SH7751R Group Serial Port Register (SCSPTR1) Bit: Initial value: R/W: 7 6 5 4 EIO — — — 3 2 1 0 0 0 0 0 0 — 0 — R/W — — — R/W R/W R/W R/W SPB1IO SPB1DT SPB0IO SPB0DT The serial port register (SCSPTR1) is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt. SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. SCSPTR1 is not initialized in the module standby state or standby mode. Bit 7—Error Interrupt Only (EIO): See section 15.2.8, Serial Port Register (SCSPTR1). Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO Description 0 SPB1DT bit value is not output to the SCK pin 1 SPB1DT bit value is output to the SCK pin Page 764 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 18 I/O Ports Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 2: SPB1DT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 1—Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR1 should be cleared to 0. Bit 1: SPB0IO Description 0 SPB0DT bit value is not output to the TxD pin 1 SPB0DT bit value is output to the TxD pin (Initial value) Bit 0—Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB0DT Description 0 Input/output data is low-level 1 Input/output data is high-level R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 765 of 1128 Section 18 I/O Ports 18.2.7 SH7751 Group, SH7751R Group Serial Port Register (SCSPTR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT 0 — 0 — 0 — 0 — R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: SPB2IO SPB2DT The serial port register (SCSPTR2) is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface with FIFO (SCIF) pins. Input data can be read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK2 pin data reading and output data writing can be performed by means of bits 3 and 2. CTS2 pin data reading and output data writing can be performed by means of bits 5 and 4, and RTS2 pin data reading and output data writing by means of bits 7 and 6. SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, 2, and 0 is undefined. SCSPTR2 is not initialized in standby mode or in the module standby state. Bits 15 to 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Serial Port RTS Port I/O (RTSIO): Specifies serial port RTS2 pin input/output. When the RTS2 pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 7: RTSIO Description 0 RTSDT bit value is not output to the RTS2 pin 1 RTSDT bit value is output to the RTS2 pin Page 766 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 18 I/O Ports Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port RTS2 pin input/output data. Input or output is specified by the RTSIO pin (see the description of bit 7, RTSIO, for details). When the RTS2 pin is designated as an output, the value of the RTSDT bit is output to the RTS2 pin. The RTS2 pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 6: RTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 5—Serial Port CTS Port I/O (CTSIO): Specifies serial port CTS2 pin input/output. When the CTS2 pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 5: CTSIO Description 0 CTSDT bit value is not output to the CTS2 pin 1 CTSDT bit value is output to the CTS2 pin (Initial value) Bit 4—Serial Port CTS Port Data (CTSDT): Specifies the serial port CTS2 pin input/output data. Input or output is specified by the CTSIO pin (see the description of bit 5, CTSIO, for details). When the CTS2 pin is designated as an output, the value of the CTSDT bit is output to the CTS2 pin. The CTS2 pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 4: CTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 3—Serial Port Clock Port I/O (SCKIO): Sets the I/O for the SCK2 pin serial port. To actually set the SCK2 pin as the port output pin and output the value set in the SCKDT bit, set the CKE1 and CKE0 bits of the SCSCR2 register to 0. Bit 3: SCKIO Description 0 Shows that the value of the SCKDT bit is not output to the SCK2 pin (Initial value) 1 Shows that the value of the SCKDT bit is output to the SCK2 pin R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 767 of 1128 Section 18 I/O Ports SH7751 Group, SH7751R Group Bit 2—Serial Port Clock Port Data (SCKDT): Specifies the I/O data for the SCK2 pin serial port. The SCKIO bit specified input or output. (See bit 3: SCKIO, for details.) When set for output, the value of the SCKDT bit is output to the SCK2 pin. Regardless of the value of the SCKIO bit, the value of the SCK2 pin is fetched from the SCKDT bit. The initial value after a power-on reset or manual reset is undefined. Bit 2: SCKDT Description 0 Shows I/O data level is LOW 1 Shows I/O data level is HIGH Bit 1—Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0. Bit 1: SPB2IO Description 0 SPB2DT bit value is not output to the TxD2 pin 1 SPB2DT bit value is output to the TxD2 pin (Initial value) Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB2DT Description 0 Input/output data is low-level 1 Input/output data is high-level Page 768 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) Section 19 Interrupt Controller (INTC) 19.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority. 19.1.1 Features The INTC has the following features. • Fifteen interrupt priority levels can be set By setting the five interrupt priority registers, the priorities of on-chip peripheral module interrupts can be selected from 15 levels for different request sources. • NMI noise canceler function The NMI input level bit indicates the NMI pin state. The pin state can be checked by reading this bit in the interrupt exception handler, enabling it to be used as a noise canceler. • NMI request masking when SR.BL bit is set It is possible to select whether or not NMI requests are to be masked when the SR.BL bit is set. 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the INTC. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 769 of 1128 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group NMI Input control IRL3– IRL0 4 4 TMU (Interrupt request) RTC (Interrupt request) SCI (Interrupt request) SCIF (Interrupt request) SR WDT (Interrupt request) IMASK REF (Interrupt request) DMAC (Interrupt request) H-UDI (Interrupt request) GPIO PCIC Priority identifier Interrupt request Comparator CPU (Interrupt request) (Interrupt request) IPR ICR Internal bus IPRA–IPRD, INTPRI00 Bus interface INTC Legend: TMU: RTC: SCI: SCIF: WDT: REF: DMAC: H-UDI: GPIO: PCIC: ICR: IPRA–IPRD: INTPRI00: SR: Timer unit Realtime clock unit Serial communication interface Serial communication interface with FIFO Watchdog timer Memory refresh controller section of the bus state controller Direct memory access controller High-performance user debug interface unit I/O port PCI bus controller Interrupt control register Interrupt priority registers A–D Interrupt priority register 00 Status register Figure 19.1 Block Diagram of INTC Page 770 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 19.1.3 Section 19 Interrupt Controller (INTC) Pin Configuration Table 19.1 shows the INTC pin configuration. Table 19.1 INTC Pins Pin Name Abbreviation I/O Function Nonmaskable interrupt input pin NMI Input Input of nonmaskable interrupt request signal Interrupt input pins IRL3–IRL0 Input Input of interrupt request signals (maskable by IMASK in SR) 19.1.4 Register Configuration The INTC has the registers shown in table 19.2. Table 19.2 INTC Registers Name Abbreviation R/W Initial Value*1 Interrupt control register ICR R/W * H'FFD00000 H'1FD00000 16 Interrupt priority register A IPRA R/W H'0000 H'FFD00004 H'1FD00004 16 Interrupt priority register B IPRB R/W H'0000 H'FFD00008 H'1FD00008 16 Interrupt priority register C IPRC R/W H'0000 H'FFD0000C H'1FD0000C 16 Interrupt priority register D IPRD R/W H'DA74 H'FFD00010 H'1FD00010 16 Interrupt priority register 00 INTPRI00 R/W H'00000000 H'FE080000 H'1E080000 32 Interrupt request register 00 INTREQ00 R H'00000000 H'FE080020 H'1E080020 32 Interrupt mask register 00 INTMSK00 R/W H'000003FF H'FE080040 H'1E080040 32 Interrupt mask clear register 00 INTMSKCLR00 W — H'FE080060 H'1E080060 32 2 P4 Address Area 7 Address Access Size Notes: 1. Initialized by a power-on reset or manual reset. 2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 771 of 1128 Section 19 Interrupt Controller (INTC) 19.2 SH7751 Group, SH7751R Group Interrupt Sources There are three types of interrupt sources: NMI, IRL, and on-chip peripheral modules. Each interrupt has a priority level (16–0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored. 19.2.1 NMI Interrupt The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in the status register in the CPU is set to 1. In sleep or standby mode, the interrupt is accepted even if the BL bit is set to 1. A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1. Input from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in the interrupt control register (ICR) is used to select either rising or falling edge. When the NMIE bit in the ICR register is modified, the NMI interrupt is not detected for a maximum of 6 bus clock cycles after the modification. NMI interrupt exception handling does not affect the interrupt mask level bits (IMASK) in the status register (SR). Page 772 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 19.2.2 Section 19 Interrupt Controller (INTC) IRL Interrupts IRL interrupts are input by level at pins IRL3–IRL0. The priority level is the level indicated by pins IRL3–IRL0. An IRL3–IRL0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). SH7751/SH7751R Priority encoder Interrupt requests 4 IRL3 to IRL0 IRL3 to IRL0 Figure 19.2 Example of IRL Interrupt Connection R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 773 of 1128 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Table 19.3 IRL3–IRL0 Pins and Interrupt Levels IRL3 IRL2 IRL1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 IRL0 Interrupt Priority Level Interrupt Request 0 15 Level 15 interrupt request 1 14 Level 14 interrupt request 0 13 Level 13 interrupt request 1 12 Level 12 interrupt request 0 11 Level 11 interrupt request 1 10 Level 10 interrupt request 0 9 Level 9 interrupt request 1 8 Level 8 interrupt request 0 7 Level 7 interrupt request 1 6 Level 6 interrupt request 0 5 Level 5 interrupt request 1 4 Level 4 interrupt request 0 3 Level 3 interrupt request 1 2 Level 2 interrupt request 0 1 Level 1 interrupt request 1 0 No interrupt request A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every bus clock cycle remain unchanged for three consecutive cycles, so that no transient level on the IRL pin change is detected. In standby mode, as the bus clock is stopped, noise cancellation is performed using the 32.768 kHz clock for the RTC instead. When the RTC is not used, therefore, interruption by means of IRL interrupts cannot be performed in standby mode. The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the interrupt handling starts. However, the priority level can be changed to a higher one. The interrupt mask bits (IMASK) in the status register (SR) are not affected by IRL interrupt handling. Pins IRL0–IRL3 can be used for four independent interrupt requests by setting the IRLM bit to 1 in the ICR register. Page 774 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 19.2.3 Section 19 Interrupt Controller (INTC) On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following ten modules: • • • • • • • • • • High-performance user debug interface unit (H-UDI) Direct memory access controller (DMAC) Timer unit (TMU) Realtime clock (RTC) Serial communication interface (SCI) Serial communication interface with FIFO (SCIF) Bus state controller (BSC) Watchdog timer (WDT) I/O port (GPIO) PCI bus controller (PCIC) Not every interrupt source is assigned a different interrupt vector, bus sources are reflected in the interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT register value as a branch offset in the exception handling routine. A priority level from 15 to 0 can be set for each module by means of interrupt priority registers A to D (IPRA–IPRD) and interrupt priority register 00 (INTPRI00). The interrupt mask bits (IMASK) in the status register (SR) are not affected by on-chip peripheral module interrupt handling. On-chip peripheral module interrupt source flag and interrupt enable flag updating should only be carried out when the BL bit in the status register (SR) is set to 1. To prevent acceptance of an erroneous interrupt from an interrupt source that should have been updated, first read the on-chip peripheral register containing the relevant flag, then clear the BL bit to 0. Furthermore, in case of an interrupt of TMU channels 3 and 4 and PCIC, read the interrupt factor register 00 (INTREQ00). This will secure the necessary timing internally. When updating a number of flags, there is no problem if only the register containing the last flag updated is read. If flag updating is performed while the BL bit is cleared to 0, the program may jump to the interrupt handling routine when the INTEVT register value is 0. In this case, interrupt handling is initiated due to the timing relationship between the flag update and interrupt request recognition within the chip. Processing can be continued without any problem by executing an RTE instruction. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 775 of 1128 Section 19 Interrupt Controller (INTC) 19.2.4 SH7751 Group, SH7751R Group Interrupt Exception Handling and Priority Table 19.4 lists the codes for the interrupt event register (INTEVT), and the order of interrupt priority. Each interrupt source is assigned a unique INTEVT code. The start address of the interrupt handler is common to each interrupt source. This is why, for instance, the value of INTEVT is used as an offset at the start of the interrupt handler and branched to in order to identify the interrupt source. The order of priority of the on-chip peripheral modules is specified as desired by setting priority levels from 0 to 15 in interrupt priority registers A to D (IPRA–IPRD) and interrupt priority register 00 (INTPRI00). The order of priority of the on-chip peripheral modules is set to 0 by a reset. When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated simultaneously, they are handled according to the default priority order shown in table 19.4. Updating of interrupt priority registers A to D, and INTPRI00 should only be carried out when the BL bit in the status register (SR) is set to 1. To prevent erroneous interrupt acceptance, first read one of the interrupt priority registers, then clear the BL bit to 0. This will secure the necessary timing internally. Page 776 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) Table 19.4 Interrupt Exception Handling Sources and Priority Order Interrupt Source INTEVT Interrupt Priority IPR (Bit Code (Initial Value) Numbers) Priority within Default IPR Setting Unit Priority NMI H'1C0 16 — — IRL IRL3–IRL0 = 0 H'200 15 — — IRL3–IRL0 = 1 H'220 14 — — IRL3–IRL0 = 2 H'240 13 — — IRL3–IRL0 = 3 H'260 12 — — IRL3–IRL0 = 4 H'280 11 — — IRL3–IRL0 = 5 H'2A0 10 — — IRL3–IRL0 = 6 H'2C0 9 — — IRL3–IRL0 = 7 H'2E0 8 — — IRL3–IRL0 = 8 H'300 7 — — IRL3–IRL0 = 9 H'320 6 — — IRL3–IRL0 = A H'340 5 — — IRL3–IRL0 = B H'360 4 — — IRL3–IRL0 = C H'380 3 — — IRL3–IRL0 = D H'3A0 2 — — — IRL3–IRL0 = E H'3C0 1 — IRL0 H'240 15–0 (13) IPRD (15–12) — IRL1 H'2A0 15–0 (10) IPRD (11–8) — IRL2 H'300 15–0 (7) IPRD (7–4) — IRL3 H'360 15–0 (4) IPRD (3–0) — — H-UDI H-UDI H'600 15–0 (0) IPRC (3–0) GPIO GPIOI H'620 15–0 (0) IPRC (15–12) — DMAC DMTE0 H'640 15–0 (0) IPRC (11–8) DMTE1 H'660 DMTE2 H'680 DMTE3 H'6A0 DMTE4* H'780 DMTE5* H'7A0 DMTE6* H'7C0 DMTE7* H'7E0 DMAE H'6C0 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 High High Low Low Page 777 of 1128 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Interrupt Source INTEVT Interrupt Priority IPR (Bit Code (Initial Value) Numbers) Priority within Default IPR Setting Unit Priority PCIC PCISERR H'A00 15–0 (0) INTPRI00 (3–0) — PCIERR H'AE0 15–0 (0) INTPRI00 (7–4) High PCIPWDWN H'AC0 PCIPWON H'AA0 PCIDMA0 H'A80 PCIDMA1 H'A60 PCIDMA2 H'A40 PCIDMA3 H'A20 TMU3 TUNI3 H'B00 15–0 (0) INTPRI00 (11–8) — TMU4 TUNI4 H'B80 15–0 (0) INTPRI00 (15–12) — TMU0 TUNI0 H'400 15–0 (0) IPRA (15–12) — TMU1 TUNI1 H'420 15–0 (0) IPRA (11–8) — TMU2 TUNI2 H'440 15–0 (0) IPRA (7–4) High TICPI2 H'460 ATI H'480 PRI H'4A0 CUI H'4C0 ERI H'4E0 RXI H'500 TXI H'520 TEI H'540 ERI H'700 RXI H'720 BRI H'740 TXI H'760 WDT ITI H'560 15–0 (0) IPRB (15–12) — REF RCMI H'580 15–0 (0) IPRB (11–8) ROVI H'5A0 RTC SCI SCIF High Low Low 15–0 (0) IPRA (3–0) High Low 15–0 (0) IPRB (7–4) High Low 15–0 (0) IPRC (7–4) High Low High Low Low Legend: TUNI0–TUNI4: Underflow interrupts Page 778 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) TICPI2: Input capture interrupt ATI: Alarm interrupt PRI: Periodic interrupt CUI: Carry-up interrupt ERI: Receive-error interrupt RXI: Receive-data-full interrupt TXI: Transmit-data-empty interrupt TEI: Transmit-end interrupt BRI: Break interrupt request ITI: Interval timer interrupt RCMI: Compare-match interrupt ROVI: Refresh counter overflow interrupt H-UDI: H-UDI interrupt GPIOI: I/O port interrupt DMTE0–DMTE7: DMAC transfer end interrupts DMAE: DMAC address error interrupt PCISERR: PCIC SERR error interrupt PCIERR: PCIC error interrupt PCIPWDWN: PCIC power-down request interrupt PCIPWON: PCIC power-ON request interrupt PCIDMA0 to 3: PCIC DMA transfer end interrupts Note: * SH7751R only R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 779 of 1128 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group 19.3 Register Descriptions 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized to H'0000 and IPRD is to H'DA74 by a reset. They are not initialized in standby mode. IPRA to IPRC Bit: 15 14 13 12 11 10 9 8 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 R/W: R/W: IPRD Bit: Initial value: R/W: Bit: Initial value: R/W: 1 1 0 1 1 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 1 1 1 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 19.5 shows the relationship between the interrupt request sources and the IPRA–IPRD register bits. Page 780 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) Table 19.5 Interrupt Request Sources and IPRA–IPRD Registers Bits Register 15–12 11–8 7–4 3–0 Interrupt priority register A TMU0 TMU1 TMU2 RTC Interrupt priority register B WDT REF*1 SCI1 Reserved*2 Interrupt priority register C GPIO DMAC SCIF H-UDI Interrupt priority register D IRL0 IRL1 IRL2 IRL3 Notes: 1. REF is the memory refresh unit in the bus state controller (BSC). See section 13, Bus State Controller (BSC), for details. 2. Reserved bits: These bits are always read as 0 and should always be written with 0. As shown in table 19.5, four on-chip peripheral modules are assigned to each register. Interrupt priority levels are established by setting a value from H'F (1111) to H'0 (0000) in each of the fourbit groups: 15–12, 11–8, 7–4, and 3–0. Setting H'F designates priority level 15 (the highest level), and setting H'0 designates priority level 0 (requests are masked). 19.3.2 Interrupt Control Register (ICR) The interrupt control register (ICR) is a 16-bit register that sets the input signal detection mode for external interrupt input pin NMI and indicates the input signal level at the NMI pin. This register is initialized by a power-on reset or manual reset. It is not initialized in standby mode. Bit: 15 14 13 12 11 10 9 8 Bit name: NMIL MAI — — — — NMIB NMIE Initial value: 0/1* 0 0 0 0 0 0 0 R/W: R R/W — — — — R/W R/W Bit: 7 6 5 4 3 2 1 0 IRLM — — — — — — — 0 0 0 0 0 0 0 0 R/W — — — — — — — Bit name: Initial value: R/W: Note: * 1 when NMI pin input is high, 0 when low. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 781 of 1128 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. It cannot be modified. Bit 15: NMIL Description 0 NMI pin input level is low 1 NMI pin input level is high Bit 14—NMI Interrupt Mask (MAI): Specifies whether or not all interrupts are to be masked while the NMI pin input level is low, irrespective of the CPU's SR.BL bit. Bit 14: MAI Description 0 Interrupts enabled even while NMI pin is low 1 Interrupts disabled while NMI pin is low* Note: * (Initial value) NMI interrupts are accepted in normal operation and in sleep mode. In standby mode, all interrupts are masked, and standby is not cleared, while the NMI pin is low. Bit 9—NMI Block Mode (NMIB): Specifies whether an NMI request is to be held pending or detected immediately while the SR.BL bit is set to 1. Bit 9: NMIB Description 0 NMI interrupt requests held pending while SR.BL bit is set to 1 (Initial value) 1 NMI interrupt requests detected while SR.BL bit is set to 1 Notes: 1. If interrupt requests are enabled while SR.BL = 1, the previous exception information will be lost, and so must be saved beforehand. 2. This bit is cleared automatically by NMI acceptance. Bit 8—NMI Edge Select (NMIE): Specifies whether the falling or rising edge of the interrupt request signal to the NMI pin is detected. Bit 8: NMIE Description 0 Interrupt request detected on falling edge of NMI input 1 Interrupt request detected on rising edge of NMI input Page 782 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) Bit 7—IRL Pin Mode (IRLM): Specifies whether pins IRL3–IRL0 are to be used as levelencoded interrupt requests or as four independent interrupt requests. Bit 7: IRLM Description 0 IRL pins used as level-encoded interrupt requests 1 IRL pins used as four independent interrupt requests (level-sense IRQ mode) (Initial value) Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written with 0. 19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00) The interrupt priority level setting register (INTPRI00) sets the order of priority (levels 15 to 0) of the internal peripheral module interrupts. The INTPRI00 register is a 32-bit read/write register. It is initialized to H'00000000 at a reset. It is not initialized in standby mode. Bit: 31 30 29 ... 19 18 17 16 ... Initial value: 0 0 0 ... 0 0 0 0 R/W: R R R ... R R R R Bit: 15 14 13 ... 3 2 1 0 ... Initial value: R/W: 0 0 0 ... 0 0 0 0 R/W R/W R/W ... R/W R/W R/W R/W Table 19.6 shows the relationship between interrupt request sources and the respective bits of the INTPRI00 register. Table 19.6 Interrupt Request Sources and INTPRI00 Register Bits Register 31 to 28 27 to 24 23 to 20 19 to 16 15 to 12 11 to 8 7 to 4 3 to 0 Interrupt priority level setting register Reserved Reserved Reserved Reserved TMU ch4 TMU ch3 PCI (1) PCI (0) Note: Reserved bits: These bits always read as 0, and should only be written with 0. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 783 of 1128 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group As shown in table 19.6, 8 combinations of internal peripheral modules are assigned to one register. Values of H'F (1111) to H'0 (0000) can be set in each 4 bits, allowing the order levels of the corresponding interrupts to be set. H'F is priority level 15 (highest level) while H'0 is priority level 0 (request mask). Reserved: These bits are always read as 0, and should only be written with 0. 19.3.4 Interrupt Factor Register 00 (INTREQ00) The interrupt factor register 00 (INTREQ00) shows which interrupt have been requested of the INTC. Even when the interrupts are masked with INTPRI00 and INTMSK00, the bits in this register are not affected. INTREQ00 is a 32-bit read-only register. Bit: 31 30 29 ... 11 10 9 8 ... Initial value: 0 0 0 ... 0 0 0 0 R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bits 31 to 0—Interrupt Request: These bits indicate the existence of an interrupt request corresponding to each bit. For the correspondence between bits and interrupt sources, see section 19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation. Bits 31 to 0 Description 0 Shows no corresponding interrupt request 1 Shows existence of corresponding interrupt request 19.3.5 (Initial value) Interrupt Mask Register 00 (INTMSK00) The interrupt mask register 00 (INTMSK00) specifies whether or not to mask individual interrupts each time they are requested. The INTMSK00 register is a 32-bit register. It is initialized to H'000003FF at a reset. The values are retained in standby mode. Page 784 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) To clear each interrupt mask, write 1 to the corresponding bit of the INTMSKCLR00 register. The values in INTMSK00 do not change if you write 0 to it. Bit: 31 30 29 ... 11 10 9 8 ... Initial value: 0 0 0 ... 0 0 1 1 R/W: R R R ... R R R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: Bits 31 to 0—Interrupt Masks: These bits indicate the existence of an interrupt request corresponding to each bit. For the correspondence between bits and interrupt sources, see section 19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation. Bits 31 to 0 Description 0 Accept corresponding interrupt request 1 Mask corresponding interrupt request 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) The interrupt mask clear register 00 (INTMSKCLR00) clears the masks for each request of the corresponding interrupt. INTMSKCLR00 is a 32-bit write-only register. Bit: 31 30 29 ... 11 10 9 8 ... Initial value: — — — ... — — — — R/W: W W W ... W W W W Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W: W W W W W W W W R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 785 of 1128 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Bits 31 to 0—Interrupt Mask Clear: These bits indicate the existence of an interrupt request corresponding to each bit. For the correspondence between bits and interrupt sources, see section 19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation. Bits 31 to 0 Description 0 Do not change corresponding interrupt mask 1 Clear corresponding interrupt mask 19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation The following shows the relationship between individual bits in the register and interrupt factors. Table 19.7 Bit Allocation Bit No. Module Interrupt 31 to 10 Reserved Reserved 9 TMU TUNI4 8 TMU TUNI3 7 PCI PCIERR 6 PCI PCIPWDWN 5 PCI PCIPWON 4 PCI PCIDMA0 3 PCI PCIDMA1 2 PCI PCIDMA2 1 PCI PCIDMA3 0 PCI PCISERR Page 786 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 19.4 INTC Operation 19.4.1 Interrupt Operation Sequence Section 19 Interrupt Controller (INTC) The sequence of operations when an interrupt is generated is described below. Figure 19.3 shows a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, according to the priority levels set in interrupt priority registers A to D (IPRA–IPRD) and interrupt priority register 00 (INTPRI00). Lower-priority interrupts are held pending. If two of these interrupts have the same priority level, or if multiple interrupts occur within a single module, the interrupt with the highest priority according to table 19.4, Interrupt Exception Handling Sources and Priority Order, is selected. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (IMASK) in the status register (SR) of the CPU. If the request priority level is higher that the level in bits IMASK, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU accepts an interrupt at a break between instructions. 5. The interrupt source code is set in the interrupt event register (INTEVT). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). The interrupt handler may branch with the INTEVT register value as its offset in order to identify the interrupt source. This enables it to branch to the handling routine for the particular interrupt source. Notes: 1. The interrupt mask bits (IMASK) in the status register (SR) are not changed by acceptance of an interrupt in this LSI. 2. The interrupt source flag should be cleared in the exception handling routine. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 19.8 (Time for priority decision and SR mask bit comparison) before clearing the BL bit or executing an RTE instruction. 3. Depending on the interrupt factor, the interrupt mask (INTMSK00) must be cleared for each factor using the INTMSKCLR00 register. See section 19.3.5, Interrupt Mask R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 787 of 1128 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Register 00 (INTMSK00), and section 19.3.6, Interrupt Mask Clear Register 00 (INTMSKCLR00), for details. Program execution state Interrupt generated? No Yes (BL bit in SR = 0) or (sleep or standby mode)? No NMIB in ICR = 1 and NMI? Yes No No NMI? Yes Yes No Level 15 interrupt? Yes Yes IMASK* = level 14 or lower? No Set interrupt source in INTEVT Yes Level 14 interrupt? Yes IMASK = level 13 or lower? No Yes Save SR to SSR; save PC to SPC No Level 1 interrupt? No Yes IMASK = level 0? No Set BL, MD, RB bits in SR to 1 Branch to exception handler Note: * IMASK: Interrupt mask bits in status register (SR) Figure 19.3 Interrupt Operation Flowchart Page 788 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 19.4.2 Section 19 Interrupt Controller (INTC) Multiple Interrupts When handling multiple interrupts, interrupt handling should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in the INTEVT register. The code in INTEVT can be used as a branch-offset for branching to the specific handler. 2. Clear the interrupt source in the corresponding interrupt handler. 3. Save SPC and SSR to the stack. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Set the BL bit in SR to 1. 7. Restore SSR and SPC from memory. 8. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. This enables the interrupt response time to be shortened for urgent processing. 19.4.3 Interrupt Masking with MAI Bit By setting the MAI bit to 1 in the ICR register, it is possible to mask interrupts while the NMI pin is low, irrespective of the BL and IMASK bits in the SR register. • In normal operation and sleep mode All interrupts are masked while the NMI pin is low. However, an NMI interrupt only is generated by a transition at the NMI pin. • In standby mode All interrupts are masked while the NMI pin is low, and an NMI interrupt is not generated by a transition at the NMI pin. Therefore, standby cannot be cleared by an NMI interrupt while the MAI bit is set to 1. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 789 of 1128 Section 19 Interrupt Controller (INTC) 19.5 SH7751 Group, SH7751R Group Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table 19.8. Table 19.8 Interrupt Response Time Number of States Item NMI RL Peripheral Modules Time for priority decision and SR mask bit comparison* 1Icyc + 4Bcyc 1Icyc + 7Bcyc 1Icyc + 2Bcyc Wait time until end of sequence being executed by CPU S – 1 (≥ 0) × Icyc S – 1 (≥ 0) × Icyc S – 1 (≥ 0) × Icyc Time from interrupt exception handling (save of SR and PC) until fetch of first instruction of exception handler is started 4 × Icyc 4 × Icyc 4 × Icyc Response time Total 5Icyc + 4Bcyc + (S – 1)Icyc 5Icyc + 7Bcyc + (S – 1)Icyc 5Icyc + 2Bcyc + (S – 1)Icyc Minimum case 13Icyc 19Icyc 9Icyc When Icyc: Bcyc = 2:1 Maximum case 36 + S Icyc 60 + S Icyc 20 + S Icyc When Icyc: Bcyc = 8:1 Notes Legend: Icyc: One cycle of internal clock supplied to CPU, etc. Bcyc: One CKIO cycle S: Latency of instruction Note: * In the SH7751, this includes the case where the mask bit (IMASK) in SR is changed and a new interrupt is generated. Page 790 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 19.6 Usage Notes 19.6.1 NMI Interrupts (SH7751 Only) Section 19 Interrupt Controller (INTC) When multiple NMI interrupts are input to the NMI pin within a set period of time (which is dependent on the internal state of the CPU and the external bus state), subsequent interrupts may not be accepted. Note that this problem does not occur when sufficient time*1 is provided between NMI interrupt inputs or with non-NMI interrupts such as IRL interrupts. Workarounds: Any of the following methods may be used to avoid the above problem. (1) Allow sufficient time between NMI interrupt inputs, as described in note 1, below. Note that it may not be possible to assure the above interval between NMI interrupt inputs if hazard is input to NMI, and that this may cause the device to malfunction. Design the external circuits so that no hazard is input via NMI.*2 (2) Do not use NMI interrupts. Use IRL interrupts instead. (3) Workaround using software The above problem can be avoided by inserting the following lines of code*3*4 into the NMI exception handling routine. Notes: 1. If SR.BL is cleared to 0 so that one or more instructions may be executed between the handling of two NMI interrupts. 2. When changing the level of the NMI input, ensure that the high and low durations are at least 5 CKIO cycles. Also ensure that no noise pulses occur before or after level changes. 3. If the NMI exception handling routine contains code that changes the value of the SR.BL bit, the code listed below should be inserted before the point at which the change is made. 4. Registers R0 to R3 in the code sample can be changed to any general register. Also, the necessary register save and restore instructions should be inserted before and after the code listed below, as appropriate. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 791 of 1128 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; R0 : tmp ;; R1 : Original SR ;; R2 : Original ICR ;; R3 : ICR Address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; NMIH: ; (1) Set SR.IMASK = H'F stc SR, R1 ; mov R1,R0 or #H'F0,R0 ldc R0, SR Store SR ; (2) Reverse ICR.NMIE mov.l #ICR, R3 mov.w @R3, R2 mov.w #H'0100, R0 xor R2, R0 mov.w R0, @R3 bra NMIH1 ; Store ICR ; Write ICR.NMIE inverted (dummy) @R3, R0 ; dummy read ; Write ICR.NMIE nop .pool .align 4 NMIH2: ; mov.w mov.w R2, @R3 stc SR, R0 ldc R0, SR ldc R0, SR ldc R0, SR ldc R0, SR ldc R0, SR ldc R0, SR ldc R0, SR ldc R0, SR Page 792 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group ldc R1, SR ; bra NMIH3 Section 19 Interrupt Controller (INTC) Restore SR nop NMIH1: bra NMIH2 nop NMIH3: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 793 of 1128 Section 19 Interrupt Controller (INTC) Page 794 of 1128 SH7751 Group, SH7751R Group R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Section 20 User Break Controller (UBC) 20.1 Overview The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU. This function makes it easy to design an effective selfmonitoring debugger, enabling programs to be debugged with the chip alone, without using an incircuit emulator. 20.1.1 Features The UBC has the following features. • Two break channels (A and B) User break interrupts can be generated on independent conditions for channels A and B, or on sequential conditions (sequential break setting: channel A → channel B). • The following can be set as break compare conditions: ⎯ Address (selection of 32-bit virtual address and ASID for comparison): Address: All bits compared/lower 10 bits masked/lower 12 bits masked/lower 16 bits masked/lower 20 bits masked/all bits masked ASID: All bits compared/all bits masked ⎯ Data (channel B only, 32-bit mask capability) ⎯ Bus cycle: Instruction access/operand access ⎯ Read/write ⎯ Operand size: Byte/word/longword/quadword • An instruction access cycle break can be effected before or after the instruction is executed. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 795 of 1128 Section 20 User Break Controller (UBC) 20.1.2 SH7751 Group, SH7751R Group Block Diagram Figure 20.1 shows a block diagram of the UBC. Access control Address bus Data bus Channel A Access comparator BBRA BARA Address comparator BASRA BAMRA Channel B Access comparator BBRB BARB Address comparator BASRB BAMRB Data comparator BDRB BDMRB Legend: BBRA: BARA: BASRA: BAMRA: BBRB: BARB: BASRB: BAMRB: BDRB: BDMRB: BRCR: Break bus cycle register A Break address register A Break ASID register A Break address mask register A Break bus cycle register B Break address register B Break ASID register B Break address mask register B Break data register B Break data mask register B Break control register Control BRCR User break trap request Figure 20.1 Block Diagram of User Break Controller Page 796 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Table 20.1 shows the UBC registers. Table 20.1 UBC Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Break address register A BARA R/W Undefined H'FF200000 H'1F200000 32 Break address mask register A BAMRA R/W Undefined H'FF200004 H'1F200004 8 Break bus cycle register A BBRA R/W H'0000 H'FF200008 H'1F200008 16 Break ASID register A BASRA R/W Undefined H'FF000014 H'1F000014 8 Break address register B BARB R/W Undefined H'FF20000C H'1F20000C 32 Break address mask register B BAMRB R/W Undefined H'FF200010 H'1F200010 8 Break bus cycle register B BBRB R/W H'0000 H'FF200014 H'1F200014 16 Break ASID register B BASRB R/W Undefined H'FF000018 H'1F000018 8 Break data register B BDRB R/W Undefined H'FF200018 H'1F200018 32 Break data mask register B BDMRB R/W Undefined H'FF20001C H'1F20001C 32 Break control register BRCR R/W H'0000* H'FF200020 H'1F200020 16 Note: * Some bits are not initialized. See section 20.2.12, Break Control Register (BRCR), for details. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 797 of 1128 Section 20 User Break Controller (UBC) 20.2 Register Descriptions 20.2.1 Access to UBC Registers SH7751 Group, SH7751R Group The access size must be the same as the control register size. If the sizes are different, a write will not be effected in a UBC register write operation, and a read operation will return an undefined value. UBC register contents cannot be transferred to a floating-point register using a floatingpoint memory load instruction. When a UBC register is updated, use either of the following methods to make the updated value valid: 1. Execute an RTE instruction after the memory store instruction that updated the register. The updated value will be valid from the RTE instruction jump destination onward. 2. Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. As the CPU executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted. The updated value will be valid from the 6th state onward. Page 798 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 20.2.2 Break Address Register A (BARA) Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Note: Section 20 User Break Controller (UBC) * 31 30 29 28 27 26 25 24 BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Undefined Break address register A (BARA) is a 32-bit readable/writable register that specifies the virtual address used in the channel A break conditions. BARA is not initialized by a power-on reset or manual reset. Bits 31 to 0—Break Address A31 to A0 (BAA31–BAA0): These bits hold the virtual address (bits 31–0) used in the channel A break conditions. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 799 of 1128 Section 20 User Break Controller (UBC) 20.2.3 Break ASID Register A (BASRA) Bit: Initial value: R/W: Note: SH7751 Group, SH7751R Group * 7 6 5 4 3 2 1 0 BASA7 BASA6 BASA5 BASA4 BASA3 BASA2 BASA1 BASA0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Undefined Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID used in the channel A break conditions. BASRA is not initialized by a power-on reset or manual reset. Bits 7 to 0—Break ASID A7 to A0 (BASA7–BASA0): These bits hold the ASID (bits 7–0) used in the channel A break conditions. 20.2.4 Break Address Mask Register A (BAMRA) Bit: 7 6 5 4 3 2 1 0 — — — — BAMA2 BASMA BAMA1 BAMA0 Initial value: 0 0 0 0 * * * * R/W: R R R R R/W R/W R/W R/W Note: * Undefined Break address mask register A (BAMRA) is an 8-bit readable/writable register that specifies which bits are to be masked in the break ASID set in BASRA and the break address set in BARA. BAMRA is not initialized by a power-on reset or manual reset. Bits 7 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 2—Break ASID Mask A (BASMA): Specifies whether all bits of the channel A break ASID (BASA7–BASA0) are to be masked. Bit 2: BASMA Description 0 All BASRA bits are included in break conditions 1 No BASRA bits are included in break conditions Page 800 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Bits 3, 1, and 0—Break Address Mask A2 to A0 (BAMA2–BAMA0): These bits specify which bits of the channel A break address (BAA31–BAA0) set in BARA are to be masked. Bit 3: BAMA2 Bit 1: BAMA1 Bit 0: BAMA0 Description 0 0 0 All BARA bits are included in break conditions 1 Lower 10 bits of BARA are masked, and not included in break conditions 0 Lower 12 bits of BARA are masked, and not included in break conditions 1 All BARA bits are masked, and not included in break conditions 0 Lower 16 bits of BARA are masked, and not included in break conditions 1 Lower 20 bits of BARA are masked, and not included in break conditions * Reserved (cannot be set) 1 1 0 1 Legend: * Don't care 20.2.5 Break Bus Cycle Register A (BBRA) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — SZA2 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W Break bus cycle register A (BBRA) is a 16-bit readable/writable register that sets three conditions—(1) instruction access/operand access, (2) read/write, and (3) operand size—from among the channel A break conditions. BBRA is initialized to H'0000 by a power-on reset. It retains its value in standby mode. Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 801 of 1128 Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group Bits 5 and 4—Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel A break conditions. Bit 5: IDA1 Bit 4: IDA0 0 1 Description 0 Condition comparison is not performed 1 Instruction access cycle is used as break condition (Initial value) 0 Operand access cycle is used as break condition 1 Instruction access cycle or operand access cycle is used as break condition Bits 3 and 2—Read/Write Select A (RWA1, RWA0): These bits specify whether a read cycle or write cycle is used as the bus cycle in the channel A break conditions. Bit 3: RWA1 Bit 2: RWA0 Description 0 0 Condition comparison is not performed 1 Read cycle is used as break condition 0 Write cycle is used as break condition 1 Read cycle or write cycle is used as break condition 1 (Initial value) Bits 6, 1, and 0—Operand Size Select A (SZA2–SZA0): These bits select the operand size of the bus cycle used as a channel A break condition. Bit 6: SZA2 Bit 1: SZA1 Bit 0: SZA0 Description 0 0 0 Operand size is not included in break conditions (Initial value) 1 Byte access is used as break condition 1 1 0 1 0 Word access is used as break condition 1 Longword access is used as break condition 0 Quadword access is used as break condition 1 Reserved (cannot be set) * Reserved (cannot be set) Legend: * Don't care Page 802 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 20.2.6 Section 20 User Break Controller (UBC) Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 20.2.7 Break ASID Register B (BASRB) BASRB is the channel B break ASID register. The bit configuration is the same as for BASRA. 20.2.8 Break Address Mask Register B (BAMRB) BAMRB is the channel B break address mask register. The bit configuration is the same as for BAMRA. 20.2.9 Break Data Register B (BDRB) Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Note: * 31 30 29 28 27 26 25 24 BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Undefined R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 803 of 1128 Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31– 0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or manual reset. Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be used in the channel B break conditions. 20.2.10 Break Data Mask Register B (BDMRB) Bit: 31 30 29 28 27 26 25 24 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 Initial value: R/W: Bit: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value: R/W: Bit: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 Initial value: R/W: Bit: Initial value: R/W: Note: * 8 BDMB8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Undefined Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on reset or manual reset. Page 804 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31–BDMB0): These bits specify whether the corresponding bit of the channel B break data (BDB31–BDB0) set in BDRB is to be masked. Bit 31–0: BDMBn Description 0 Channel B break data bit BDBn is included in break conditions 1 Channel B break data bit BDBn is masked, and not included in break conditions Notes: n = 31 to 0 When the data bus value is included in the break conditions, the operand size should be specified. When byte size is specified, set the same data in bits 15–8 and 7–0 of BDRB and BDMRB. 20.2.11 Break Bus Cycle Register B (BBRB) BBRB is the channel B bus break register. The bit configuration is the same as for BBRA. 20.2.12 Break Control Register (BRCR) Bit: Initial value: R/W: Bit: Initial value: R/W: Note: * 15 14 13 12 11 10 9 8 CMFA CMFB — — — PCBA — — 0 0 0 0 0 * 0 0 R/W R/W R R R R/W R R 7 6 5 4 3 2 1 0 DBEB PCBB — — SEQ — — UBDE * * 0 0 * 0 0 0 R/W R/W R R R/W R R R/W Undefined The break control register (BRCR) is a 16-bit readable/writable register that specifies (1) whether channels A and B are to be used as two independent channels or in a sequential condition, (2) whether the break is to be effected before or after instruction execution, (3) whether the BDRB register is to be included in the channel B break conditions, and (4) whether the user break debug function is to be used. BRCR also contains condition match flags. The CMFA, CMFB, and UBDE bits in BRCR are initialized to 0 by a power-on reset, but retain their value in standby mode. The value of the PCBA, DBEB, PCBB, and SEQ bits is undefined after a power-on reset or manual reset, so these bits should be initialized by software as necessary. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 805 of 1128 Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group Bit 15—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write). Bit 15: CMFA Description 0 Channel A break condition is not matched 1 Channel A break condition match has occurred (Initial value) Bit 14—Condition Match Flag B (CMFB): Set to 1 when a break condition set for channel B is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write). Bit 14: CMFB Description 0 Channel B break condition is not matched 1 Channel B break condition match has occurred (Initial value) Bits 13 to 11—Reserved: These bits are always read as 0, and should only be written with 0. Bit 10—Instruction Access Break Select A (PCBA): Specifies whether a channel A instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 10: PCBA Description 0 Channel A PC break is effected before instruction execution 1 Channel A PC break is effected after instruction execution Bits 9 and 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Data Break Enable B (DBEB): Specifies whether the data bus condition is to be included in the channel B break conditions. This bit is not initialized by a power-on reset or manual reset. Bit 7: DBEB Description 0 Data bus condition is not included in channel B conditions 1 Data bus condition is included in channel B conditions Note: When the data bus is included in the break conditions, bits IDB1–0 in break bus cycle register B (BBRB) should be set to 10 or 11. Page 806 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Bit 6—PC Break Select B (PCBB): Specifies whether a channel B instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 6: PCBB Description 0 Channel B PC break is effected before instruction execution 1 Channel B PC break is effected after instruction execution Bits 5 and 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Sequence Condition Select (SEQ): Specifies whether the conditions for channels A and B are to be independent or sequential. This bit is not initialized by a power-on reset or manual reset. Bit 3: SEQ Description 0 Channel A and B comparisons are performed as independent conditions 1 Channel A and B comparisons are performed as sequential conditions (channel A → channel B) Bits 2 and 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0—User Break Debug Enable (UBDE): Specifies whether the user break debug function (see section 20.4, User Break Debug Support Function) is to be used. Bit 0: UBDE Description 0 User break debug function is not used 1 User break debug function is used R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 (Initial value) Page 807 of 1128 Section 20 User Break Controller (UBC) 20.3 Operation 20.3.1 Explanation of Terms Relating to Accesses SH7751 Group, SH7751R Group An instruction access is an access that obtains an instruction. For example, the fetching of an instruction from the branch destination when a branch instruction is executed is an instruction access. An operand access is any memory access for the purpose of instruction execution. For example, the access to address PC+disp×2+4 in the instruction MOV.W@(disp,PC), Rn is an operand access. As the term “data” is used to distinguish data from an address, the term “operand access” is used in this section. In this LSI, all operand accesses are treated as either read accesses or write accesses. The following instructions require special attention: • PREF, OCBP, and OCBWB instructions: Treated as read accesses. • MOVCA.L and OCBI instructions: Treated as write accesses. • TAS.B instruction: Treated as one read access and one write access. The operand accesses for the PREF, OCBP, OCBWB, and OCBI instructions are accesses with no access data. This LSI handles all operand accesses as having a data size. The data size can be byte, word, longword, or quadword. The operand data size for the PREF, OCBP, OCBWB, MOVCA.L, and OCBI instructions is treated as longword. 20.3.2 Explanation of Terms Relating to Instruction Intervals In this section, “1 (2, 3, ...) instruction(s) after...”, as a measure of the distance between two instructions, is defined as follows. A branch is counted as an interval of two instructions. • Example of sequence of instructions with no branch: 100 Instruction A (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A) 104 Instruction C (2 instructions after instruction A) 106 Instruction D (3 instructions after instruction A) Page 808 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) • Example of sequence of instructions with a branch (however, the example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch instruction is the instruction itself + 4): 100 Instruction A: BT/S L200 (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B) L200 200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B) 202 Instruction D (4 instructions after instruction A, 3 instructions after instruction B) 20.3.3 User Break Operation Sequence The sequence of operations from setting of break conditions to user break exception handling is described below. 1. Specify pre- or post-execution breaking in the case of an instruction access, inclusion or exclusion of the data bus value in the break conditions in the case of an operand access, and use of independent or sequential channel A and B break conditions, in the break control register (BRCR). Set the break addresses in the break address registers for each channel (BARA, BARB), the ASIDs corresponding to the break space in the break ASID registers (BASRA, BASRB), and the address and ASID masking methods in the break address mask registers (BAMRA, BAMRB). If the data bus value is to be included in the break conditions, also set the break data in the break data register (BDRB) and the data mask in the break data mask register (BDMRB). 2. Set the break bus conditions in the break bus cycle registers (BBRA, BBRB). If even one of the BBRA/BBRB instruction access/operand access select (ID bit) and read/write select groups (RW bit) is set to 00, a user break interrupt will not be generated on the corresponding channel. Make the BBRA and BBRB settings after all other break-related register settings have been completed. If breaks are enabled with BBRA/BBRB while the break address, data, or mask register, or the break control register is in the initial state after a reset, a break may be generated inadvertently. 3. The operation when a break condition is satisfied depends on the BL bit (in the CPU's SR register). When the BL bit is 0, exception handling is started and the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition. When the BL bit is 1, the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition but exception handling is not started. The condition match flags (CMFA, CMFB) are set by a branch condition match, but are not reset. Therefore, a memory store instruction should be used on the BRCR register to clear the R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 809 of 1128 Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group flags to 0. See section 20.3.6, Condition Match Flag Setting, for the exact setting conditions for the condition match flags. 4. When sequential condition mode has been selected, and the channel B condition is matched after the channel A condition has been matched, a break is effected at the instruction at which the channel B condition was matched. See section 20.3.8, Contiguous A and B Settings for Sequential Conditions, for the operation when the channel A condition match and channel B condition match occur close together. With sequential conditions, only the channel B condition match flag is set. When sequential condition mode has been selected, if it is wished to clear the channel A match when the channel A condition has been matched but the channel B condition has not yet been matched, this can be done by writing 0 to the SEQ bit in the BRCR register. 20.3.4 Instruction Access Cycle Break 1. When an instruction access/read/word setting is made in the break bus cycle register (BBRA/BBRB), an instruction access cycle can be used as a break condition. In this case, breaking before or after execution of the relevant instruction can be selected with the PCBA/PCBB bit in the break control register (BRCR). When an instruction access cycle is used as a break condition, clear the LSB of the break address registers (BARA, BARB) to 0. A break will not be generated if this bit is set to 1. 2. When a pre-execution break is specified, the break is effected when it is confirmed that the instruction is to be fetched and executed. Therefore, overrun-fetched instructions (instructions that are fetched but not executed when a branch or exception occurs) cannot be used in a break. However, if a TLB miss or TLB protection violation exception occurs at the time of the fetch of instructions subject to a break, the break exception handling is carried out first. The instruction TLB exception handling is performed when the instruction is re-executed (see section 5.4, Exception Types and Priorities). Also, since a delayed branch instruction and the delay slot instruction are executed as a single instruction, if a pre-execution break is specified for a delay slot instruction, the break will be effected before execution of the delayed branch instruction. However, a pre-execution break cannot be specified for the delay slot instruction for an RTE instruction. 3. With a post-execution break, the instruction set as a break condition is executed, then a break interrupt is generated before the next instruction is executed. When a post-execution break is set for a delayed branch instruction, the delay slot is executed and the break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). Page 810 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) 4. When an instruction access cycle is set for channel B, break data register B (BDRB) is ignored in judging whether there is an instruction access match. Therefore, a break condition specified by the DBEB bit in BRCR is not executed. 20.3.5 Operand Access Cycle Break 1. In the case of an operand access cycle break, the bits included in address bus comparison vary as shown below according to the data size specification in the break bus cycle register (BBRA/BBRB). Data Size Address Bits Compared Quadword (100) Address bits A31–A3 Longword (011) Address bits A31–A2 Word (010) Address bits A31–A1 Byte (001) Address bits A31–A0 Not included in condition (000) In quadword access, address bits A31–A3 In longword access, address bits A31–A2 In word access, address bits A31–A1 In byte access, address bits A31–A0 2. When data bus is included in break conditions in channel B When a data value is included in the break conditions, set the DBEB bit in the break control register (BRCR) to 1. In this case, break data register B (BDRB) and break data mask register B (BDMRB) settings are necessary in addition to the address condition. A user break interrupt is generated when all three conditions—address, ASID, and data—are matched. When a quadword access occurs, the 64-bit access data is divided into an upper 32 bits and lower 32 bits, and interpreted as two 32-bit data units. A break is generated if either of the 32-bit data units satisfies the data match condition. Set the IDB1–0 bits in break bus cycle register B (BBRB) to 10 or 11. When byte data is specified, the same data should be set in the two bytes comprising bits 15–8 and bits 7–0 in break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31–16 of BDRB and BDMRB are ignored. 3. When the DBEB bit in the break control register (BRCR) is set to 1, a break is not generated by an operand access with no access data (an operand access in a PREF, OCBP, OCBWB, or OCBI instruction). R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 811 of 1128 Section 20 User Break Controller (UBC) 20.3.6 SH7751 Group, SH7751R Group Condition Match Flag Setting 1. Instruction access with post-execution condition, or operand access The flag is set when execution of the instruction that causes the break is completed. As an exception to this, however, in the case of an instruction with more than one operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed. Example 1: 100 BT L200 (branch performed) 102 Instruction (operand access break on channel A) → flag not set Example 2: 110 FADD (FPU exception) 112 Instruction (operand access break on channel A) → flag not set 2. Instruction access with pre-execution condition The flag is set when the break match condition is detected. Example 1: 110 Instruction (pre-execution break on channel A) → flag set 112 Instruction (pre-execution break on channel B) → flag not set Example 2: 110 Instruction (pre-execution break on channel B, instruction access TLB miss) → flag set 20.3.7 Program Counter (PC) Value Saved 1. When instruction access (pre-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction at which the break condition match occurred. In this case, a user break interrupt is generated and the fetched instruction is not executed. 2. When instruction access (post-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction to be executed after the instruction at which the break condition match occurred. In this case, the fetched instruction is executed, and a user break interrupt is generated before execution of the next instruction. 3. When an instruction access (post-execution) break condition is set for a delayed branch instruction, the delay slot instruction is executed and a user break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). In this case, the PC Page 812 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) value saved to SPC is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made). 4. When operand access (address only) is set as a break condition, the address of the instruction to be executed after the instruction at which the condition match occurred is saved to SPC. 5. When operand access (address + data) is set as a break condition, execution of the instruction at which the condition match occurred is completed. A user break interrupt is generated before execution of instructions from one instruction later to four instructions later. It is not possible to specify at which instruction, from one later to four later, the interrupt will be generated. The start address of the instruction after the instruction for which execution is completed at the point at which user break interrupt handling is started is saved to SPC. If an instruction between one instruction later and four instructions later causes another exception, control is performed as follows. Designating the exception caused by the break as exception 1, and the exception caused by an instruction between one instruction later and four instructions later as exception 2, memory updating and register updating that essentially cannot be performed by exception 2 cannot be performed is guaranteed irrespective of the existence of exception 1. The program counter value saved is the address of the first instruction for which execution is suppressed. Whether exception 1 or exception 2 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT) is not guaranteed. However, if exception 2 is from a source not synchronized with an instruction (external interrupt or peripheral module interrupt), exception 1 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT). 20.3.8 Contiguous A and B Settings for Sequential Conditions When channel A match and channel B match timings are close together, a sequential break may not be guaranteed. Rules relating to the guaranteed range are given below. 1. Instruction access matches on both channel A and channel B Instruction B is 0 instructions after instruction A Equivalent to setting the same address. Do not use this setting Instruction B is 1 instruction after instruction A Sequential operation is not guaranteed Instruction B is 2 or more instructions after instruction A Sequential operation is guaranteed R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 813 of 1128 Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group 2. Instruction access match on channel A, operand access match on channel B Instruction B is 0 or 1 instruction after instruction A Sequential operation is not guaranteed Instruction B is 2 or more instructions after instruction A Sequential operation is guaranteed 3. Operand access match on channel A, instruction access match on channel B Instruction B is 0 to 3 instructions after instruction A Sequential operation is not guaranteed Instruction B is 4 or more instructions after instruction A Sequential operation is guaranteed 4. Operand access matches on both channel A and channel B Do not make a setting such that a single operand access will match the break conditions of both channel A and channel B. There are no other restrictions. For example, sequential operation is guaranteed even if two accesses within a single instruction match channel A and channel B conditions in turn. 20.3.9 Usage Notes 1. Do not execute a post-execution instruction access break for the SLEEP instruction. 2. Do not make an operand access break setting between 1 and 3 instructions before a SLEEP instruction. 3. The value of the BL bit referenced in a user break exception depends on the break setting, as follows. a. Pre-execution instruction access break: The BL bit value before the executed instruction is referenced. b. Post-execution instruction access break: The OR of the BL bit values before and after the executed instruction is referenced. c. Operand access break (address/data): The BL bit value after the executed instruction is referenced. d. In the case of an instruction that modifies the BL bit Page 814 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) SL.BL PreExecution Instruction Access PostExecution Instruction Access PreExecution Instruction Access PostExecution Instruction Access Operand Access (Address/Data) 0→0 A A A A A 1→0 M M M M A 0→1 A M A M M 1→1 M M M M M Legend: A: Accepted M: Masked e. In the case of an RTE delay slot The BL bit value before execution of a delay slot instruction is the same as the BL bit value before execution of an RTE instruction. The BL bit value after execution of a delay slot instruction is the same as the first BL bit value for the first instruction executed on returning by means of an RTE instruction (the same as the value of the BL bit in SSR before execution of the RTE instruction). f. If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit before execution of the first instruction of the exception handling routine is 1. 4. If channels A and B both match independently at virtually the same time, and, as a result, the SPC value is the same for both user break interrupts, only one user break interrupt is generated, but both the CMFA bit and the CMFB bit are set. For example: 110 Instruction (post-execution instruction break on channel A) → SPC = 112, CMFA = 1 112 Instruction (pre-execution instruction break on channel B) → SPC = 112, CMFB = 1 5. The PCBA or PCBB bit in BRCR is valid for an instruction access break setting. 6. When the SEQ bit in BRCR is 1, the internal sequential break state is initialized by a channel B condition match. For example: A → A → B (user break generated) → B (no break generated) 7. In the event of contention between a re-execution type exception and a post-execution break in a multistep instruction, the re-execution type exception is generated. In this case, the CMF bit may or may not be set to 1 when the break condition occurs. 8. A post-execution break is classified as a completion type exception. Consequently, in the event of contention between a completion type exception and a post-execution break, the postexecution break is suppressed in accordance with the priorities of the two events. For example, R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 815 of 1128 Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group in the case of contention between a TRAPA instruction and a post-execution break, the user break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break condition. 20.4 User Break Debug Support Function The user break debug support function enables the processing used in the event of a user break exception to be changed. When a user break exception occurs, if the UBDE bit is set to 1 in the BRCR register, the DBR register value will be used as the branch destination address instead of [VBR + offset]. The value of R15 is saved in the SGR register regardless of the value of the UBDE bit in the BRCR register or the kind of exception event. A flowchart of the user break debug support function is shown in figure 20.2. Page 816 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Exception/interrupt generation Hardware operation SPC ← PC SSR ← SR SR.BL ← B'1 SR.MD ← B'1 SR.RB ← B'1 Exception Exception/ interrupt/trap? Trap Interrupt EXPEVT ← exception code INTEVT ← interrupt code EXPEVT ← H'160 TRA ← TRAPA (imm) SGR ← R15 No Yes Reset exception? (BRCR.UBDE == 1) && (user break exception)? Yes No PC ← DBR PC ← VBR + vector offset Debug program Exception handling routine PC ← H'A0000000 R15 ← SGR (STC instruction) Execute RTE instruction PC ← SPC SR ← SSR End of exception operations Figure 20.2 User Break Debug Support Function Flowchart R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 817 of 1128 Section 20 User Break Controller (UBC) 20.5 SH7751 Group, SH7751R Group Examples of Use Instruction Access Cycle Break Condition Settings • Register settings: BASRA = H'80 / BARA = H'00000404 / BAMRA = H'00 / BBRA = H'0014 / BASRB = H'70 / BARB = H'00008010 / BAMRB = H'01 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0400 Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00000404 / address mask: H'00 Bus cycle: instruction access (post-instruction-execution), read (operand size not included in conditions) ⎯ Channel B: ASID: H'70 / address: H'00008010 / address mask: H'01 Data: H'00000000 / data mask: H'00000000 Bus cycle: instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break is generated after execution of the instruction at address H'00000404 with ASID = H'80, or before execution of an instruction at addresses H'00008000–H'000083FE with ASID = H'70. • Register settings: BASRA = H'80 / BARA = H'00037226 / BAMRA = H'00 / BBRA = H'0016 / BASRB = H'70 / BARB = H'0003722E / BAMRB = H'00 / BBRB = H'0016 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0008 Conditions set: Channel A → channel B sequential mode ⎯ Channel A: ASID: H'80 / address: H'00037226 / address mask: H'00 Bus cycle: instruction access (pre-instruction-execution), read, word ⎯ Channel B: ASID: H'70 / address: H'0003722E / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: instruction access (pre-instruction-execution), read, word The instruction at address H'00037266 with ASID = H'80 is executed, then a user break is generated before execution of the instruction at address H'0003722E with ASID = H'70. • Register settings: BASRA = H'80 / BARA = H'00027128 / BAMRA = H'00 / BBRA = H'001A / BASRB = H'70 / BARB = H'00031415 / BAMRB = H'00 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0000 Page 818 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00027128 / address mask: H'00 Bus cycle: CPU, instruction access (pre-instruction-execution), write, word ⎯ Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break interrupt is not generated on channel A since the instruction access is not a write cycle. A user break interrupt is not generated on channel B since instruction access is performed on an even address. Operand Access Cycle Break Condition Settings • Register settings: BASRA = H'80 / BARA = H'00123456 / BAMRA = H'00 / BBRA = H'0024 / BASRB = H'70/ BARB = H'000ABCDE / BAMRB = H'02 / BBRB = H'002A / BDRB = H'0000A512 / BDMRB = H'00000000 / BRCR = H'0080 Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00123456 / address mask: H'00 Bus cycle: operand access, read (operand size not included in conditions) ⎯ Channel B: ASID: H'70 / address: H'000ABCDE / address mask: H'02 Data: H'0000A512 / data mask: H'00000000 Bus cycle: operand access, write, word Data break enabled On channel A, a user break interrupt is generated in the event of a longword read at address H'00123454, a word read at address H'00123456, or a byte read at address H'00123456, with ASID = H'80. On channel B, a user break interrupt is generated when H'A512 is written by word access to any address from H'000AB000 to H'000ABFFE with ASID = H'70. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 819 of 1128 Section 20 User Break Controller (UBC) 20.6 SH7751 Group, SH7751R Group User Break Controller Stop Function This function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating. Note that, if you use this function, you cannot use the user break controller. 20.6.1 Transition to User Break Controller Stopped State Setting the MSTP5 bit of the STBCR2 (inside the CPG) to 1 stops the clock supply and causes the user break controller to enter the stopped state. Follow steps (1) to (5) below to set the MSTP5 bit to 1 and enter the stopped state. (1) Initialize BBRA and BBRB to 0; (2) Initialize BRCR to 0; (3) Make a dummy read of BRCR; (4) Read STBCR2, then set the MSTP5 bit in the read data to 1 and write back. (5) Make two dummy reads of STBCR2. Make sure that, if an exception or interrupt occurs while performing steps (1) to (5), you do not change the values of these registers in the exception handling routine. Do not read or write the following registers while the user break controller clock is stopped: BARA, BAMRA, BBRA, BARB, BAMRB, BBRB, BDRB, BDMRB, and BRCR. If these registers are read or written, the value cannot be guaranteed. 20.6.2 Cancelling the User Break Controller Stopped State The clock supply can be restarted by setting the MSTP5 bit of STBCR2 (inside the CPG) to 0. The user break controller can then be operated again. Follow steps (6) and (7) below to clear the MSTP5 bit to 0 to cancel the stopped state. (6) Read STBCR2, then clear the MSTP5 bit in the read data to 0 and write the modified data back; (7) Make two dummy reads of STBGR2. As with the transition to the stopped state, if an exception or interrupt occurs while processing steps (6) and (7), make sure that the values in these registers are not changed in the exception handling routine. Page 820 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 20.6.3 Section 20 User Break Controller (UBC) Examples of Stopping and Restarting the User Break Controller The following are example programs: ; Transition to user break controller stopped state ; (1) Initialize BBRA and BBRB to 0. mov #0, R0 mov.l #BBRA, R1 mov.w R0, @R1 mov.l #BBRB, R1 mov.w R0, @R1 ; (2) Initialize BRCR to 0. mov.l #BRCR, R1 mov.w R0, @R1 ; (3) Dummy read BRCR. mov.w @R1, R0 ; (4) Read STBCR2, then set MSTP5 bit in the read data to 1 and write it back mov.l #STBCR2, R1 mov.b @R1, R0 or #H'1, R0 mov.b R0, @R1 ; (5) Twice dummy read STBCR2. mov.b @R1, R0 mov.b @R1, R0 ; Canceling user break controller stopped state ; (6) Read STBCR2, then clear MSTP5 bit in the read data to 0 and write it back mov.l #STBCR2, R1 mov.b @R1, R0 and #H'FE, R0 mov.b R0, @R1 ; (7) Twice dummy read STBCR2. mov.b @R1, R0 mov.b @R1, R0 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 821 of 1128 Section 20 User Break Controller (UBC) Page 822 of 1128 SH7751 Group, SH7751R Group R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) Section 21 High-performance User Debug Interface (H-UDI) 21.1 Overview 21.1.1 Features The high-performance user debug interface (H-UDI) is a serial input/output interface supporting a subset of the JTAG, IEEE 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. This LSI H-UDI support boundary-scan, and is used for emulator connection. The functions of this interface should not be used when using an emulator. Refer to the emulator manual for the method of connecting the emulator. The H-UDI uses six pins (TCK, TMS, TDI, TDO, TRST, and ASEBRK/BRKACK). In this LSI, six dedicated emulator pins have been added (AUDSYNC, AUDCK, and AUDATA3 to AUDATA0). The pin functions and serial transfer protocol conform to the JTAG specifications. 21.1.2 Block Diagram Figure 21.1 shows a block diagram of the H-UDI. The TAP (test access port) controller and control registers are reset independently of the chip reset pin by driving the TRST pin low or setting TMS to 1 and applying TCK for at least five clock cycles. The other circuits are reset and initialized in an ordinary reset. The H-UDI circuit has six internal registers: SDBPR, SDBSR, SDIR, SDINT, SDDRH, and SDDRL (these last two together designated SDDR). The SDBPR register supports the JTAG bypass mode, SDBSR is a shift register forming a JTAG boundary scan, SDIR is the command register, SDDR is the data register, and SDINT is the H-UDI interrupt register. SDIR can be accessed directly from the TDI and TDO pins. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 823 of 1128 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Interrupt/reset etc. Break control ASEBRK/BRKACK TCK TAP controller TMS Decoder TDI Shift register SDBPR SDBSR SDIR SDINT SDDRH SDDRL TDO Peripheral module bus TRST MUX AUDSYNC AUDCK Trace control AUDATA3–0 Figure 21.1 Block Diagram of H-UDI Circuit Page 824 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 21.1.3 Section 21 High-performance User Debug Interface (H-UDI) Pin Configuration Table 21.1 shows the H-UDI pin configuration. Table 21.1 H-UDI Pins Pin Name Abbreviation I/O Function When Not Used Clock pin TCK Input Same as the JTAG serial clock input Open* pin. Data is transferred from data input pin TDI to the H-UDI circuit, and data is read from data output pin TDO, in synchronization with this signal. Mode pin TMS Input 1 The mode select input pin. Changing Open* this signal in synchronization with TCK determines the meaning of the data input from TDI. The protocol conforms to the JTAG (IEEE Std 1149.1) specification. Reset pin TRST Input 2, 3 The input pin that resets the H-UDI. * * This signal is received asynchronously with respect to TCK, and effects a reset of the JTAG interface circuit when low. TRST must be driven low for a certain period when powering on, regardless of whether or not JTAG is used. This differs from the IEEE specification. Data input pin TDI Input The data input pin. Data is sent to the H-UDI circuit by changing this signal in synchronization with TCK. Data output pin TDO Output The data output pin. Data is sent to the Open H-UDI circuit by reading this signal in synchronization with TCK. Emulator pin ASEBRK/ BRKACK Input/ output AUDSYNC Output Dedicated emulator pin 1 Dedicated emulator pin Open*1 Open*1 Open AUDCK AUDATA3– AUDATA0 Notes: 1. Pulled up inside the chip. When designing a board that allows use of an emulator, or when using interrupts and resets via the H-UDI, there is no problem in connecting a pullup resistance externally. 2. When designing a board that enables the use of an emulator, or when using interrupts and resets via the H-UDI, drive TRST low for a period overlapping RESET at power-on, and also provide for control by TRST alone. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 825 of 1128 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group 3. Fixed to the ground or connected to the same signal line as RESET, or to a signal line that behaves in the same way. However, there is a problem when this pin is fixed to the ground. TRST is pulled up in the chip so, when this pin is fixed to the ground via external connection, a minute current will flow. The size of this current is determined by the rating of the pull-up resistor. Although this current has no effect on the chip's operation, unnecessary current will be dissipated. The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or this LSI CPG setting so that the TCK frequency is lower than that of this LSI's peripheral module clock. 21.1.4 Register Configuration Table 21.2 shows the H-UDI registers. Except for SDBPR and SDBSR, these registers are mapped in the control register space and can be referenced by the CPU. Table 21.2 H-UDI Registers CPU Side H-UDI Side R/W Access Initial 1 Size Value* H'FFFF R/W 32 H'FFFFFFFD (Fixed 2 value* ) SDDR/ R/W H'FFF00008 H'1FF00008 32/16 SDDRH Undefined — — — Data register L SDDRL R/W H'FFF0000A H'1FF0000A 16 Undefined — — — Bypass register SDBPR — Undefined R/W 1 — Interrupt factor register SDINT H'0000 W* 32 H'00000000 Boundary scan register SDBSR — Undefined R/W — Undefined Abbreviation P4 R/W Address Instruction register SDIR R Data register H Name Area 7 Address Access Initial 1 Size Value* H'FFF00000 H'1FF00000 16 — — — R/W H'FFF00014 H'1FF00014 16 — — — 3 Notes: 1. Initialized when the TRST pin goes low or when the TAP is in the Test-Logic-Reset state. 2. The value read from H-UDI is fixed (H'FFFFFFFD). 3. 1 can be written to the LSB using the H-UDI interrupt command. Page 826 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) 21.2 Register Descriptions 21.2.1 Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is initialized by the TRST pin or in the TAP Test-Logic-Reset state. When this register is written to from the H-UDI, writing is possible regardless of the CPU mode. Operation is undefined if a reserved command is set in this register. Bit: 15 14 13 12 11 10 9 8 TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R R R R R Bits 15 to 8—Test Instruction Bits (TI7–TI0) Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9: TI7 TI6 TI5 TI4 TI3 TI2 TI1 Bit 8: TI0 Description 0 0 0 0 0 0 0 0 EXTEST 0 0 0 0 0 1 0 0 SAMPLE/PRELOAD 0 1 1 0 — — — — H-UDI reset negate 0 1 1 1 — — — — H-UDI reset assert 1 0 1 — — — — — H-UDI interrupt 1 1 1 1 1 1 1 1 Bypass mode (Initial value) Other than above Reserved Bits 7 to 0—Reserved: These bits are always read as 1, and should only be written with 1. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 827 of 1128 Section 21 High-performance User Debug Interface (H-UDI) 21.2.2 SH7751 Group, SH7751R Group Data Register (SDDR) The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and SDDRL, that can be read and written to by the CPU. The value in this register is initialized by TRST, but not by a CPU reset. Bit: 31 30 29 28 27 26 25 24 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: R/W: R/W: Note: * Undefined Bits 31 to 0—DR Data: These bits store the SDDR value. 21.2.3 Bypass Register (SDBPR) The bypass register (SDBPR) is a one-bit register that cannot be accessed by the CPU. When bypass mode is set in SDIR, SDBPR is connected between the TDI pin and TDO pin of the H-UDI. Page 828 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 21.2.4 Section 21 High-performance User Debug Interface (H-UDI) Interrupt Factor Register (SDINT) The interrupt factor register (SDINT) is a 16-bit register that can be read/written from the CPU. When a (H-UDI interrupt) command is set in the SDIR (Update-IR) via the H-UDI pin, the INTREQ bit is set to 1. While SDIR has the “H-UDI interrupt” command, the SDINT register is connected between H-UDI pins TDI and TDO, and can be read as a 32-bit register. The high 16 bits are 0 and the low 16 bits are SDINT. Only 0 can be written to the INTREQ bit from the CPU. While this bit is 1, the interrupt request continues to be generated, and must therefore be cleared to 0 by the interrupt handler. This register is initialized by TRST or when in the Test Logic Reset state. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — INTREQ Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bits 15 to 1— Reserved: These bits always read as 0, and should only be written with 0. Bit 0—Interrupt Request Bit (INTREQ): Shows the existence of an interrupt request from the “H-UDI interrupt” command. The interrupt request can be cleared by writing 0 to this bit from the CPU. When 1 is written to this bit, the existing value is retained. 21.2.5 Boundary Scan Register (SDBSR) The boundary scan register (SDBSR) is a shift register that is placed on the pads to control the chip's I/O pins. This register can perform a boundary scan test equivalent to the JTAG (IEEE Std 1149.1) standard using EXTEST, SAMPLE, and PRELOAD commands. Table 21.3 shows the relationship between this LSI pins and the boundary scan register. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 829 of 1128 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Table 21.3 Structure of Boundary Scan Register No. Pin name Type 418 CS0 OUT 417 CS0 CTL 416 CS1 OUT 415 CS1 CTL 414 CS4 OUT 413 CS4 CTL 412 CS5 OUT 411 CS5 CTL 410 CS6 OUT 409 CS6 CTL 408 BS OUT 407 BS CTL 406 WE0/REG OUT 405 WE0/REG CTL 404 WE1 OUT 403 WE1 CTL 402 D0 OUT 401 D0 CTL 400 D0 IN 399 D1 OUT 398 D1 CTL 397 D1 IN 396 D2 OUT 395 D2 CTL 394 D2 IN 393 D3 OUT 392 D3 CTL 391 D3 IN 390 D4 OUT 389 D4 CTL to TDO Page 830 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) No. Pin name Type 388 D4 IN 387 D5 OUT 386 D5 CTL 385 D5 IN 384 D6 OUT 383 D6 CTL 382 D6 IN 381 D7 OUT 380 D7 CTL 379 D7 IN 378 D8 OUT 377 D8 CTL 376 D8 IN 375 D9 OUT 374 D9 CTL 373 D9 IN 372 D10 OUT 371 D10 CTL 370 D10 IN 369 D11 OUT 368 D11 CTL 367 D11 IN 366 D12 OUT 365 D12 CTL 364 D12 IN 363 D13 OUT 362 D13 CTL 361 D13 IN 360 D14 OUT 359 D14 CTL 358 D14 IN 357 D15 OUT 356 D15 CTL R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 831 of 1128 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group No. Pin name Type 355 D15 IN 354 CAS0/DQM0 OUT 353 CAS0/DQM0 CTL 352 CAS1/DQM1 OUT 351 CAS1/DQM1 CTL 350 RD/WR OUT 349 RD/WR CTL 348 RD/CASS/FRAME OUT 347 RD/CASS/FRAME CTL 346 CKE OUT 345 CKE CTL 344 RAS OUT 343 RAS CTL 342 CS2 OUT 341 CS2 CTL 340 CS3 OUT 339 CS3 CTL 338 A0 OUT 337 A0 CTL 336 A1 OUT 335 A1 CTL 334 A2 OUT 333 A2 CTL 332 A3 OUT 331 A3 CTL 330 A4 OUT 329 A4 CTL 328 A5 OUT 327 A5 CTL 326 A6 OUT 325 A6 CTL 324 A7 OUT 323 A7 CTL Page 832 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) No. Pin name Type 322 A8 OUT 321 A8 CTL 320 A9 OUT 319 A9 CTL 318 A10 OUT 317 A10 CTL 316 A11 OUT 315 A11 CTL 314 A12 OUT 313 A12 CTL 312 A13 OUT 311 A13 CTL 310 A14 OUT 309 A14 CTL 308 A15 OUT 307 A15 CTL 306 A16 OUT 305 A16 CTL 304 A17 OUT 303 A17 CTL 302 CAS2/DQM2 OUT 301 CAS2/DQM2 CTL 300 CAS3/DQM3 OUT 299 CAS3/DQM3 CTL 298 D16 OUT 297 D16 CTL 296 D16 IN 295 D17 OUT 294 D17 CTL 293 D17 IN 292 D18 OUT 291 D18 CTL 290 D18 IN R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 833 of 1128 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group No. Pin name Type 289 D19 OUT 288 D19 CTL 287 D19 IN 286 D20 OUT 285 D20 CTL 284 D20 IN 283 D21 OUT 282 D21 CTL 281 D21 IN 280 D22 OUT 279 D22 CTL 278 D22 IN 277 D23 OUT 276 D23 CTL 275 D23 IN 274 D24 OUT 273 D24 CTL 272 D24 IN 271 D25 OUT 270 D25 CTL 269 D25 IN 268 D26 OUT 267 D26 CTL 266 D26 IN 265 D27 OUT 264 D27 CTL 263 D27 IN 262 D28 OUT 261 D28 CTL 260 D28 IN 259 D29 OUT 258 D29 CTL 257 D29 IN Page 834 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) No. Pin name Type 256 D30 OUT 255 D30 CTL 254 D30 IN 253 D31 OUT 252 D31 CTL 251 D31 IN 250 A18 OUT 249 A18 CTL 248 A19 OUT 247 A19 CTL 246 A20 OUT 245 A20 CTL 244 A21 OUT 243 A21 CTL 242 A22 OUT 241 A22 CTL 240 A23 OUT 239 A23 CTL 238 A24 OUT 237 A24 CTL 236 A25 OUT 235 A25 CTL 234 WE2/ICIORD OUT 233 WE2/ICIORD CTL 232 WE3/ICIOWR OUT 231 WE3/ICIOWR CTL 230 SLEEP IN 229 PCIGNT4 OUT 228 PCIGNT4 CTL 227 PCIGNT3 OUT 226 PCIGNT3 CTL 225 PCIGNT2 OUT 224 PCIGNT2 CTL R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 835 of 1128 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group No. Pin name Type 223 PCIREQ4 OUT 222 PCIREQ4 CTL 221 PCIREQ4 IN 220 PCIREQ3/MD10 OUT 219 PCIREQ3/MD10 CTL 218 PCIREQ3/MD10 IN 217 PCIREQ2/MD9 OUT 216 PCIREQ2/MD9 CTL 215 PCIREQ2/MD9 IN 214 IDSEL IN 213 INTA OUT 212 INTA CTL 211 PCIRST OUT 210 PCIRST CTL 209 PCICLK IN 208 PCIGNT1/REQOUT OUT 207 PCIGNT1/REQOUT CTL 206 PCIREQ1/GNTIN OUT 205 PCIREQ1/GNTIN CTL 204 PCIREQ1/GNTIN IN 203 SERR OUT 202 SERR CTL 201 SERR IN 200 AD31 OUT 199 AD31 CTL 198 AD31 IN 197 AD30 OUT 196 AD30 CTL 195 AD30 IN 194 AD29 OUT 193 AD29 CTL 192 AD29 IN 191 AD28 OUT Page 836 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) No. Pin name Type 190 AD28 CTL 189 AD28 IN 188 AD27 OUT 187 AD27 CTL 186 AD27 IN 185 AD26 OUT 184 AD26 CTL 183 AD26 IN 182 AD25 OUT 181 AD25 CTL 180 AD25 IN 179 AD24 OUT 178 AD24 CTL 177 AD24 IN 176 C/BE3 OUT 175 C/BE3 CTL 174 C/BE3 IN 173 AD23 OUT 172 AD23 CTL 171 AD23 IN 170 AD22 OUT 169 AD22 CTL 168 AD22 IN 167 AD21 OUT 166 AD21 CTL 165 AD21 IN 164 AD20 OUT 163 AD20 CTL 162 AD20 IN 161 AD19 OUT 160 AD19 CTL 159 AD19 IN 158 AD18 OUT R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 837 of 1128 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group No. Pin name Type 157 AD18 CTL 156 AD18 IN 155 AD17 OUT 154 AD17 CTL 153 AD17 IN 152 AD16 OUT 151 AD16 CTL 150 AD16 IN 149 C/BE2 OUT 148 C/BE2 CTL 147 C/BE2 IN 146 PCIFRAME OUT 145 PCIFRAME CTL 144 PCIFRAME IN 143 IRDY OUT 142 IRDY CTL 141 IRDY IN 140 TRDY OUT 139 TRDY CTL 138 TRDY IN 137 DEVSEL OUT 136 DEVSEL CTL 135 DEVSEL IN 134 PCISTOP OUT 133 PCISTOP CTL 132 PCISTOP IN 131 PCILOCK OUT 130 PCILOCK CTL 129 PCILOCK IN 128 PERR OUT 127 PERR CTL 126 PERR IN 125 PAR OUT Page 838 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) No. Pin name Type 124 PAR CTL 123 PAR IN 122 C/BE1 OUT 121 C/BE1 CTL 120 C/BE1 IN 119 AD15 OUT 118 AD15 CTL 117 AD15 IN 116 AD14 OUT 115 AD14 CTL 114 AD14 IN 113 AD13 OUT 112 AD13 CTL 111 AD13 IN 110 AD12 OUT 109 AD12 CTL 108 AD12 IN 107 AD11 OUT 106 AD11 CTL 105 AD11 IN 104 AD10 OUT 103 AD10 CTL 102 AD10 IN 101 AD9 OUT 100 AD9 CTL 99 AD9 IN 98 AD8 OUT 97 AD8 CTL 96 AD8 IN 95 C/BE0 OUT 94 C/BE0 CTL 93 C/BE0 IN 92 AD7 OUT R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 839 of 1128 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group No. Pin name Type 91 AD7 CTL 90 AD7 IN 89 AD6 OUT 88 AD6 CTL 87 AD6 IN 86 AD5 OUT 85 AD5 CTL 84 AD5 IN 83 AD4 OUT 82 AD4 CTL 81 AD4 IN 80 AD3 OUT 79 AD3 CTL 78 AD3 IN 77 AD2 OUT 76 AD2 CTL 75 AD2 IN 74 AD1 OUT 73 AD1 CTL 72 AD1 IN 71 AD0 OUT 70 AD0 CTL 69 AD0 IN 68 IRL0 IN 67 IRL1 IN 66 IRL2 IN 65 IRL3 IN 64 NMI IN 63 BACK/BSREQ OUT 62 BACK/BSREQ CTL 61 BREQ/BSACK IN 60 MD6/IOIS16 IN 59 RDY IN Page 840 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) No. Pin name Type 58 TXD OUT 57 TXD CTL 56 TXD IN 55 MD2/RXD2 IN 54 RXD IN 53 TCLK OUT 52 TCLK CTL 51 TCLK IN 50 RTS2/MD8 OUT 49 RTS2/MD8 CTL 48 RTS2/MD8 IN 47 SCK OUT 46 SCK CTL 45 SCK IN 44 MD1/TXD2 OUT 43 MD1/TXD2 CTL 42 MD1/TXD2 IN 41 MD0/SCK2 OUT 40 MD0/SCK2 CTL 39 MD0/SCK2 IN 38 MD7/CTS2 OUT 37 MD7/CTS2 CTL 36 MD7/CTS2 IN 35 AUDSYNC OUT 34 AUDSYNC CTL 33 AUDCK OUT 32 AUDCK CTL 31 AUDATA0 OUT 30 AUDATA0 CTL 29 AUDATA1 OUT 28 AUDATA1 CTL 27 AUDATA2 OUT 26 AUDATA2 CTL R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 841 of 1128 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group No. Pin name Type 25 AUDATA3 OUT 24 AUDATA3 CTL 23 MD3/CE2A OUT 22 MD3/CE2A CTL 21 MD3/CE2A IN 20 MD4/CE2B OUT 19 MD4/CE2B CTL 18 MD4/CE2B IN 17 MD5 OUT 16 MD5 CTL 15 MD5 IN 14 DACK0 OUT 13 DACK0 CTL 12 DACK1 OUT 11 DACK1 CTL 10 DRAK0 OUT 9 DRAK0 CTL 8 DRAK1 OUT 7 DRAK1 CTL 6 STATUS0 OUT 5 STATUS0 CTL 4 STATUS1 OUT 3 STATUS1 CTL 2 DREQ0 IN 1 DREQ1 IN from TDI Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Page 842 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 21.3 Operation 21.3.1 TAP Control Section 21 High-performance User Debug Interface (H-UDI) Figure 21.2 shows the internal states of the TAP control circuit. These conform to the state transitions specified by JTAG. • The transition condition is the TMS value at the rising edge of TCK. • The TDI value is sampled at the rising edge of TCK, and shifted at the falling edge. • The TDO value changes at the falling edge of TCK. When not in the Shift-DR or Shift-IR state, TDO is in the high-impedance state. • In a transition to TRST = 0, a transition is made to the Test-Logic-Reset state asynchronously with respect to TCK. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR-Scan 1 Select-IR-Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 1 Exit1-IR 0 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 Figure 21.2 TAP Control State Transition Diagram R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 843 of 1128 Section 21 High-performance User Debug Interface (H-UDI) 21.3.2 SH7751 Group, SH7751R Group H-UDI Reset A power-on reset is effected by an SDIR command. A reset is effected by sending a H-UDI reset assert command, and then sending a H-UDI reset negate command, from the H-UDI pin (see figure 21.3). The interval required between the H-UDI reset assert command and the H-UDI reset negate command is the same as the length of time the reset pin is held low in order to effect a power-on reset. H-UDI reset assert H-UDI pin H-UDI reset negate Chip internal reset CPU state Normal Reset Reset processing Figure 21.3 H-UDI Reset 21.3.3 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command value in SDIR from the H-UDI. The H-UDI interrupt is of general exception/interrupt operation type, with a branch to an address based on VBR and return effected by means of an RTE instruction. The exception code stored in control register INTEVT in this case is H'600. The priority of the H-UDI interrupt can be controlled with bits 3 to 0 of control register IPRC. The H-UDI interrupt request signal is asserted when, after the command is set (Update-IR), the INTREQ bit of the SDINT register is set to 1. The interrupt request signal is not negated until 0 is written to the INTREQ bit by software, and there is therefore no risk of the interrupt request being unexpectedly missed. While the H-UDI interrupt command is set in SDIR, the SDINT register is connected between TDI and TDO. Page 844 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 21.3.4 Section 21 High-performance User Debug Interface (H-UDI) Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) In this LSI, setting a command from the H-UDI in SDIR can place the H-UDI pins in the boundary scan mode. However, the following limitations apply. 1. Clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, and CKIO) are excluded from the boundary scan. 2. Reset-related signals (RESET, MRESET, and CA) are excluded from the boundary scan. 3. H-UDI signals (TCK, TDI, TDO, TMS, and TRST) are excluded from the boundary scan. 4. With EXTEST, assert the MRESET pin (Low), negate the RESET pin (High), and assert the CA pin (High). With SAMPLE/PRELOAD, assert the CA pin (High). 5. When executing a boundary scan (EXTEST, SAMPLE/PRELOAD, and BYPASS), supply a clock signal to the EXTAL pin. The allowed range of input clock frequencies is from 1 to 33.3 MHz. Execute the boundary scan after tOSC1 (the power-on oscillation-stabilization time) has elapsed. The clock signal need not be supplied to the EXTAL pin after tOSC1 has elapsed. For details on tOSC1 (the power-on oscillation-stabilization time), see section 23, Electrical Characteristics. 21.4 Usage Notes 1. SDIR Command Once an SDIR command is set, it does not change until another command is written from the H-UDI, unless initialized by asserting TRST or the TAP is set in the Test-Logic-Reset state. 2. SDIR Commands in Sleep Mode Sleep mode is cleared by an H-UDI interrupt or H-UDI reset, and these exception requests are accepted in this mode. In standby mode, neither an H-UDI interrupt nor an H-UDI reset is accepted. 3. In standby mode, the H-UDI function cannot be used. Furthermore, TCK must be retained at a high level when entering the standby mode in order to retain the TAP state before and after standby mode. 4. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when an emulator is used. 5. When the SH7751 is in bypass mode, the bypass register (SDBPR) is not fixed in the CaptureDR state. (It is cleared to 0 in the SH7751R.) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 845 of 1128 Section 21 High-performance User Debug Interface (H-UDI) Page 846 of 1128 SH7751 Group, SH7751R Group R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Section 22 PCI Controller (PCIC) 22.1 Overview The PCI Controller (PCIC) controls the PCI bus and transfers data between memory connected to the external bus and a PCI device connected to the PCI bus. The ability for PCI devices to be connected directly not only facilitates the design of systems using PCI buses but also enables systems to be more compact and capable of high-speed data transfer. 22.1.1 Features The PCIC has the following features: • • • • • • • • • • • • • Supports a subset of PCI version 2.1. Compatible with PCI bus operating speeds of 33 MHz/66 MHz. Compatible with 32-bit PCI bus. Up to four PCI master devices running at 33 MHz or one PCI master device at 66 MHz can be connected. Arbitration control is available as a PCI host function. Can operate as master or target. When operating as master, PIO and DMA transfer are available. Four DMA transfer channels. Six 32-bit x 16 longword internal FIFO (one for target reading, one for target writing, and four for DMA transfer). Asynchronous operation of BSC bus clock and PCI bus clock available, and CKIO can be used as PCI bus clock. SRAM, DRAM, SDRAM, and MPX* can be used as external memory for PCI bus data transfers. 32-bit or 16-bit memory data bus for data transfers with PCI bus (32-bit bus when connected to SDRAM). Support for big endian and little endian local bus (PCI bus operates with little endian, while internal bus for peripheral modules operates with big endian). Note: * MPX is only supported by the SH7751R and is not supported by the SH7751. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 847 of 1128 Section 22 PCI Controller (PCIC) 22.1.2 SH7751 Group, SH7751R Group Block Diagram Figure 22.1 is a block diagram of the PCIC. PCI bus PCIC module Interrupts Interrupt control PCI bus interface Local register Internal peripheral module bus (Peripheral bus) Internal peripheral module bus interface Data transfer control PCI configuration register FIFO 32B × 2 sides × 6 Local register Local register Bus request Acknowledge PCIC bus controller Local register Local bus Local bus clock (Bck) cycle: Bcyc Feedback input clock from CKIO PCI clock 33/66 MHz (PCICLK) Figure 22.1 PCIC Block Diagram Page 848 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.1.3 Section 22 PCI Controller (PCIC) Pin Configuration Table 22.1 shows the configuration of I/O pins of the PCIC. Table 22.1 Pin Configuration No. Pin Name PCI Standard Signal Name Function I/O Status in Operating Modes Host Non-host I/O Pull-up 1 Type Resistor* Master Target Master Target Remarks 1 PCICLK CLK PCI input clock (33 MHz/66 MHz) in I I I I 2 PCIRST — Reset output out O O — — 3 AD31 to AD0 AD[31:0] Address/data t/s I/O I/O I/O I/O Low level output at reset 4 C/BE3 to C/BE0 C/BE[3:0] Command/byte enable t/s O I O I Low level output at reset 5 PAR PAR t/s I/O I/O I/O I/O Low level output at reset 6 PCIFRAME FRAME Bus cycle s/t/s Yes O I O I 7 IRDY IRDY Initiator ready s/t/s Yes O I O I 8 TRDY TRDY 9 PCISTOP STOP Target ready s/t/s Yes I O I O Transaction stop s/t/s Yes I O I O 10 PCILOCK LOCK Exclusive access control s/t/s Yes O I O I 11 DEVSEL DEVSEL Device select s/t/s Yes I O I O 12 PCIREQ1/ GNTIN REQ1 Bus request (host function) t/s Yes I I — — GNT Bus grant t/s Yes — — I 13 PCIGNT1/ REQOUT GNT1 Bus grant (host function) t/s No O O — REQ Bus request t/s No — — O 14 PERR PERR Parity error s/t/s Yes I/O O I/O 15 SERR SERR System error o/d Yes O O O O 16 INTA INTA Interrupt (async) o/d Yes — — O O Parity R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 — O Page 849 of 1128 Section 22 PCI Controller (PCIC) No. Pin Name 17 PCIREQ2/ MD9 18 PCIREQ3/ MD10 PCI Standard Signal Name Function REQ2 REQ3 SH7751 Group, SH7751R Group I/O Status in Operating Modes Host Non-host I/O Pull-up 1 Type Resistor* Master Target Master Target Remarks Bus request (host function) t/s PCI clock switch (BCLK/PCICLK) in Bus request (host function) t/s Host bridge function ON/OFF in Yes Yes I I — — I I I I I I — — I I I I I I — — 2 * 2 * 19 PCIREQ4 REQ4 Bus request (host function) t/s 20 PCIGNT4 to PCIGNT2 GNT4 to GNT2 Bus grant (host function) t/s O O — — 21 IDSEL IDSEL Config device select in — — I I Yes 3 * Legend: in: Input out: Output s/t/s: Sustained try state o/d: Open drain t/s: Try state Notes: 1. Terminal provided with a pull-up resistor. 2. The values of external pins are sampled in a power-on reset by means of the RESET pin. 3. Pull down this pin to low level when IDSEL is not in use. If a configuration access to an external PCI device occurs while IDSEL is high level, the PCIC itself may respond. 22.1.4 Register Configuration The PCIC has the PCI configuration registers and PCI control registers shown in table 22.2, 22.3 and 22.4. Also, the PCI bus address space is allocated to the internal bus for the peripheral modules, making it possible to access the PCI bus by program IO (PIO). Not only do these registers control the PCI bus but also enable high-speed data transfers between the PCI device and memory on the SH-4 external data bus (hereinafter, the SH-4 external data bus is referred to as the local bus to distinguish it from the PCI bus). Page 850 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Table 22.2 List of PCI Configuration Registers PCI Configuration P4 Address Address Area 7 Address Access Size Name Abbreviation PCI R/W PP-Bus R/W Initial Value PCI configuration register 0 PCICONF0 R R *1 H'00 H'FE200000 H'1E200000 32 PCI configuration register 1 PCICONF1 R/W R/W H'02900080 H'04 H'FE200004 H'1E200004 32 PCI configuration register 2 PCICONF2 R R/W[31:8] R (other) H'xxxxxx*2 H'08 H'FE200008 H'1E200008 32 PCI configuration register 3 PCICONF3 R/W[15:8] R (other) R/W[15:8] R (other) H'00000000 H'0C H'FE20000C H'1E20000C 32 PCI configuration register 4 PCICONF4 R/W R/W H'00000001 H'10 H'FE200010 H'1E200010 32 PCI configuration register 5 PCICONF5 R/W R/W H'00000000 H'14 H'FE200014 H'1E200014 32 PCI configuration register 6 PCICONF6 R/W R/W H'00000000 H'18 H'FE200018 H'1E200018 32 PCI configuration register 7 PCICONF7 R R H'00000000 H'1C H'FE20001C H'1E20001C 32 PCI configuration register 8 PCICONF8 R R H'00000000 H'20 H'FE200020 H'1E200020 32 PCI configuration register 9 PCICONF9 R R H'00000000 H'24 H'FE200024 H'1E200024 32 PCI configuration register 10 PCICONF10 R R H'00000000 H'28 H'FE200028 H'1E200028 32 PCI configuration register 11 PCICONF11 R R/W H'xxxxxxxx H'2C H'FE20002C H'1E20002C 32 PCI configuration register 12 PCICONF12 R R H'00000000 H'30 H'FE200030 H'1E200030 32 PCI configuration register 13 PCICONF13 R R H'00000040 H'34 H'FE200034 H'1E200034 32 PCI configuration register 14 PCICONF14 R R H'00000000 H'38 H'FE200038 H'1E200038 32 PCI configuration register 15 PCICONF15 R/W[7:0] R (other) R/W[7:0] R (other) H'00000100 H'3C H'FE20003C H'1E20003C 32 PCI configuration register 16 PCICONF16 R R R/W[18:16] R (other) H'00010001 H'40 H'FE200040 H'1E200040 32 PCI configuration register 17 PCICONF17 R/W[1:0] R (other) R/W[1:0] R (other) H'00000000 H'44 H'FE200044 H'1E200044 32 Reserved — R R H'00000000 H'48 to H'FC H'FE200048 H'1E200048 32 to to H'FE2000FC H'1E2000FC Legend: x: Undefined value Notes: 1. Varies with the logic versions of the chip. 2. H'35051054 for the SH7751; H'350E1054 for the SH7751R. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 851 of 1128 Section 22 PCI Controller (PCIC) Table 22.3 SH7751 Group, SH7751R Group PCI Configuration Register Configuration PCI Configu P4 ration Address Address Area 7 Address H'00 H'1E200000 Device ID H'FE200000 PCI Configuration Register 31 to 24 23 to 16 15 to 8 7 to 0 PCI R/W PP-Bus R/W Device ID Vendor ID Vendor ID R R H'04 H'FE200004 H'1E200004 Status Status Command Command R/W R/W H'08 H'FE200008 H'1E200008 Class code Class code Class code Revision ID R R/W[31:8] R (other) H'0C H'FE20000C H'1E20000C BIST Header type PCI latency timer Cache line size R/W[15:8] R/W[15:8] R (other) R (other) H'10 H'FE200010 H'1E200010 Base address Base address Base address Base address R/W (I/O area) (I/O area) (I/O area) (I/O area) R/W H'14 H'FE200014 H'1E200014 Base address Base address Base address Base address R/W (local address (local address (local address (local address area 0) area 0) area 0) area 0) R/W H'18 H'FE200018 H'1E200018 Base address Base address Base address Base address R/W (local address (local address (local address (local address area 1) area 1) area 1) area 1) R/W H'1C H'FE20001C H'1E20001C Reserved Reserved Reserved Reserved R R H'20 H'FE200020 H'1E200020 Reserved Reserved Reserved Reserved R R H'24 H'FE200024 H'1E200024 Reserved Reserved Reserved Reserved R R H'28 H'FE200028 H'1E200028 Reserved Reserved Reserved Reserved R R H'2C H'FE20002C H'1E20002C Subsystem ID Subsystem ID Subsystem vendor ID Subsystem vendor ID R R/W H'30 H'FE200030 H'1E200030 Reserved Reserved Reserved Reserved R R H'34 H'FE200034 H'1E200034 Reserved Reserved Reserved Extended function pointer R R H'38 H'FE200038 H'1E200038 Reserved Reserved Reserved Reserved R R H'3C H'FE20003C H'1E20003C Max_Lat Min_Gnt Interrupt pin Interrupt line R/W[7:0] R (other) R/W[7:0] R (other) H'40 H'FE200040 H'1E200040 Power management related Power management related Power management related Power management related R R/W[18:16] R (other) H'44 H'FE200044 H'1E200044 Power management related Power management related Power management related Power management related R/W[1:0] R (other) R/W[1:0] R (other) H'48 to H'0FC H'FE200048 H'1E200048 Reserved to to H'FE2000FC H'1E2000FC Reserved Reserved Reserved R R Page 852 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Table 22.4 List of PCIC Local Registers PCI I/O Address (SH7751/ P4 SH7751R) Address Name Abbreviation PCI R/W PP-Bus Initial Value R/W Area 7 Address Access Size PCI control register PCICR R R/W H'000000*0 H'100/ H'00 H'FE200100 H'1E200100 32 Local space register 0 for PCI PCILSRO R R/W H'00000000 H'104/ H'04 H'FE200104 H'1E200104 32 Local space register 1 for PCI PCILSR1 R R/W H'00000000 H'108/ H'08 H'FE200108 H'1E200108 32 Local address register 0 for PCI PCILAR0 R/W R/W H'00000000 H'10C/ H'0C H'FE20010C H'1E20010C 32 Local address register 1 for PCI PCILAR1 R/W R/W H'00000000 H'110/ H'10 H'FE200110 H'1E210110 32 PCI interrupt register PCIINT R/W R/W H'00000000 H'114/ H'14 H'FE200114 H'1E200114 32 PCI interrupt mask register PCIINTM R/W R/W H'00000000 H'118/ H'18 H'FE200118 H'1E200118 32 Error address data register for PCI PCIALR R R H'xxxxxxxx H'11C/ H'1C H'FE20011C H'1E20011C 32 Error command data register for PCI PCICLR R R H'0000000x H'120/ H'20 H'FE200120 H'1E200120 32 Reserved — — — H'00000000 H'124 to H'12C/ H'24 to H'2C H'FE200124 to H'FE20012C H'1E200124 to H'1E20012C 32 PCI arbiter interrupt register PCIAINT R/W R/W H'00000000 H'130/ H'30 H'FE200130 H'1E200130 32 PCI arbiter interrupt mask register PCIAINTM R/W R/W H'00000000 H'134/ H'34 H'FE200134 H'1E200134 32 Error bus master data register for PCI PCIBMLR R R H'00000000 H'138/ H'38 H'FE200138 H'1E200138 32 Reserved — — — H'00000000 H'13C/ H'3C H'FE20013C H'1E20013C 32 DMA transfer arbitration register for PCI PCIDMABT R/W R/W H'00000000 H'140/ H'40 H'FE200140 H'1E200140 32 Reserved — — — H'00000000 H'144 to H'17C/ H'44 to H'7C H'FE200144 to H'FE20017C H'1E200144 to H'1E20017C 32 DMA transfer PCI address register 0 for PCI PCIDPA0 R/W R/W H'00000000 H'180/ H'80 H'FE200180 H'1E200180 32 DMA transfer local bus PCIDLA0 starting address regsiter 0 for PCI R/W R/W H'00000000 H'184/ H'84 H'FE200184 H'1E200184 32 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 853 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group PCI I/O Address (SH7751/ P4 SH7751R) Address Abbreviation PCI R/W PP-Bus Initial Value R/W Area 7 Address Access Size DMA transfer count register 0 for PCI PCIDTC0 R/W R/W H'00000000 H'188/ H'88 H'FE200188 H'1E200188 32 DMA control register 0 for PCI PCIDCR0 R/W R/W H'00000000 H'18C/ H'8C H'FE20018C H'1E20018C 32 DMAPCI address register 1 for PCI PCIDPA1 R/W R/W H'00000000 H'190/ H'90 H'FE200190 H'1E200190 32 DMA transfer local bus PCIDLA1 starting address register 1 for PCI R/W R/W H'00000000 H'194/ H'94 H'FE200194 H'1E200194 32 DMA transfer count register 1 for PCI PCIDTC1 R/W R/W H'00000000 H'198/ H'98 H'FE200198 H'1E200198 32 DMA control register 1 for PCI PCIDCR1 R/W R/W H'00000000 H'19C/ H'9C H'FE20019C H'1E20019C 32 DMA transfer PCI address register 2 for PCI PCIDPA2 R/W R/W H'00000000 H'1A0/ H'A0 H'FE2001A0 H'1E2001A0 32 DMA transfer local bus PCIDLA2 starting address register 2 for PCI R/W R/W H'00000000 H'1A4/ H'A4 H'FE2001A4 H'1E2001A4 32 DMA transfer count register 2 for PCI PCIDTC2 R/W R/W H'00000000 H'1A8/ H'A8 H'FE2001A8 H'1E2001A8 32 DMA control register 2 for PCI PCIDCR2 R/W R/W H'00000000 H'1AC/ H'AC H'FE2001AC H'1E2001AC 32 DMA transfer PCI address register 3 for PCI PCIDPA3 R/W R/W H'00000000 H'1B0/ H'B0 H'FE2001B0 H'1E2001B0 32 DMA transfer local bus PCIDLA3 starting address register 3 for PCI R/W R/W H'00000000 H'1B4/ H'B4 H'FE2001B4 H'1E2001B4 32 DMA transfer count register 3 for PCI PCIDTC3 R/W R/W H'00000000 H'1B8/ H'B8 H'FE2001B8 H'1E2001B8 32 DMA control register 3 for PCI PCIDCR3 R/W R/W H'00000000 H'1BC/ H'BC H'FE2001BC H'1E2001BC 32 PIO address register PCIPAR — R/W H'80xxxxxx — H'FE2001C0 H'1E2001C0 32 Memory space base register PCIMBR — R/W H'xx000000 — H'FE2001C4 H'1E2001C4 32 IO space base register PCIIOBR — R/W H'xxxx0000 — H'FE2001C8 H'1E2001C8 32 PCI power management PCIPINT interrupt register — R/W H'00000000 — H'FE2001CC H'1E2001CC 32 PCI power management PCIPINTM interrupt mask register — R/W H'00000000 — H'FE2001D0 H'1E2001D0 32 PCI clock control register — R/W H'00000000 — H'FE2001D4 H'1E2001D4 32 Name Page 854 of 1128 PCICLKR R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Name Abbreviation PCI R/W Reserved — PCI bus control register 1 PCIBCR1 — PCI bus control register 2 PCIBCR2 PCI wait control register 1 PP-Bus Initial Value R/W PCI I/O Address (SH7751/ P4 SH7751R) Address Area 7 Address Access Size H'00000000 — H'FE2001D8 to H'FE2001DC H'1E2001D8 to H'1E2001DC 32 R/W H'*0000000 — H'FE2001E0 H'1E2001E0 32 — R/W H'0000*FFC — H'FE2001E4 H'1E2001E4 32 PCIWCR1 — R/W H'77777777 — H'FE2001E8 H'1E2001E8 32 PCI wait control register 2 PCIWCR2 — R/W H'FFFEEFFF — H'FE2001EC H'1E2001EC 32 PCI wait control register 3 PCIWCR3 — R/W H'07777777 — H'FE2001F0 H'1E2001F0 32 PCIC discrete memory control register PCIMCR — R/W H'00000000 — H'FE2001F4 H'1E2001F4 32 PCIC bus control register 3*1 PCIBCR3 — R/W H'00000001 — H'FE2001F8 H'1E2001F8 32 Reserved — H'FE2001FC H'1E2001FC 32 Port control register PCIPCTR — R/W H'00000000 — H'FE200200 H'1E200200 32 Port data register PCIPDTR — R/W H'00000000 — H'FE200204 H'1E200204 32 Reserved — H'00000000 — H'FE200208 to H'FE20021C H'1E200208 to H'1E20021C 32 PIO data register PCIPDR H'xxxxxxxx — H'FE200220 H'1E200220 32 H'00000000 — R/W Notes: * The values of some external pins are sampled in a power-on reset by means of the RESET pin. x indicates “undefined.” 1. PCIC bus control register 3 is provided only in the SH7751R. The relevant areas of the SH7751 are reserved areas. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 855 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2 PCIC Register Descriptions 22.2.1 PCI Configuration Register 0 (PCICONF0) Bit: 31 30 29 28 27 26 25 24 DEVID15 DEVID14 DEVID13 DEVID12 DEVID11 DEVID10 DEVID9 DEVID8 Initial value: 0 0 1 1 0 1 0 1 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 DEVID7 DEVID6 DEVID5 DEVID4 DEVID3 DEVID2 DEVID1 DEVID0 Initial value: 0 0 0 0 0/1* 1 0/1* 1/0* PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 VNDID15 VNDID14 VNDID13 VNDID12 VNDID11 VNDID10 VNDID9 VNDID8 Initial value: 0 0 0 1 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 VNDID7 VNDID6 VNDID5 VNDID4 VNDID3 VNDID2 VNDID1 VNDID0 Initial value: 0 1 0 1 0 1 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Note: * These values differ between SH7751 and SH7751R. PCI configuration register 0 (PCICONF0) is a 32-bit read-only register that includes the device ID and vendor ID PCI configuration registers stipulated in the PCI local bus specifications. The SH7751 ID (H'3505) or the SH7751R ID (H'350E) is read from bits 31 to 16; the vendor ID (H'1054*) is read from bits 15 to 0. All bits of the PCICONF0 are fixed in hardware. Page 856 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 31 to 16—DEVID15 to 0: These bits specify the device ID of the SH7751 or SH7751R allocated by the PCI device vendor. H'3505 (fixed in hardware) for the SH7751, and H'350E (fixed in hardware) for the SH7751R. Bits 15 to 0—DNVID15 to 0: These bits specify the PCI device maker (vendor ID). (H'1054*: fixed in hardware) Note: * The vendor ID H'1054 specifies Hitachi, Ltd., but the SH7751 and SH7751R are now products of Renesas Electronics Corp. For information on these products, contact Renesas Electronics Corp. 22.2.2 PCI Configuration Register 1 (PCICONF1) Bit: Initial value: 31 30 29 28 27 26 25 24 DPE SSE RMA RTA STA DEV1 DEV0 DPD 0 0 0 0 0 0 1 0 PCI-R/W: R/WC R/WC R/WC R/WC R/WC R R R/WC PP Bus-R/W: R/WC R/WC R/WC R/WC R/WC R R R/WC 23 22 21 20 19 18 17 16 Bit: FBBC UDF 66M PM — — — — Initial value: 1 0 0 1 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R/W R/W R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — PBBE SER Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R/W PP Bus-R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 WCC PER VPS MWIE SPC BUM MES IOS Initial value: 1 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R R R R/W R/W R/W PP Bus-R/W: R/W R/W R R R R/W R/W R/W Note: Cleared by writing WC: 1. (Writing of 0 is ignored.) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 857 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group PCI configuration register 1 (PCICONF1) is a 32-bit read/partial-write register that includes the status and command PCI configuration registers stipulated in the PCI local bus specifications. The status is read from bits 31 to 16 (status register) in the event of an error on the PCI bus. Bits 15 to 0 (command register) contain the settings required for initiating transfers on the PCI bus. Bits 31 to 27, 24, 8 to 6, and 2 to 0 can be written to from both the PP and PCI buses. However, bits 31 to 27 and 24 are write-clear bits that are cleared when 1 is written to them. Bits 22 and 21 can be written to from the PP bus. Other bits are fixed in hardware. The PCICONF1 register is initialized to H'02900080 at a power-on reset or software reset. Always write to this register before initiating transfers on the PCI bus. Bit 31—Parity Error Detection Status (DPE): Indicates the detection of a parity error in read data when the PCIC is operating as the master, or a party error in write data when the PCIC is operating as a target. Bit 31: DPE Description 0 No parity error detected by device 1 (Initial value) Parity error detected by device Set this bit regardless of the parity error response bit (bit 6) on the device Bit 30—System Error Output Status (SSE): Indicates the SERR assert operation of the PCIC. Bit 30: SSE Description 0 Device not asserting SERR 1 Device asserting SERR (Value retained until cleared) (Initial value) Bit 29—Master abort receive status (RMA): Indicates the termination of transaction by master abort when the PCIC is operating as the master. Bit 29: RMA Description 0 No transaction termination using bus master abort 1 Detection by bus master of transaction termination by bus master abort (Initial value) However, in the case of a master abort in a special cycle, notify the master devices that are not set Page 858 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 28—Target Abort Receive Status (RTA): Indicates the termination of transaction by master abort when the PCIC is operating as the master. Bit 28: RTA Description 0 No transaction termination using target abort 1 Detection by bus master of transaction termination by target abort (Initial value) Bit 27—Target Abort Execution Status (STA): Indicates the termination of transaction by target abort when the PCIC is operating as the target. Bit 27: STA Description 0 No transaction termination using target abort by target device (Initial value) 1 Transaction termination by target abort by target device. Notification by target device Bits 26 and 25—DEVSEL Timing Status (DEV1 and 0): These bits indicate the DEVSEL response timing when the PCIC is operating as a target. Bit 26: DEV1 Bit 25: DEV0 Description 0 0 High-speed (not supported) 1 Medium speed 0 Low speed (not supported) 1 Reserved 1 (Initial value) Bit 24—Data Parity Status (DPD): Indicates the PERR assert operation or the detection of PERR when the PCIC is operating as the master. This bit is set only when the parity error response bit (bit 6) is 1. Bit 24: DPD Description 0 Data parity not detected 1 Data parity occurred R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 (Initial value) Page 859 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 23—High-Speed Back-To-Back Status (FBBC): Shows whether a high-speed back-to-back transfer to a different target can be accepted when the PCIC is operating as a target. Bit 23: FBBC Description 0 The target does not have a high-speed back-to-back transaction function for use with other targets 1 The target has a high-speed back-to-back transaction function for use with other targets (Initial value) Bit 22—User Defined Function System (UDF): Shows whether user defined functions are supported. Bit 22: UDF Description 0 This device does not support user functions 1 This device supports user functions (Initial value) Bit 21—66 MHz Operating Status (66M): Shows whether 66 MHz operation is supported. Bit 21: 66M Description 0 This device supports 33 MHz operation 1 This device supports 66 MHz operation (Initial value) Bit 20—PCI Power Management (PM): Shows whether the PCI power management is supported. Bit 20: PM Description 0 Power management not supported 1 Power management supported (Initial value) Bits 19 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 9—High-Speed Back-To-Back Control (PBBE): Selects whether or not to allow high-speed back-to-back control with different targets when privileged as the master. Bit 9: PBBE Description 0 Allows high-speed back-to-back control only with same target (Initial value) 1 Allows high-speed back-to-back control with different target (Not supported) Page 860 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 8—SERR Output Control (SER): Controls the SERR output. Bit 8: SER Description 0 SERR output disabled (Hi-Z) 1 SERR output enabled (Initial value) Bit 7—Wait Cycle Control (WCC): Controls the address/data stepping. When WCC=1, address and data are output in master write operations, only address is output in master read operations, and only data is output in target read operations, at least in two clocks. Bit 7: WCC Description 0 Disable address/data stepping control 1 Enable address/data stepping control (Initial value) Bit 6—Parity Error Response (PER): Controls the device response when a parity error is detected or a parity error report is received. PERR is asserted only when PER = 1. Bit 6: PER Description 0 Ignore detected parity errors 1 Respond to detected parity error (Initial value) Bit 5—VGA Pallet Snoop Control (VPS) Bit 5: VPS Description 0 VGA-compatible device 1 The device does not respond to pallet register writes (not supported) (Initial value) Bit 4—Memory Write and Invalidate Control (MWIE): Controls the issuance of memory and invalidate command when the PCIC is operating as the master. Bit 4: MWIE Description 0 The device uses memory write 1 The device can execute memory write and invalidate commands (not supported) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 (Initial value) Page 861 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 3—Special Cycle Control (SPC): Shows whether special cycles are supported when the PCIC is operating as a target. Bit 3: SPC Description 0 Ignore special cycle 1 Monitor special cycle (not supported) (Initial value) Bit 2—PCI Bus Master Control (BUM): Controls the bus master operation. Bit 2: BUM Description 0 Disable bus master operation 1 Enable bus master operation (Initial value) Bit 1—Memory Space Control (MES): Controls the access to the memory space when the PCIC is operating as a target. When this bit is 0, all memory transfers to the PCIC are terminated by master abort. Bit 1: MES Description 0 Disable access to memory space 1 Enable access to memory space (Initial value) Bit 0—I/O Space Control (IOS): Controls the access to the I/O space when the PCIC is operating as a target. When this bit is 0, all I/O transfers to the PCIC are terminated by master abort. Bit 0: IOS Description 0 Disable access to I/O space 1 Enable access to I/O space Page 862 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.2.3 Section 22 PCI Controller (PCIC) PCI Configuration Register 2 (PCICONF2) Bit: 31 30 29 28 27 26 25 24 CLASS23 CLASS22 CLASS21 CLASS20 CLASS19 CLASS18 CLASS17 CLASS16 Initial value: — — — — — — — 0 PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 PP Bus-R/W: Bit: CLASS15 CLASS14 CLASS13 CLASS12 CLASS11 CLASS10 CLASS9 CLASS8 Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — — — — — — R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 CLASS7 CLASS6 CLASS5 CLASS4 CLASS3 CLASS2 CLASS1 CLASS0 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 REVID7 REVID6 REVID5 REVID4 REVID3 REVID2 REVID1 REVID0 Initial value: * * * * * * * * PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R PP Bus-R/W: Bit: Note: * Initial values vary with the logic versions of the chip. The PCI configuration register 2 (PCICONF2) is a 32-bit read/partial-write register that includes the class code and revision ID PCI configuration registers stipulated in the PCI local bus specifications. Bits 31 to 8 (class code) set the device functions. The chip logic version can be read from bits 7 to 0 (revision ID). Bits 31 to 8 can be written to from the PP bus. Bits 7 to 0 are fixed in hardware. The PCICONF2 register class codes are not initialized at a reset. They must be initialized while CFINIT (bit 0) of the PCI control registers (PCICR) is cleared. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 863 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 24—Base Class Code (CLASS23 to 16): These bits indicate the base class code. For details of setting values, refer to table 22.5. Table 22.5 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16) CLASS23 to 16 Base Class Meaning H'00 Device designed prior to class code being defined H'01 High-capacity storage controller H'02 Network controller H'03 Display controller H'04 Multimedia device H'05 Memory controller H'06 Bridge device H'07 Simple communication device H'08 Basic peripheral device H'09 Input device H'0A Docking station H'0B Processor H'0C Serial bus controller H'0D to H'FE Reserved H'FF Device not categorized in defined class Bits 23 to 16—Sub Class Codes (CLASS15 to 8): Shows the subclass code. For details, please see appendix D, Pin Functions of the PCI Local Bus Specifications, Revision 2.1. Bits 15 to 8—Register Level Programming Interface (CLASS7 to 0): Shows the register level programming interface. For details, please see appendix D, Pin Functions of the PCI Local Bus Specifications, Revision 2.1. Bits 7 to 0—Revision ID (REVID7 to 0): Shows the PCIC revision. The initial value differs according to the logic version of the chip. Page 864 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.2.4 Section 22 PCI Controller (PCIC) PCI Configuration Register 3 (PCICONF3) Bit: 31 30 29 28 27 26 25 24 BIST7 BIST6 BIST5 BIST4 BIST3 BIST2 BIST1 BIST0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 HEAD7 HEAD6 HEAD5 HEAD4 HEAD3 HEAD2 HEAD1 HEAD0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 LAT7 LAT6 LAT5 LAT4 LAT3 LAT2 LAT1 LAT0 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Initial value: Bit: CACHE7 CACHE6 CACHE5 CACHE4 CACHE3 CACHE2 CACHE1 CACHE0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI configuration register 3 (PCICONF3) is a 32-bit read/partial-write register that includes the BIST function, header type, latency timer, and cache line size PCI configuration registers stipulated in the PCI local bus specification. The BIST function is read from bits 31 to 24, the header type from bits 23 to 16, the cache line size from bits 7 to 0. The guaranteed time for the PCIC to occupy the PCI bus when the PCIC is master is set in bits 15-8 (latency timer). Bits 15 to 8 can be written to. Other bits are fixed in hardware. The PCICONF3 register is initialized to H'00000000 at a power-on reset and software reset. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 865 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 31—BIST7: BIST function support Bit 31: BIST7 Description 0 Function not supported 1 Function supported (not supported) (Initial value) Bit 30—BIST6: Used to control the BIST starting. Bit 30: BIST6 Description 0 Execution completed 1 Executing (not supported) (Initial value) Bits 29 and 28—BIST5 and 4: These bits always return 0 when read. Bits 27 to 24—BIST3 to 0: BIST status on completion of operation. Bits 27 to 24: BIST3 to 0 Description H'0 Passed test H'1 to H'F Test failed (not supported) (Initial value) Bit 23—Multifunction Status (HEAD7): Shows whether the device is a multi-function unit or a single-function unit. Bit 23: HEAD7 Description 0 Single-function device 1 Device has between 2 and 8 functions (not supported) (Initial value) Bits 22 to 16—Configuration Layout Type (HEAD6 to 0): These bits indicate the layout type of the configuration register. Bits 22 to 16: HEAD6 to 0 Description H'00 Type 00h layout supported H'01 Type 01h layout supported (not supported) H'02 to H'3F Reserved Page 866 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 15 to 8—Latency Timer Register (LAT7 to 0): These bits specify the latency time of the PCI bus when the PCIC is operating as the master. Bits 7 to 0—Cache Line Size (CACHE7 to 0): Not supported. Memory target is set cachedisabled, and SDONE and SBO are ignored. 22.2.5 PCI Configuration Register 4 (PCICONF4) Bit: 31 30 29 28 27 26 25 24 BASE31 BASE30 BASE29 BASE28 BASE27 BASE26 BASE25 BASE24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit: BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W* R/W* R/W* R/W* PP Bus-R/W: R/W R/W R/W R/W R/W* R/W* R/W* R/W* 15 14 13 12 11 10 9 8 Bit: BASE15 BASE14 BASE13 BASE12 BASE11 BASE10 BASE9 BASE8 0 0 0 0 0 0 0 0 PCI-R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* PP Bus-R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* 7 6 5 4 3 2 1 0 BASE7 BASE6 BASE5 BASE4 BASE3 BASE2 — ASI Initial value: 0 0 0 0 0 0 0 1 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Initial value: Bit: Note: * These bits are read-only in the SH7751 and can be read from and written to in the SH7751R. PCI configuration register 4 (PCICONF4) is a 32-bit read/partial-write register that accommodates the I/O-space base address register, which is one of the PCI configuration registers that are R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 867 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group stipulated in the PCI's local-bus specifications. PCICONF4 holds the higher-order bits of the address used when a device on the PCI bus uses I/O transfer commands to access a local register in the PCIC. In the SH7751, the 12 higher-order bits (bits 31 to 8) are set; in the SH7751R, the 24 higher-order bits are set. As the I/O space for the PCI bus, allocate 1 Mbyte of space for the SH7751 and 256 bytes of space for the SH7751R. In the SH7751, bits 30 to 20 are writable, and bits 19 to 2 and 0 are fixed by the hardware. In the SH7751R, bits 31 to 8 are writable, and bits 7 to 2 and 0 are fixed by the hardware. The PCICONF4 register is initialized to H'00000001 at a power-on reset and software reset. Always write to this register prior to executing I/O transfers (accessing the local registers in the PCIC) to or from the PCIC from the PCI bus. Bits 31 to 8—Base Address of the I/O Space (BASE 31 to 8): Sets the base address of the local registers (I/O space) in the PCIC. In the SH7751, bits 19 to 8 are fixed to H'000 in hardware. Bits 7 to 2—Base Address of the I/O Space (BASE 7 to 2): Fixed at H'00 in hardware. Bit 1—Reserved: This bit always returns 0 when read. Always write 0 to this bit. Bit 0—Address Space Indicator (ASI): Shows whether the base address specified by this register is an I/O space or memory space. Bit 0: ASI Description 0 Memory space 1 I/O space Page 868 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.2.6 Section 22 PCI Controller (PCIC) PCI Configuration Register 5 (PCICONF5) Bit: 31 30 29 28 27 26 25 24 BASE031 BASE030 BASE029 BASE028 BASE027 BASE026 BASE025 BASE024 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit: BASE023 BASE022 BASE021 BASE020 BASE019 BASE018 BASE017 BASE016 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R R R R PP Bus-R/W: R/W R/W R/W R/W R R R R 15 14 13 12 11 10 9 8 Bit: BASE015 BASE014 BASE013 BASE012 BASE011 BASE010 BASE09 BASE08 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 BASE07 BASE06 BASE05 BASE04 LA0PREF LA0TYPE1 LA0TYPE0 LA0ASI Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI configuration register 5 (PCICONF5) is a 32-bit read/partial-write register that accommodates the memory space base address PCI configuration register stipulated in the PCI local bus specifications. This register holds the high bits (12 max. in bits 31 to 20) of the address used when a device on the PCI bus accesses local memory on the SH local bus using memory transfer commands. Allocate at least the capacity set in the local space register 0 (PCILSR0) as PCI bus memory space. Bits 19 to 0 are fixed in hardware. Of writable bits 31 to 20, those that hold valid values differ according to the value set in PCILSR0. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 869 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Table 22.6 Memory Space Base Address Register (BASE0) PCILSR0 [28:20] Register Value Required Address Space BASE0[31:20] Valid Writable Bits B'0_0000_0000 1 MB Bits 31 to 20 B'0_0000_0001 2 MB Bits 31 to 21 B'0_0000_0011 4 MB Bits 31 to 22 : : : B'0_1111_1111 256 MB Bits 31 to 28 B'1_1111_1111 512 MB Bits 31 to 29 The PCICONF5 register is initialized to H'00000000 at a power-on reset and software reset. Always write to this register before transferring data to and from the PCIC memory from the PCI bus. Bits 31 to 20—Base Address of the Memory Space 0 (BASE0 31 to 20): These bits specify the base address of the local address space 0 (this LSI external bus space). Bits 19 to 4—Base Address of the Memory Space 0 (BASE0 19 to 4): Fixed at H'0000 in hardware. Bit 3—Pre-fetch Control (LA0PREF): Shows availability of prefetching of the local address space 0. Bit 3: LA0PREF Description 0 Prefetch disabled 1 Prefetch enabled (not supported) (Initial value) Bits 2 and 1—LA0TYPE1 and 0: In the case of I/O space, can be set as the base address. Shows the memory type of the local address space 0. Bit 2: LA0TYPE1 Bit 1: LA0TYPE0 Description 0 0 Base address can be set to 32-bit width, 32-bit space (Initial value) 1 Base address can be set to 32-bit width, less than 1MB space (not supported) 0 Base address is 64-bit width (not supported) 1 Reserved 1 Page 870 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 0—LA0ASI: Shows whether the base address specified by this register is an I/O space or memory space. Bit 0: LA0ASI Description 0 Memory space 1 I/O space 22.2.7 (Initial value) PCI Configuration Register 6 (PCICONF6) Bit: 31 30 29 28 27 26 25 24 BASE131 BASE130 BASE129 BASE128 BASE127 BASE126 BASE125 BASE124 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit: BASE123 BASE122 BASE121 BASE120 BASE119 BASE118 BASE117 BASE116 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R R R R PP Bus-R/W: R/W R/W R/W R/W R R R R 15 14 13 12 11 10 9 8 Bit: BASE115 BASE114 BASE113 BASE112 BASE111 BASE110 BASE19 BASE18 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 BASE17 BASE16 BASE15 BASE14 LA1PREF LA1TYPE1 LA1TYPE0 LA1ASI Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI configuration register 6 (PCICONF6) is a 32-bit read/partial-write register that accommodates the memory space base address PCI configuration register stipulated in the PCI R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 871 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group local bus specifications. This register contains the most significant bits (maximum 12 in bits 31 to 20) of the address used when a device on the PCI bus accesses local memory on the SH local bus using memory transfer commands. Minimally, allocate the capacity set in the local space register 1 (PCILSR1) to PCI bus memory space. Bits 19 to 0 are fixed in hardware. The number of valid bits of those that can be written to (bit 31 to 20) differs according to the value set in PCILSR1. Table 22.7 Memory Space Base Address Register (BASE1) PCILSR1 [28:20] Register Value Required Address Space Valid BASE1 [31:20] Write Bits B'0_0000_0000 1 MB Bits 31 to 20 B'0_0000_0001 2 MB Bits 31 to 21 B'0_0000_0011 4 MB Bits 31 to 22 : : : B'0_1111_1111 256 MB Bits 31 to 28 B'1_1111_1111 512 MB Bits 31 to 29 The PCICONF6 register is initialized to H'00000000 at a power-on reset and software reset. Always write to this register prior to transferring data to or from the PCIC memory from the PCI bus. Bits 31 to 20—Base Address of the Memory Space 1 (BASE1 31 to 20): Specifies the base address of the local address space 1 (this LSI external bus space). Bits 19 to 4—Base Address of the Memory Space 1 (BASE1 19 to 4): Fixed at H'0000 in hardware. Bit 3—Pre-fetch Control (LA1PREF): Shows whether the local address space 1 can be prefetched. Bit 3: LA1PREF Description 0 Prefetch disabled 1 Prefetch enabled (not supported) Page 872 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 2 and 1—Memory Type (LA1TYPE1 to 0): These bits indicate the memory type of the local address space 1. Bit 2: LA1TYPE1 Bit 1: LA1TYPE0 Description 0 0 The base address can be set to 32-bit width, 32-bit space (Initial value) 1 The base address can be set to 32-bit width, but less than 1MB (not supported) 1 0 The base address has 64-bit width (not supported) 1 Reserved Bit 0—Address Space Indicator (LA1ASI): Shows whether the base address specified by this register is an I/O space or memory space. Bit 0: LA1ASI Description 0 Memory space 1 I/O space 22.2.8 (Initial value) PCI Configuration Register 7 (PCICONF7) to PCI Configuration Register 10 (PCICONF10) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bits 31 to 0—Reserved: These bits are always read as 0. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 873 of 1128 Section 22 PCI Controller (PCIC) 22.2.9 SH7751 Group, SH7751R Group PCI Configuration Register 11 (PCICONF11) Bit: 31 30 29 28 27 26 25 24 SSID15 SSID14 SSID13 SSID12 SSID11 SSID10 SSID9 SSID8 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 SSID7 SSID6 SSID5 SSID4 SSID3 SSID2 SSID1 SSID0 — — — — — — — — PP Bus-R/W: Bit: Initial value: PCI-R/W: PP Bus-R/W: Bit: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 SVID15 SVID14 SVID13 SVID12 SVID11 SVID10 SVID9 SVID8 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 SVID7 SVID6 SVID5 SVID4 SVID3 SVID2 SVID1 SVID0 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: Bit: PP Bus-R/W: The PCI configuration register 11 (PCICONF11) is a 32-bit read/write register that accommodates the subsystem ID and subsystem vendor ID PCI configuration registers stipulated in the PCI local bus specifications. The register contains the ID of the add-in board that this LSI is installed on its subsystem (bits 31 to 16) as well as the subsystem vendor ID (bits 15 to 0). All bits can be written to from the PP bus. The PCICONF11 register is not initialized at a reset. Always initialize this register while the CFINIT bit (bit 0) of the PCICR register is cleared. Bits 31 to 16—SSID15 to 0: Specifies the subsystem ID. Page 874 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 15 to 0—SVID15 to 0: Specifies the PCI subsystem vendor ID. 22.2.10 PCI Configuration Register 12 (PCICONF12) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bits 31 to 0—Reserved: These bits are always read as 0. 22.2.11 PCI Configuration Register 13 (PCICONF13) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 CAPPTR7 CAPPTR6 CAPPTR5 CAPPTR4 CAPPTR3 CAPPTR2 CAPPTR1 CAPPTR0 Initial value: 0 1 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI configuration register 13 (PCICONF13) is a 32-bit read-only register that accommodates the extended function pointer PCI configuration register stipulated in the PCI power management specifications. The address offset of the extended function is read from bits 7 to 0. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 875 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group All bits are fixed in hardware. Bits 31 to 8—Reserved: These bits are always read as 0. Bits 7 to 0—CAPPTR7 to 0: These bits specify the address offset of the extended functions (power management). The initial value is H'40 (fixed). 22.2.12 PCI Configuration Register 14 (PCICONF14) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bits 31 to 0—Reserved: These bits are always read as 0. Page 876 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.13 PCI Configuration Register 15 (PCICONF15) Bit: 31 30 29 28 27 26 25 24 MLAT7 MLAT6 MLAT5 MLAT4 MLAT3 MLAT2 MLAT1 MLAT0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 MGNT7 MGNT6 MGNT5 MGNT4 MGNT3 MGNT2 MGNT1 MGNT0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 IPIN7 IPIN6 IPIN5 IPIN4 IPIN3 IPIN2 IPIN1 IPIN0 Initial value: 0 0 0 0 0 0 0 1 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ILIN7 ILIN6 ILIN5 ILIN4 ILIN3 ILIN2 ILIN1 ILIN0 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W Initial value: The PCI configuration register 15 (PCICONF15) is a 32-bit read/partial-write register that accommodates the maximum latency, minimum grant, interrupt pin, and interrupt line PCI configuration registers stipulated in the PCI local bus specifications. The interrupt pins used by this LSI is read from bits 15 to 8. Bits 7 to 0 indicate to which of the interrupt request signal lines of an interrupt controller the interrupt line is connected. Bits 31 to 8 are fixed in hardware. Bits 7 to 0 can be written to from both the PP bus and PCI bus. The PCICONF15 register is initialized to H'00000100 at a power-on reset and software reset. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 877 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 24—Designation of Maximum Latency (MLAT7 to 0): These bits specify the maximum time from the time the PCI master device demands bus privileges and to the time it obtains the privileges (not supported). Bits 23 to 16—Minimum Latency Specification (MGNT 7 to 0): Specify the burst interval required by the PCI device (not supported). Bits 15 to 8—Interrupt Pin Specification (IPIN7 to 0) Bits 15 to 8: IPIN7 to 0 Description H'01 INTA used H'02 INTB used H'03 INTC used H'04 INTD used H'05 to H'FF Reserved bits (Initial value) Bits 7 to 0—Interrupt Line Specification (ILIN7 to 0): Specifies an interrupt line of a system to which interrupt output used by the PCIC is connected. Page 878 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.14 PCI Configuration Register 16 (PCICONF16) Bit: 31 30 29 28 27 PMESPT4 PMESPT3 PMESPT2 PMESPT1 PMESPT0 26 25 24 D2SPT D1SPT — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — DS1 — PMECLK VER2 VER1 VER0 Initial value: 0 0 0 0 0 0 0 1 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 NIP7 NIP6 NIP5 NIP4 NIP3 NIP2 NIP1 NIP0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 CAPID7 CAPID6 CAPID5 CAPID4 CAPID3 CAPID2 CAPID1 CAPID0 Initial value: 0 0 0 0 0 0 0 1 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI configuration register 16 (PCICONF16) is a 32-bit read/partial-write register than accommodates the power management function (PMC), next-item pointer, and extended function ID power management registers stipulated in the PCI power management specifications. PCICONF16 is valid only when the PCIC is functioning not as the host. The power management related functions are read from bits 31 to 16 (PMC), the address offset of the next function in the extended function list is read from bits 15 to 8 (next item pointer), and the power management ID (H'01) is read from bits 7 to 0 (extended function ID). Bits 18 to 16 can be written to from the PP bus only. Other bits are fixed in hardware. The PCICONF16 regsiter is initialized to H'00010001 at a power-on reset and a software reset. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 879 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 27—PME Support (PMESPT4 to 0): Not supported. Defines the function state supporting PME output. Bit 26—D2 Support (D2SPT): Not supported. Specifies whether D2 state is supported. Bit 25—D1 Support (D1SPT): Not supported. Specifies whether D1 state is supported. Bits 24 to 22—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 21—DSI: Specifies whether bit-device-specific initialization is required. Bit 20—Reserved: This bit always returns 0 when read. Always write 0 to this bit. Bit 19—PME Clock (PMECLK): Not supported. Specifies whether a clock is required for PME support. Bits 18 to 16—Version (VER2 to 0): Specify the version of power management specifications. Bits 15 to 8—Next Item Pointer (NIP7 to 0): Specify the offset to the next extended function register Bits 7 to 0—Extended Function ID (CAPID7 to 0): Extended function (Capability Identifier) ID. These bits always return H'01 when read. Page 880 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.15 PCI Configuration Register 17 (PCICONF17) Bit: 31 30 29 28 27 26 25 24 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 PMEST DTATSCL1 DTATSCL0 DATASEL3 DATASEL2 DATASEL1 DATASEL0 PMEEN Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — PWRST1 PWRST0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R/W R/W PP Bus-R/W: R R R R R R R/W R/W The PCI configuration register 17 (PCICONF17) is a 32-bit read/partial-write register that accommodates the power management control/status (PMCSR), bridge-compatible PMCSR extended (PMCSR_BSE), and data power management registers stipulated in the PCI power management specifications. PCICONF17 is valid only when the PCIC is operating not as the host. Bits 31 to 24 (data) and bits 23 to 16 (PMCSR_BSE) are not supported. The power management status is read from bits 15 to 0 (PMCSR). Bits 1 and 0 can be written to from both the PP bus and the PCI bus. Other bits are fixed in hardware. PCICONF17 is initialized to H'00000000 at a power-on reset and software reset. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 881 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group When B'11 is written to bits 1 and 0 and a transition is made to power state D3 (power down mode), PCIC operation as a master target is disabled, regardless of the setting of bits 2 to 0 of the PCICONF1 (bus master control, memory and I/O space access control) (these bits are masked). When B'00 is written to bits 1 and 0 and a transition is made to power state D0 (normal operating mode), the mask is canceled. Bits 31 to 24—DATA (DATA7 to 0): Not supported. Data field for power management. Bits 23 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 15—PME Status (PMEST): Not supported. Shows the status of the PME bit. This bit is set when the signal is output. Bits 14 and 13—Data Scale (DTATSCL1 to 0): Not supported. These bits specify the scaling value for the data field value. Bits 12 to 9—Data Select (DATASEL3 to 0): Not supported. Select the value to be output to the data field. Bit 8—PME Enable (PMEEN): Not supported. Controls the PME signal output. Bits 7 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bits 1 and 0—Power State (PWRST1 and 0): Specifies the power state. No state transition is effected when a non-supported state is specified. (Normal termination, no error output.) Bit 1: PWRST1 Bit 0: PWRST0 Description 0 0 D0 state (Initial value, normal state) 1 D1 state (not supported) 0 D2 state (not supported) 1 D3 state (power down mode) 1 Page 882 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.16 Reserved Area Reserved area. Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Note: PCI configuration addresses H'48 to H'FC are reserved. Bits 31 to 0—Reserved: These bits always return 0 when read. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 883 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.17 PCI Control Register (PCICR) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — TRDSGL BYTESWAP Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R/W R/W PP Bus-R/W: R R R R R R R/W R/W Bit: 7 6 5 4 3 2 1 0 PCIPUP BMABT MD10 MD9 SERR INTA RSTCTL CFINIT Initial value: 0 0 0/1* 0/1* 0 0 0 0 PCI-R/W: R R R R R R R R R/W R/W R R R/W R/W R/W R/W PP Bus-R/W: Note: * The value of the external pin is sampled in a power-on reset by means of the RESET pin. The PCI control register (PCICR) is a 32-bit register that monitors the status of the mode pin at initialization and controls the basic operation of the PCIC. Bits 5 (MD10) and 4 (MD9) are readonly bits from the PP bus. Other bits are read/write bits. Bits 9 (TRDSGL) and 8 (BYTESWAP) are read/write bits from the PCI bus. Other bits are read-only. In PCIC host operation, a software reset can be applied to the PCI bus by means of bit 1 (RSTCTL) of PCICR. When a software reset is executed, the PCIRST pin is asserted and the internal state of the PCIC is initialized. Page 884 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) The PCICR register is initialized at a power-on reset to H'000000*0 (bits 7 and 6 are initialized to B'00, and bits 5 and 4 sample the value of mode pins 9 and 10). At a software reset, bit 1 (RSTCTL) is not initialized. All other bits are initialized in the same way as at a software reset. This register can be written to only when bits 31 to 24 are H'A5. Always set bit 0 (CFINIT) to 1 on completion of PCIC register initialization. Bits 31 to 10—Reserved: These bits are always read as 0. When writing, write H'A5 to bits 31 to 24, and 0 to others. Bit 9—Target Read Single Buffer (TRDSGL): This bit specifies whether one target read buffer (32 bytes) or two target read buffers (64 bytes) are used for target memory read access to the PCIC. When two target read buffers faces are used, the data from two buffers are read via the local bus in advanced. Bit 9: TRDSGL Description 0 Use 2 target read buffers 1 Use 1 target read buffer only (Initial value) Bit 8—Data Byte Swap (BYTESWAP): Specifies whether the data byte is swapped when the PCIC performs PIO transfer. Bit 8: BYTESWAP Description 0 Send data as-is 1 Swap data byte before sending (Initial value) Note: For details, refer to section 22.4, Endians. Bit 7—PCI Signal Pull-up (PCIUP): Controls the pull-up resistance of the PCI signal. Regarding the pins that are subject to pull-up, refer to table 22.1. Regarding the pull-up control provided when the PCIPEQ2/MD9, PCIREQ3/MD10 or PCIREQ4 is used as a port, refer to the section on port control register (PCIPCTR). Bit 7: PCIUP Description 0 Pull-up 1 No pull-up R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 (Initial value) Page 885 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 6—Bus Master Arbitration (BMABT): Controls the PCI bus arbitration mode of the PCIC when the PCIC is operating as the host. When the PCIC is non-host, the value of this bit is ignored. Bit 6: BMABT Description 0 Fixed priority order (device 0 (PCIC) > device 1 > device 2 > device 3 > device 4) (Initial value) 1 Pseudo round-ribbon (The priority level of the device with bus privileges is set lowest at the next access.) Bit 5—Mode 10 Pin Monitor (MD10): Monitors the PCIREQ3/MD10 pin value in a power-on reset by means of the RESET pin. Bit 5: MD10 Description 0 Host bridge function (arbitration) enabled 1 Host bridge function disabled Bit 4—Mode 9 Pin Monitor (MD9): Monitors the PCIREQ2/MD9 pin value in a power-on reset by means of the RESET pin. Bit 4: MD9 Description 0 PCICLK used as PCI clock 1 Feedback input clock from CKIO used as PCI clock Bit 3—SERR Output (SERR): Software control of SERR output. This bit is valid only when bit 8 (SER) of the PCICONFI register is “1”. When “1” is written to this bit, SERR is asserted for 1 clock. This bit always returns “0” when read. Used when the PCIC is not the host. If used when the PCIC is the host, an SERR assert interrupt is generated to the CPU. Bit 3: SERR Description 0 SERR pin at Hi-Z (driven to High by pull-up resistor) 1 Assert SERR (Low output) Page 886 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 2—INTA Output (INTA): Software control of INTA (valid only when PCIC is not host) Bit 2: INTA Description 0 INTA pin at Hi-Z (driven to High by pull-up resistor) 1 Assert INTA (Low output) (Initial value) Bit 1—PCIRST Output Control (RSTCTL): Controls the PCIRST output. This field is reset only at a power-on reset. Do not use the field when the PCIC is non-host. Bit 1: PCIRST Description 0 Negate PCIRST (High output) 1 Assert PCIRST (Low output) (Initial value) Bit 0—PCIC Internal Register Initialization Control Bit (CFINIT): After the SH initializes the PCI registers, setting this bit enables access from the PCI bus. During initialization, no bus privileges are granted to other devices on the PCI bus while operating as the host. When operating not as the host, a retry is returned without the access from the PCI bus being accepted. Bit 0: CFINIT Description 0 Initialization busy 1 Initialization complete R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 (Initial value) Page 887 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.18 PCI Local Space Register [1:0] (PCILSR [1:0]) Bit: 31 30 29 — — — Initial value: 0 0 0 28 27 26 25 24 PLSR28 PLSR27 PLSR26 PLSR25 PLSR24 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 — — — — PLSR23 PLSR22 PLSR21 PLSR20 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R R/W R/W R/W R/W R R R R 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R PP Bus-R/W: Bit: The PCI local space register [1:0] (PCILSR [1:0]) specifies the capacities of the two local address spaces (address space 0 and address space 1) supported when a device on the PCI bus performs a memory read/memory write of the PCIC using target transfers. This is a 32-bit register that can be read and written from the PP bus, or read only from the PCI bus. The PCILSR [1:0] register is initialized to H'00000000 at a power-on reset and software reset. Always write to this register before performing target transfers to specify the capacity of the address space being used. Specify the value “(capacity –1) bytes” in bits 28 to 20. For example, to secure a 32MB space, set the value H'01F00000. Page 888 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) If you specify all zeros, a 1MB space is reserved. You can specify an address space up to 512MB. Refer to table 22.6 in section 22.2.6, PCI Configuration Register 5 (PCICONF5). Bits 31 to 29—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bits 28 to 20—Capacities of the Local Address Spaces 0, 1 (PLSR28 to 20): These bits specify the capacities of the address space 0 and address space 1 in bytes. Specifying (capacity –1) bytes. A 1MB space is secured if all zeros are specified. Bits 19 to 0—Reserved: These bits always return 0 when read. Always write 0 to these bits. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 889 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.19 PCI Local Address Register [1:0] (PCILAR [1:0]) Bit: 31 30 29 28 27 26 25 24 — — — LAR28 LAR27 LAR26 LAR25 LAR24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 LAR23 LAR22 LAR21 LAR20 — — — — 0 0 0 0 0 0 0 0 Initial value: PCI-R/W: PP Bus-R/W: Bit: R R R R R R R R R/W R/W R/W R/W R R R R 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI local address register [1:0] (PCILAR [1:0]) specifies the starting address (external address of local bus) of the two local address spaces (address space 0 and address space 1) supported when performing memory read/memory write operations due to target transfers to the PCIC. It is a 32-bit register that can be read and written from the PP bus and is read-only from the PCI bus. The PCILAR [1:0] register is initialized to H'00000000 at a power-on reset and software reset. The valid bits of the local address specified by this register vary according to the capacity of the address space specified in the PCILSR [1:0] register. In other words, set 0 in the least significant address bit which corresponds to the capacity set by PCILSR0, 1, and set the starting address only Page 890 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) in the most significant address bit. For example, when the capacity of the local address space is set to 32MB (PCILSR: H'01F00000), bits 28 to 25 of the local address are valid. Only the value set in these bits is used as the physical address of the local address space. Always write to this register prior to target transfers. Specify the starting address (physical address) of the memory installed on the local bus according to the address space being used. Bits 28 to 26 of the PCI local address register 0 select the local address area. Bits 25 to 20 show the address within that area. Bits 31 to 29—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bits 28 to 20—Local Address (LAR28 to 20): Specify bits 28 to 20 of the starting address of the local address space. Bits 19 to 0—Reserved: These bits always return 0 when read. Always write 0 to these bits. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 891 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.20 PCI Interrupt Register (PCIINT) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — M_LOCK T_TGT_A ON BORT Initial value: TGT_RET MST_DIS RY 0 0 0 0 0 0 0 0 PCI-R/W: R/WC R/WC R R R R R/WC R/WC PP Bus-R/W: R/WC R/WC R R R R R/WC R/WC 7 6 5 4 3 2 1 0 Bit: ADRPER SERR_D T_DPER T_PERR_ M_TGT_A M_MST_ M_DPER M_DPER R ET R_WT DET BORT ABORT R_WT R_RD Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC PP Bus-R/W: R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC Note: WC: Cleared by writing “1”. (Writing of 0 is ignored.) The PCI interrupt register (PCIINT) is a 32-bit register that saves the error source when an error occurs on the PCI bus as a result of the PCIC attempting to invoke a transfer on the PCI bus, or when the PCIC is the PCI master or PCI target. This register can be read from both the PP bus and PCI bus. Also, 1 can be written from either the PP bus or PCI bus to perform a write-clear in which the detection bit is cleared to its initial value (0). The PCIINT register is initialized to H'00000000 at a power-on reset or software reset. Page 892 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) When an error occurs, the bit corresponding to the error content is set to 1. Each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it. (Write clear) Note that the error detection bits can be set even when the interrupt is masked. The error source holding circuit can only store one error source. For this reason, any second or subsequent error factors are not stored if errors occur consecutively. Bits 31 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 15—Unlocked Transfer Detection Interrupt (M_LOCKON): When the PCIC is master, an unlocked PIO transfer was performed when the I-specified target was locked. Bit 14—Target Target Abort Interrupt (T_TGT_ABORT): Indicates the termination of transaction by target abort when the PCIC is a target. Target abort is generated when the 2 least significant address bits (bits 1, 0) and byte enable constitute an illegal combination (illegal byte enable) during I/O transfer. Bits 13 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 9—Target Memory Read Retry Timeout Interrupt (TGT_RETRY): When the PCIC is target, the master did not attempt a retry within the prescribed number of PCI bus clocks (215) (detected only in the case of memory read operations). Bit 8—Master Function Disable Error Interrupt (MST_DIS): Indicates that an attempt was made to conduct a master operation (PIO transfer, DMA transfer) when bit 2 (BUM) of the PCICONF1 was set to 0 to prohibit bus master operations. Bit 7—Address Parity Error Detection Interrupt (ADRPERR): Address parity error detected. Detects only when bit 6 (PER) and bit 8 (SER) of the PCICONF1 are both 1. Bit 6—SERR Detection Interrupt (SERR_DET): When the PCIC is host, assertion of the SERR signal was detected. Bit 5—Target Write Data Parity Error Interrupt (T_DPERR_WT): When the PCIC is target, a data parity error was detected while receiving a target write transfer (only detected when PCICONFI bit 6 (PER) is 1). Bit 4—Target Read PERR Detection Interrupt (T_PERR_DET): When the PCIC is target, PERR was detected when receiving a target read transfer. Detects only when bit 6 (SER) of the PCICONF1 is 1. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 893 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 3—Master Target Abort Interrupt (M_TGT_ABORT): When the PCIC is master. Indicates the termination of transaction by target abort. Bit 2—Master Master Abort Interrupt (M_MST_ABORT): When the PCIC is master. Indicates the termination of transaction by master abort. Bit 1—Master Write PERR Detection Interrupt (M_DPERR_WT): When the PCIC is master. PERR received from the target while writing data to the target. Detects only when bit 6 (PER) of the PCICONF1 is 1. Bit 0—Master Read Data Parity Error Interrupt (M_DPERR_RD): When the PCIC is master, a parity error was detected during a data read from the target. Detects only when bit 6 (PER) of the PCICONF1 is 1. Page 894 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.21 PCI Interrupt Mask Register (PCIINTM) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — M_LOCK T_TGT_A ON BORT Initial value: TGT_RET MST_DIS RY 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R R R R R/W R/W PP Bus-R/W: R/W R/W R R R R R/W R/W 7 6 5 4 3 2 1 0 Bit: ADRPER SERR_D T_DPER T_PERR_ M_TGT_A M_MST_ M_DPER M_DPER R ET R_WT DET BORT ABORT R_WT R_RD Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W The PCI interrupt mask register (PCIINTM) sets the respective interrupt masks for the interrupts generated when errors occur in PCI transfers. It is a 32-bit read/write register that can be accessed from both the PP bus and PCI bus. When set to 0, the respective interrupt is disabled, and enabled when set to 1. The PCIINTM register is initialized to H'00000000 at a power-on reset and software reset. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 895 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 15—Unlocked Transfer Detection Interrupt Mask (M_LOCKON) Bit 14—Target Target Abort Interrupt Mask (T_TGT_ABORT) Bits 13 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 9—Target Retry Timeout Interrupt Mask (TGT_RETRY) Bit 8—Master Function Disable Error Interrupt Mask (MST_DIS) Bit 7—Address Parity Error Detection Interrupt Mask (ADRPERR) Bit 6—SERR Detection Interrupt Mask (SERR_DET) Bit 5—Target Write Data Parity Error Interrupt Mask (T_DPERR_WT) Bit 4—Target Read PERR Detection Interrupt Mask (T_PERR_DET) Bit 3—Master Target Abort Interrupt Mask (M_TGT_ABORT) Bit 2—Master Master Abort Interrupt Mask (M_MST_ABORT) Bit 1—Master Write Data Parity Error Interrupt Mask (M_DPERR_WT) Bit 0—Master Read Data Parity Error Interrupt Mask (M_DPERR_RD) Page 896 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.22 PCI Address Data Register at Error (PCIALR) Bit: 31 30 29 28 27 26 25 24 ALOG31 ALOG30 ALOG29 ALOG28 ALOG27 ALOG26 ALOG25 ALOG24 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 ALOG23 ALOG22 ALOG21 ALOG20 ALOG19 ALOG18 ALOG17 ALOG16 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 ALOG9 ALOG8 Initial value: ALOG15 ALOG14 ALOG13 ALOG12 ALOG11 ALOG10 — — — — — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ALOG7 ALOG6 ALOG5 ALOG4 ALOG3 ALOG2 ALOG1 ALOG0 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI address data register at error (PCIALR) stores the PCI address data (ALOG [31:0]) of errors that occur on the PCI bus. It is a 32-bit register that can be read from both the PP bus and PCI bus. The PCIALR register is not initialized at a power-on reset or software reset. The initial value is undefined. A valid value is retained only when one of the PCIINT register bits is set to 1. The error source holding circuit can only store one error source. For this reason, any second or subsequent error factors are not stored if errors occur consecutively. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 897 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 0—Address Log (ALOG31 to 0): PIC address data (value of A/D line) at time of error. (Initial value is undefined.) 22.2.23 PCI Command Data Register at Error (PCICLR) Bit: 31 30 29 28 27 MSTPIO MSTDMA0 MSTDMA1 MSTDMA2 MSTDMA3 26 25 24 TGT — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — Initial value: 0 0 0 0 — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R CMDLOG3 CMDLOG2 CMDLOG1 CMDLOG0 The PCI command data register at error (PCICLR) stores the type of transfer (MSTPIO, MSTDMA0, MSTDMA1, MSTDMA2, MSTDMA3, or TGT) when an error occurs on the PCI bus, and the PCI command (CMDLOG [3:0]). It is a 32-bit register that can be read from both the PP bus and PCI bus. Although bits 31 to 26 of the PCICLR register are initialized at a power-on reset and a software reset, bits 3 through 0 are not initialized. When an error is detected, 1 is set in one of bits 31 to 26, and the relevant command value is retained in bits 3 to 0. Page 898 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) A valid value is retained only when one of the PCIINT register bits is set to 1. The error source holding circuit can only store one error source. For this reason, any second or subsequent error factors are not stored if errors occur consecutively. Bit 31—PIO Error (MSTPIO): Error occurred in PIO transfer. Bit 30—DMA0 Error (MSTDMA0): Error occurred in DMA channel 0 transfer. Bit 29—DMA1 Error (MSTDMA1): Error occurred in DMA channel 1 transfer. Bit 28—DMA2 Error (MSTDMA2): Error occurred in DMA channel 2 transfer. Bit 27—DMA3 Error (MSTDMA3): Error occurred in DMA channel 3 transfer. Bit 26—Target Error (TGT): Error occurred in target read or target write transfer. Bits 25 to 4—Reserved: These bits are always read as 0. Bits 3 to 0—Command Log (CMDLOG3 to 0): These bits retain the PCI transfer command information (value of C/BE line) upon detection of an error. (Initial value is undefined.) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 899 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.24 PCI Arbiter Interrupt Register (PCIAINT) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — MST_BRKN — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R/WC R/WC R/WC R R R PP Bus-R/W: R R R/WC R/WC R/WC R R R Bit: 7 6 5 4 3 2 1 0 — — — — DPERR_WT DPERR_RD Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R/WC R/WC R/WC R/WC PP Bus-R/W: R R R R R/WC R/WC R/WC R/WC TGT_BUSTO MST_BUSTO TGT_ABORT MST_ABORT Note: Cleared by writing WC:1. (Writing of 0 is ignored.) The PCI arbiter interrupt register (PCIAINT) is a 32-bit register that stores the sources of PCI bus errors occurring during transfers by another PCI master device when the PCIC is operating as the host with the arbitration function. The register can be read from both the PP bus and the PCI bus. Also, each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it from either the PP bus or the PCI bus. (Write clear) The PCIAINT register is initialized to H'00000000 at a power-on reset or software reset. Page 900 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) When an error is detected, the bit corresponding to the error type is set to 1. Each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it. (Write clear) The error detection bits are set even when the interrupts are masked. Bits 31 to 14—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 13—Master Broken Interrupt (MST_BRKN): Detects when the master granted with bus privileges does not start a transaction (FRAME not asserted) within 16 clocks. For the SH7751, see 22.12, Usage Notes. Bit 12—Target Bus Timeout Interrupt (TGT_BUSTO): Neither TRDY nor STOP are not returned within 16 clocks in the case of the first data transfer, or within 8 clocks in the case of second and subsequent data transfers. For the SH7751, see 22.12, Usage Notes. Bit 11—Master Bus Timeout Interrupt (MST_BUSTO): Indicates the detection that IRDY was not asserted within 8 clock cycles in a transaction initiated by a device including PCIC. Bits 10 to 4—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 3—Target Abort Interrupt (TGT_ABORT): Indicates the termination of transaction by target abort when a device other than the PCIC is operating as the bus master. Bit 2—Master Abort Interrupt (MST_ABORT): Indicates the termination of transaction by master abort when a device other than the PCIC is operating as the bus master. Bit 1—Write Data Parity Error Interrupt (DPERR_WT): Indicates the detection of the assertion of PERR in a data write operation when a device other than the PCIC is operating as the bus master. Bit 0—Read Data Parity Error Interrupt (DPERR_RD): Indicates the detection of the assertion of PERR in a data read operation when a device other than the PCIC is operating as the bus master. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 901 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — MST_BRKN — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R/W R/W R/W R R R PP Bus-R/W: R R R/W R/W R/W R R R Bit: 7 6 5 4 3 2 1 0 — — — — DPERR_WT DPERR_RD Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R/W R/W R/W R/W PP Bus-R/W: R R R R R/W R/W R/W R/W TGT_BUSTO MST_BUSTO TGT_ABORT MST_ABORT The PCI arbiter interrupt mask register (PCIAINTM) sets interrupt masks for the individual interrupts that occur due to errors generated during PCI transfers performed by other PCI devices when the PCIC is operating as the host with the arbitration function. It is a 32-bit register that is readable and writable from both the peripheral bus and the PCI bus. Each bit is set to 0 to disable the respective interrupt, or 1 to enable that interrupt. The PCIINTM register is initialized to H'00000000 at a power-on reset or software reset. Bits 31 to 14—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Page 902 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 13—Master Broken Interrupt Mask (MST_BRKN) Bit 12—Target Bus Timeout Interrupt Mask (TGT_BUSTO) Bit 11—Master Bus Timeout Interrupt Mask (MST_BUSTO) Bits 10 to 4—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 3—Target Abort Interrupt Mask (TGT_ABORT) Bit 2—Master Abort interrupt Mask (MST_ABORT) Bit 1—Read Data Parity Error Interrupt Mask (DPERR_WT) Bit 0—Write Data Parity Error Interrupt Mask (DPERR_RD) 22.2.26 PCI Error Bus Master Data Register (PCIBMLR) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — Initial value: 0 0 0 — — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R REQ4ID REQ3ID REQ2ID REQ1ID REQ0ID The PCI error bus master data register (PCIBMLR) stores the device number of the bus master at the time an error occurred in PCI transfer by another PCI device when the PCIC was operating as the host with the arbitration function. It is a 32-bit register than can be read from both the PP bus and PCI bus. The PCIINTM register is initialized to H'00000000 at a power-on reset or software reset. A valid value is retained only when one of the PCIAINT register bits is set to 1. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 903 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group The bus master data holding circuit can only store data for one master. For this reason, no bus master data is stored for any second or subsequent errors if errors occur consecutively. Bits 31 to 5—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 4—REQ4 Error (REQ4ID): Error occurred when device 4 (REQ4) was bus master. Bit 3—REQ3 Error (REQ3ID): Error occurred when device 3 (REQ3) was bus master. Bit 2—REQ2 Error (REQ2ID): Error occurred when device 2 (REQ2) was bus master. Bit 1—REQ1 Error (REQ1ID): Error occurred when device 1 (REQ1) was bus master. Bit 0—REQ0 Error (REQ0ID): Error occurred when device 0 (REQ0) was bus master. 22.2.27 PCI DMA Transfer Arbitration Register (PCIDMABT) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — DMABT Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R/W PP Bus-R/W: R R R R R R R R/W The PCI DMA transfer arbitration register (PCIDMABT) is a register that controls the arbitration mode in the case of DMA transfers. Two types of DMA arbitration mode can be selected: priorityfixed and pseudo round-robin. This 32-bit read/write register can be accessed from both the PP bus and PCI bus. The PCIDMABT register is initialized to H'00000000 at a power-on reset or software reset. Always write to this register to specify the DMA transfer arbitration mode prior to starting DMA transfers. Page 904 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 31 to 1—Reserved: These bits always returns 0 when read. Always write 0 to these bits when writing. Bit 0—DMA Arbitration Mode (DMABT): Controls the DMA arbitration mode. Bit 0: DMABT Description 0 Priority-fixed (Channel 0 > Channel 1 > Channel 2 > Channel 3) (Initial value) 1 Pseudo round-robin 22.2.28 PCI DMA Transfer PCI Address Register [3:0] (PCIDPA [3:0]) Bit: 31 30 29 28 27 26 25 24 PDPA31 PDPA30 PDPA29 PDPA28 PDPA27 PDPA26 PDPA25 PDPA24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit: PDPA23 PDPA22 PDPA21 PDPA20 PDPA19 PDPA18 PDPA17 PDPA16 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Bit: PDPA15 PDPA14 PDPA13 PDPA12 PDPA11 PDPA10 PDPA9 PDPA8 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PDPA7 PDPA6 PDPA5 PDPA4 PDPA3 PDPA2 PDPA1 PDPA0 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W Initial value: Bit: Initial value: R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 905 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group The DMA transfer PCI address register [3:0] (PCIDPA [3:0]) specifies the starting address at the PCI when performing DMA transfers. This 32-bit read/write register can be accessed from both the PP bus and PCI bus. The PCIDPA register is initialized to H'00000000 at a power-on reset and a software reset. The transfer address of a byte boundary or character boundary can be set, but the 2 least significant bits of this register are ignored, and the data of the longword boundary is transferred. Before starting a DMA transfer, be sure to write to this register. After a DMA transfer starts, the value in the register is not retained. Always re-set the register value before starting a new DMA transfer after a DMA transfer has been completed. Bits 31 to 0—DMA Transfer PCI Starting Address (PDPA31 to 0): Set the PCI starting address for DMA transfer. Page 906 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.29 PCI DMA Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0]) Bit: 31 30 29 — — — 28 27 26 25 24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R/W R/W R/W R/W R/W PP Bus-R/W: R R R R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 PDLA28 PDLA27 PDLA26 PDLA25 PDLA24 PDLA23 PDLA22 PDLA21 PDLA20 PDLA19 PDLA18 PDLA17 PDLA16 Initial value: 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Bit: PDLA15 PDLA14 PDLA13 PDLA12 PDLA11 PDLA10 0 0 PDLA9 PDLA8 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PDLA7 PDLA6 PDLA5 PDLA4 PDLA3 PDLA2 PDLA1 PDLA0 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W Initial value: Bit: Initial value: The DMA transfer local bus start address register [3:0] (PCIDLA [3:0]) specifies the starting address at the local bus when performing DMA transfers. This 32-bit read/write register can be accessed from both the PP bus and PCI bus. The PCIDLA register is initialized to H'00000000 at a power-on reset and a software reset. The transfer address of a byte boundary or character boundary can be set, but the 2 least significant bits of the register are ignored, and the data of the longword boundary is transferred. Note that the local bus starting address set in this register is the external address of the SH bus. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 907 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Always write to this register prior to starting DMA transfers. After a DMA transfer starts, the register value is not retained. Always re-set this register before starting a new DMA transfer after a DMA transfer has completed. Bits 31 to 29—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bits 28 to 0—DMA Transfer Local Bus Starting Address (PDLA28 to 0): These bits set the starting address of the local bus (external address of SH bus) for DMA transfer. Bits 28 to 26 indicate the local bus area. 22.2.30 PCI DMA Transfer Counter Register [3:0] (PCIDTC [3:0]) Bit: 31 30 29 28 27 26 25 24 — — — — — — PTC25 PTC24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R/W R/W PP Bus-R/W: R R R R R R R/W R/W Bit: 23 22 21 20 19 18 17 16 PTC23 PTC22 PTC21 PTC20 PTC19 PTC18 PTC17 PTC16 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PTC15 PTC14 PTC13 PTC12 PTC11 PTC10 PTC9 PTC8 Initial value: Bit: Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: Page 908 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) The DMA transfer counter register [3:0] (PCIDTC [3:0]) specifies the number of bytes for DMA transfers. This 32-bit read/write register can be accessed from both the PP bus and PCI bus. When read during a DMA transfer, it returns the remaining number of bytes in the DMA transfer. The PCIDTC register is initialized to H'00000000 at a power-on reset and a software reset. Bits 25 to 0 are used to specify the number of transfer bytes. When set to H'00000000, the maximum 64MB transfer is performed. Since the transfer data size corresponds only to longword data, the 2 least significant bits are ignored. Always write to this register prior to starting a DMA transfer. Please re-set this register when starting a new DMA transfer after a DMA transfer completes. Bits 31 to 26—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bits 25 to 0—DMA Transfer Byte Count (PTC25 to 0): Specify the number of bytes in DMA transfer. The maximum number of transfer bits are 64 MB (when set to H'00000000). R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 909 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0]) Bit: 31 30 29 ... 19 18 17 16 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — Initial value: 0 0 0 0 0 0 0 0 ALNMD10 ALMMD9 DMAST PCI-R/W: R R R R R R/W R/W R PP Bus-R/W: R R R R R R/W R/W R Bit: 7 6 5 4 3 2 1 0 DMAIM DMAIS LAHOLD — IOSEL0 DIR 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/WC R/W R R/W R/W R/W R/W PP Bus-R/W: R/W R/WC R/W R R/W R/W R/W R/W Initial value: DMASTOP DMASTRT Note: Cleared by writing WC:1. (Writing of 0 is ignored.) The DMA transfer control register [3:0] (PCIDCR [3:0]) specifies the operating mode of the respective channels and the method of transfer, etc. This 32-bit read/write register can be accessed from the PP bus and PCI bus. The PCIDCR register is initialized to H'00000000 at a power-on reset and software reset. Writing 1 to bit 0 (DMASTRT) starts DMA transfer. Always re-set the value in this register before starting a new DMA transfer after completion of a DMA transfer. When setting the DMASTOP bit, do not write 1 to the DMASTART bit. Also, write the same setting at the start of transfer to the DMAIM, DMAIS, LAHOLD, IOSEL and DIR bits. Example: Starting transfer with PCIDCR = H'00000085 Forced DMA termination PCIDCR = H'00000086 If DMA is forcibly terminated with a value other than the setting used in the transfer being performed, data accuracy is not guaranteed. Page 910 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 31 to 11—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bits 10 and 9—Alignment Mode (ALNMD): Sets data alignment when local bus is big endian Bit 10: ALNMD10 Bit 9: ALNMD9 Description 0 0 Byte boundary mode 1 W/LW boundary mode 1 (LW data is sent as byte × 4) 1 (Initial value) 0 W/LW boundary mode 2 (LW data is sent as word × 2) 1 W/LW boundary mode 3 (LW data is sent as longword) Legend: W: Word LW: Longword Note: For details, refer to section 22.4, Endians. Bit 8—DMA Transfer End Status (DMAST): Indicates the DMA transfer end status. Bit 8: DMAST Description 0 Normal termination 1 Abnormal termination (Error detection or forced DMA transfer termination) (Initial value) Bit 7—DMA Transfer Termination Interrupt Mask (DMAIM): Specifies the DMA transfer termination interrupt mask. Bit 7: DMAIM Description 0 Interrupt disabled 1 Interrupt enabled (Initial value) Bit 6—DMA Transfer Termination Interrupt Status (DMAIS): Indicates the DMA transfer termination interrupt status. The interrupt status is set even when the interrupt mask is set. Bit 6: DMAIS When writing When reading Description 0 Ignored 1 Status clear 0 Interrupt not detected 1 Interrupt detected R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 (Initial value) Page 911 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 5—Local Address Control (LAHOLD): Local address control during DMA transfer Bit 5: LAHOLD Description 0 Incremented 1 High address fixed (Address A[4:0] is incremented) (Initial value) Bit 4—Reserved: This bit always returns 0 when read. Always write 0 to this bit. Bit 3—PCI Address Space Type (IOSEL): Type of PCI address space during transfer Bit 3: IOSEL Description 0 Memory space 1 I/O space (Initial value) Bit 2—Transfer Direction (DIR): Transfer direction during DMA transfer Bit 2: DIR Description 0 Transfer from PCI bus to local bus (SH bus) 1 Transfer from local bus (SH bus) to PCI bus (Initial value) Bit 1—Forced DMA Transfer Termination (DMASTOP): Forced termination of DMA transfer Bit 1: DMASTOP When writing Description 0 Writing of 0 is ignored. 1 Forced termination of DMA transfer When reading When DMA transfer stops due to forced DMA transfer termination, 1 is set Bit 0—DMA Transfer Start Control (DMASTRT): Controls the starting of DMA transfer. Bit 0: DMASTRT When writing When reading Page 912 of 1128 Description 0 Ignored 1 Start 0 End of transfer 1 Busy (in transfer) (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.32 PIO Address Register (PCIPAR) Bit: 31 30 29 28 27 26 25 24 CFGEN — — — — — — — Initial value: 1 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 BUSNO23 BUSNO22 BUSNO21 BUSNO20 BUSNO19 BUSNO18 BUSNO17 BUSNO16 Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — — — — — — — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 DEVNO15 DEVNO14 DEVNO13 DEVNO12 DEVNO11 FNCNO10 FNCNO9 FNCNO8 Initial value: — — — — — — — — PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — — PP Bus-R/W: Bit: REGADR7 REGADR6 REGADR5 REGADR4 REGADR3 REGADR2 Initial value: — — — — — — 0 0 PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R R PP Bus-R/W: The PIO address register (PCIPAR) is used when issuing configuration cycles on the PCI bus when the PCIC is host. The PCIC supports the configuration mechanism 1 stipulated in the PCI local bus specifications. This register is equivalent to the configuration register of configuration mechanism 1. This register is equivalent to the CONFIG_ADDRESS of configuration mechanism 1. The check that the issuance of the PCI configuration cycle is enabled, and access the PCI configuration space, this register contains the PCI bus No., device No., Function No., and LW (longword) boundary of the configuration register. This 32-bit read/write register can be accessed from the PP bus. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 913 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 31 (CFGEN) is set in hardware and none of the other bits of the PCIPAR register are initialized at a power-on reset or software reset. Always write to this register prior to accessing the PCI configuration space. After setting a value in this register, generate the configuration cycle by reading or writing to the PIO data register (PCIPDR). Also, a special cycle is issued by setting H'8000FF00 in this register and writing to the PCIPDR. Bit 31—Configuration Cycle Generate Enable (CFGEN): Indicates the configuration cycle generation enable. Bits 30 to 24—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bits 23 to 16—PCI Bus No. (BUSNO): These bits specify the No. of the PCI bus subject to configuration access. Bus No. D indicates the bus connected with the PCIC. The bus No. is expressed with 8 bits, and its maximum value is 255. Bits 15 to 11—Device No. (DEVNO): These bits specify the No. of the device subject to configuration access. The device No. is expressed with 5 bits, and takes a value from bits 0 to 31. In place of IDSEL, one of bits 31 to 16 of the A/D line, corresponding to the device No. set in this field, is driven to “1”. The following table shows the relationship between the device No. and IDSEL (A/D [31 to 16]). When the device No. is 10h or greater, A/D [31 to 16]) are all zeros. DEVNO IDSEL DEVNO IDSEL DEVNO IDSEL DEVNO IDSEL H'0 AD[16] = 1 H'4 AD[20] = 1 H'8 AD[24] = 1 H'C AD[28] = 1 H'1 AD[17] = 1 H'5 AD[21] = 1 H'9 AD[25] = 1 H'D AD[29] = 1 H'2 AD[18] = 1 H'6 AD[22] = 1 H'A AD[26] = 1 H'E AD[30] = 1 H'3 AD[19] = 1 H'7 AD[23] = 1 H'B AD[27] = 1 H'F AD[31] = 1 Bits 10 to 8: Function No. (FNCNO): These bits specify the No. of the function subject to configuration access. The function No. is expressed with 3 bits, and takes a value of 0 to 7. Bits 7 to 2—Configuration Register Address (REGADR): These bits set the register subject to configuration access with a longword boundary. Bits 1 and 0—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Page 914 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.33 Memory Space Base Register (PCIMBR) Bit: 31 30 29 28 27 26 25 24 MBR31 MBR30 MBR29 MBR28 MBR27 MBR26 MBR25 MBR24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PP Bus-R/W: Bit: PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — LOCK Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R/W The memory space base register (PCIMBR) specifies the most significant 8 bits of the address of the PCI memory space when performing a memory read/write operation using PIO transfers. It also specifies locked transfers. This 32-bit read/write register can be accessed from the PP bus. All bits of the PCIMBR register are initialized to 0 at a power-on reset. They are not initialized at a software reset. Setting bit 0 (LOCK) to 1 locks the memory space for PIO transfers while the bit remains set. A locked transfer consists of the combined read and write operations. Do not attempt to perform other PIO transfers during the locked combination of read and write operations. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 915 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Always write to this register prior to performing memory read/write operations by PIO transfer. Bits 31 to 24—Memory Space Base Address (MBR31 to 24): Sets the base address for the PCI memory space in PIO transfers. (Initial value is undefined.) Bits 23 to 1—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 0—Lock Transfer (LOCK): Specifies the locking of the memory space during PIO transfer. Bit 0: LOCK Description 0 Not locked 1 Locked Page 916 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.34 I/O Space Base Register (PCIIOBR) Bit: Initial value: PCI-R/W: PP Bus-R/W: Bit: 31 30 29 28 27 26 25 24 IOBR31 IOBR30 IOBR29 IOBR28 IOBR27 IOBR26 IOBR25 IOBR24 0 0 0 0 0 0 0 0 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 IOBR23 IOBR22 IOBR21 IOBR20 IOBR19 IOBR18 — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R R 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — LOCK Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R/W PP Bus-R/W: Bit: The I/O space base register (PCIIOBR) species the most significant 14 bits of the address of the PCI I/O space when performing I/O read and I/O write operations by PIO transfer. It also specifies locked transfers. This 32-bit read/write register can be accessed from the PP bus. All bits of the PCII0BR register are initialized to 0 at a power-on reset. They are not initialized at a software reset. Setting bit 0 (LOCK) to 1 locks the I/O space for PIO transfers while the bit remains set. A locked transfer consists of the combined read and write operations. Do not attempt to perform other PIO transfers during the locked combination of read and write operations. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 917 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Always write to this register prior to I/O space read and I/O space write operations by PIO transfer. Bits 31 to 18—I/O Space Base Address (IOBR31 to 18): Sets the base register for the PCI I/O space in PIO transfers. Bits 17 to 1—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 0—Lock Transfer (LOCK): Specifies the locking of the I/O space during PIO transfer. Bit 0: LOCK Description 0 Not locked 1 Locked (Initial value) 22.2.35 PCI Power Management Interrupt Register (PCIPINT) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: — — — ... — — — — PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — PWRST_ PWRST_ D3 D0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R/WC R/WC Note: Cleared by setting WC: 1. (Writing of 0 is ignored.) The PCI power management interrupt register (PCIPINT) controls the power management interrupts. It provides the interrupt bits for a transition to the power state D3 (power down mode) and recovery to the power state D0 (normal state). This 32-bit read/write register can be accessed from the PP bus. Page 918 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) The PCIPINT register is initialized to H'00000000 at a power-on reset. It is not initialized at a software reset. When an interrupt is detected, the bit corresponding to the content of that interrupt is set to 1. Each interrupt detection bit can be cleared to 0 by writing 1 to it (write clear). The power state D0 interrupt is not generated at a power-on reset. Bits 31 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 1—Power state D3 (PWRST_D3): Transition request to power-down mode interrupt for this LSI. Bit 0—Power state D0 (PWRST_D0): Restore from power-down mode interrupt for this LSI. Note: The power states D3, D0 are not masked even when the interrupt mask bit is set ON. 22.2.36 PCI Power Management Interrupt Mask Register (PCIPINTM) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: — — — ... — — — — PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R/W R/W DPERR_ DPERR_ WT RD The PCI power management interrupt mask register (PCIPINTM) sets the interrupt mask for the power management interrupts. This 32-bit read/write register can be accessed from the PP bus. The PCIPINTM register is initialized to H'00000000 at a power-on reset. It is not initialized at a software reset. Interrupt masks can be set for both the interrupt for a transition to the power state D3 (power down mode) and recovery to the power state D0 (normal status). Setting the respective bit to 0 disables the interrupt and setting it to 1 enables the interrupt. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 919 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 1—Power State D3 (DPERR_WT): Transition request to power-down mode interrupt mask for this LSI. Bit 0—Power State D0 (DPERR_RD): Restore from power-down mode interrupt mask for this LSI. 22.2.37 PCI Clock Control Register (PCICLKR) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: — — — ... — — — — PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — PCICLKS BCLKST TOP OP Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R/W R/W The PCI clock control register (PCICLKR) controls the stopping of the local bus clock (BCLK) in the PCIC and the PCI bus clock. This 32-bit read/write register can be accessed from the PP bus. The PCICLKR register is initialized to H'00000000 at a power-on reset. It is not initialized at a software reset. When the PCI bus clock is input from the external input pin PCICLK, the PCI bus clock can be stopped by setting the PCICLKSTOP bit to 1. Likewise, the local bus clock can be stopped by setting the BCLKSTOP bit to 1. When the PCI bus clock is input via the CKIO pin, setting BCLKSTOP to 1 stops both the Bck in the PCIC and the feedback input clock from CKIO. Writing to this register is valid only when bits 31 to 24 are H'A5. Page 920 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 31 to 2—Reserved: These bits are always read as 0. When writing, always write H'A5 to bits 31 to 24, and 0 to the other bits. Always write 0 to these bits when writing. Bit 1—PCICLK Stop Control (PCICLKSTOP): Controls the stopping of the clock input via the PCICLK pin. Bit 1: PCICLKSTOP Description 0 PCICLK input enabled value) 1 Stop PCICLK input (Initial Bit 0—BCLK Stop Control (BCLKSTOP): Controls the stopping of the Bck input clock and CKIO input clock in the PCIC. Bit 0: BCLKSTOP Description 0 Bck input enabled value) 1 Stop Bck input (Initial 22.2.38 PCIC-BSC Registers PCIC Bus Control Register 1 (PCIBCR1) PCIC Bus Control Register 2 (PCIBCR2) PCIC Bus Control Register 3 (PCIBCR3)*1 PCIC Wait Control Register 1 (PCIWCR1) PCIC Wait Control Register 2 (PCIWCR2) PCIC Wait Control register 3 (PCIWCR3) PCIC Discrete Memory Control Register (PCIMCR) Because PCI bus data is stored, in the PCIC, in memory on the local bus, the PCIC is equipped with an internal bus controller (PCIC-BSC). The PCIC-BSC performs the same type of control as the slave function of the bus controller (BSC). However, the PCIC-BSC returns bus rights to the BSC after each data transfer of up to 32 bytes of data. There are six registers in the PCIC-BSC: PCIBCR1 (equivalent to the BCR1 of the BSC), PCIBCR2 (equivalent to the BCR2 of the BSC), PCIBCR3 (equivalent to the BCR3 of the BSC)*1, PCIWCR1 (equivalent to the WCR1 of the BSC), PCIWCR2 (equivalent to the WCR2 of the BSC), PCIWCR3 (equivalent to the WCR3 of the BSC), and PCIMCR (equivalent to the MCR of the BSC). Each is a 32-bit register. BCR2 and BCR3 are 16-bit registers, but PCIBCR2 and PCIBCR3 should be accessed by longword access. The low 16 bits of PCIBCR2 and PCIBCR3 corresponds to the 16 bits of these registers, respectively. See section 13, Bus State Controller (BSC), for details of the initial values, etc. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 921 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group • The PCIC-BSC performs the same operations as the slave mode of the BSC. Therefore, the MATER bit of the PCI bus control register 1 (PCIBCR1) shows the slave status. • Because the PCIC-BSC operates in slave mode, the bus privilege is handed to the BSC once per bus cycle. • The external memory capable of data transfers to the PCI bus is SRAM, DRAM, synchronous DRAM, and MPX*2. • The memory data width is 32-bit or 16-bit only (only 32-bit in the case of synchronous DRAM). • Do not specify other external memory types (burst ROM, MPX, byte control SRAM or PCMCIA) as the external memory for data transfers with the PCI bus. • Because the PCIC-BSC operates in slave mode, the RAS-down mode of DRAM and SDRAM is not available. • The local bus supports both big and little endian. However, the PCI bus supports only little endian. The PCI-BSC does not support mode register setting of synchronous DRAM nor refreshing of synchronous DRAM or DRAM. These must be executed by the BSC. Also, do not implement any settings that are not allowed in slave mode in the PCIC-BSC registers. This is because bit 30: master/slave flag (MASTER) of the PCIBCR1 is fixed Low, regardless of the value of the external master/slave setting pin (MD7) at a power-on reset, and the PCIC-BSC therefore is set in slave mode. In the case of external memory not used for data transfers with the PCI bus, make the same settings as the corresponding bus state controller register. These registers are initialized at a power-on reset, but not by a software reset. Notes: 1. This register is provided only in the SH7751R, not provided in the SH7751. 2. MPX is supported only in the SH7751R, not supported in the SH7751. Page 922 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.39 Port Control Register (PCIPCTR) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 — — — — — — — — PORT2EN PORT1EN PORT0EN Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — PB2PUP PB2IO PB1PUP PB1IO PB0PUP PB0IO Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R/W R/W R/W R/W R/W R/W The port control register (PCIPCTR) selects whether to enable or disable port function allocation for pins for unwanted PCI bus arbitration when the PCIC is used in non-host mode. It also specifies the swithing ON/OFF of pin pull-up resistances and between input and output. This 32bit read/write register can be accessed from the PP bus. The PCIPCTR register is initialized to H'00000000 at a power-on reset. It is not initialized at a software reset. When the PCIC is operating as host, the port function cannot be used if the arbitration function is enabled. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 923 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 19—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 18—Port 2 Enable (PORT2EN): Provides the enable control for the port 2. Bit 18: PORT2EN Description 0 Do not use pins PCIGNT4 or PCIREQ4 as ports 1 Use pins PCIGNT4 or PCIREQ4 as ports (Initial value) Bit 17—Port 1 Enable (PORT1EN): Provides the enable control for the port 1. Bit 17: PORT1EN Description 0 Do not use pins PCIGNT3 or PCIREQ3 as ports 1 Use pins PCIGNT3 or PCIREQ3 as ports (Initial value) Bit 16—Port 0 Enable (PORT0EN): Provides the enable control for the port 0. Bit 16: PORT0EN Description 0 Do not use pins PCIGNT2 or PCIREQ2 as ports 1 Use pins PCIGNT2 or PCIREQ2 as ports (Initial value) Bits 15 to 6—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 5—Port 2 Pull-up Resistance Control (PB2PUP): Controls pull-up resistance when PCIREQ4 pin is used as port. Bit 5: PB2PUP Description 0 Pull-up PCIREQ4 pin 1 Do not pull-up PCIREQ4 pin (Initial value) Bit 4—Port 2 Input/Output Control (PB2IO): Controls input or output when PCIREQ4 is used as a port. Bit 4: PB2IO Description 0 Set PCIREQ4 pin for input 1 Set PCIREQ4 pin for output Page 924 of 1128 (Initial value) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 3—Port 1 Pull-up Resistance Control (PB1PUP): Controls pull-up resistance when PCIREQ3 pin is used as port. Bit 3: PB1PUP Description 0 Pull-up PCIREQ3 pin 1 Do not pull-up PCIREQ3 pin (Initial value) Bit 2—Port 1 Input/Output Control (PB1IO): Controls input or output when PCIREQ3 is used as a port. Bit 2: PB1IO Description 0 Set PCIREQ3 pin for input 1 Set PCIREQ3 pin for output (Initial value) Bit 1—Port 0 Pull-up Resistance Control (PB0PUP): Controls pull-up resistance when PCIREQ2 pin is used as port. Bit 1: PB0PUP Description 0 Pull-up PCIREQ2 pin 1 Do not pull-up PCIREQ2 pin (Initial value) Bit 0—Port 0 Input/Output Control (PB0IO): Controls input or output when PCIREQ2 is used as a port. Bit 0: PB0IO Description 0 Set PCIREQ2 pin for input 1 Set PCIREQ2 pin for output R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 (Initial value) Page 925 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.40 Port Data Register (PCIPDTR) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: — — — ... — — — — PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R/W R/W R/W R/W R/W R/W The port data register (PCIPDTR) inputs and outputs the port data when allocation of the port function to the unwanted PCI bus arbitration pins is enabled when the PCIC is operating in nonhost mode. This 32-bit read/write register can be accessed from the PP bus. The PCIPDTR register is intialized to H'00000000 at a power-on reset. It is not initialized at a software reset. Data is output in sync with the local bus clock. Input data is fetched at the rising edge of the local bus clock. Bits 31 to 6—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 5—Port 2 Output Data (PB5DT): Output data when PCIGNT4 pin is used as port. (PCIGNT4 pin is output-only.) Bit 4—Port 2 Input/Output Data (PB4DT): Receives input data and sets output data when the PCIREQ4 pin is used as a port. Bit 3—Port 1 Output Data (PB3DT): Output data when PCIGNT3 pin is used as port. (PCIGNT3 pin is output-only.) Bit 2—Port 1 Input/Output Data (PB2DT): Receives input data and sets output data when the PCIREQ3 pin is used as a port. Page 926 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 1—Port 0 Output Data (PB1DT): Output data when PCIGNT2 pin is used as port. (PCIGNT2 pin is output-only.) Bit 0—Port 0 Input/Output Data (PB0DT): Receives input data and sets output data when the PCIREQ2 pin is used as a port. 22.2.41 PIO Data Register (PCIPDR) Bit: 31 30 29 28 27 26 25 24 PPDA31 PPDA30 PPDA29 PPDA28 PPDA27 PPDA26 PPDA25 PPDA24 Initial value: — — — — — — — — PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 PP Bus-R/W: Bit: PPDA23 PPDA22 PPDA21 PPDA20 PPDA19 PPDA18 PPDA17 PPDA16 Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — — — — — — — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PPDA9 PPDA8 Initial value: PPDA15 PPDA14 PPDA13 PPDA12 PPDA11 PPDA10 — — — — — — — — PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PPDA7 PPDA6 PPDA5 PPDA4 PPDA3 PPDA2 PPDA1 PPDA0 Initial value: — — — — — — — — PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: Bit: PP Bus-R/W: The PIO data register (PCIPDR) sets the data for read/write in the PCI configuration cycle. This 32-bit read/write register can be accessed from the PP bus. The PCIPDR register is not initialized at a power-on reset or software reset. The initial value is undefined. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 927 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Always write to this register before accessing the PCI configuration space. Always read/write to this register after setting the value in the PIO address register (PCIPAR). The configuration cycle on the PCI bus can be generated by reading/writing to this register. Bits 31 to 0—PIO Configuration Data (PPDA31 to 0): Read/write register for configuration data in PIO transfers. The configuration cycle on the PCI bus can be generated by reading/writing to this register. 22.3 Description of Operation 22.3.1 Operating Modes The external mode pins (MD9 and MD10) select whether the PCIC operates as the host on the PCI bus and also select the bus clock for the PCI bus. The mode selection signals input via the external mode pins are fetched on negation of a power-on reset. Table 22.8 Operating Modes MD9 MD10 Operating Modes 0 0 The PCIC host functions are enabled and the external input via the PCICLK pin is the operating clock for the PCI bus 1 The PCIC host functions are enabled and this LSI bus clock (feedback input clock from CKIO pin) is the operating clock for the PCI bus 0 The PCIC host functions are disabled (non-host) and the input clock from the PCICLK pin is selected as the clock for the PCI bus 1 PCIC-disabled mode. In this mode, PCIC operation is disabled 1 Note: In PCIC-disabled mode, do not attempt to access the PCIC local registers. In this section, the clock resulting from the above mode switching is known as the PCI bus clock. Page 928 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.3.2 Section 22 PCI Controller (PCIC) PCI Commands Table 22.9 lists the PCI commands and shows the PCIC support. Table 22.9 PCI Command Support Host Operation Non-Host Operation Command Master Target Master Target Memory read O O O O Memory read line X Δ X Δ When the target, operates as memory read Memory read multiple X Δ X Δ When the target, operates as memory read Memory write O O O O Memory write and invalidate X Δ X Δ I/O read O O O O I/O write O O O O Configuration read O — — O Configuration write O — — O Interrupt acknowledge cycle X X X X Special cycle O — — X Dual address cycle X X X X Remarks When the target, operates as memory write Legend: O: Supported Δ: Limited support X, —: Not issued by PCIC or no response from PCIC When PCIC Operates as Master: The PCIC supports the memory read command, memory write command, I/O read command, and I/O write command. When the host functions are enabled, the configuration command and special cycle can also be used. When PCIC Operates as Target: The PCIC receives the memory read command, memory write command, I/O read command, and I/O write command. The memory read line command and memory read multiple command function as memory reads, while the memory write invalidate command functions as a memory write. When operating in non-host mode, the PCIC accepts the configuration command. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 929 of 1128 Section 22 PCI Controller (PCIC) 22.3.3 SH7751 Group, SH7751R Group PCIC Initialization After a power-on reset, the configuration register initialization bit (CFINIT) of the PCI control register (PCICR) is cleared. At this point, if the PCIC is operating as the PCI bus host, the bus privileges are permanently granted to the PCIC, and no device arbitration is performed on the PCI bus. When the PCIC is not operating as host, retries are returned without accepting access from PCI devices connected to the PCI bus. The PCIC's internal configuration registers and local registers must be initialized while the CFINIT bit is cleared to 0. On completion of initialization, set the CFINIT bit to 1. When operating as host, arbitration is enabled; when operating as non-host, the PCIC can be accessed from the PCI bus. Regardless of whether or not the PCIC is operating as host, external PCI devices cannot be accessed from the PCIC while the CFINIT bit is cleared. If the PCIC's internal configuration registers and local registers are initialized correctly, the PCIC will operate correctly. However, we recommend first setting the CFINIT bit to 1. When the PCIC is operating as the host, arbitration is enabled. When operating as non-host, the PCIC can be accessed from the PCI bus. Regardless of whether the PCIC is operating as the host or non-host, external PCI devices cannot be accessed from the PCIC while the CFINT bit is being cleared. Set the CFINIT bit to 1 before accessing an external PCIC device. Be sure to initialize the following 13 registers while the CFINIT bit is being cleared: configuration registers 1, 2, 11 (PCICONF1, 2, 11) for PCI, local space registers 0, 1 (PCILSR0, 1) for PCI, local address registers 0, 1 (PCILAR0, 1) for PCI, PCI bus control registers 1, 2 (PCIBCR1, 2) for PCIC-BSC, PCI weight control registers 1, 2, 3 (PCIWCR1, 2, 3), and PCI-specific memory control register (PCIMCR). Since the PCIC-BSC is fixed in sleep mode at a power-on reset regardless of the value of the external pin (MD7) for master/slave designation, do not make a PCIC-BSC register setting that is prohibited in the sleep mode. Also, as the BSC has BCR1.BREQEN bits that enable an external request and a bus request from the PCIC to be accepted, BCR1.BREQEN should be set to 1 when the PCIC is used. While 1 is being set in the CFINIT bit, the registers for the PCIC-BSC (PCIBCR1, 2, PCIWCR1, 2, 3, PCIMCR) cannot be written to. The data transfer accuracy between the PCI bus and local bus cannot be guaranteed if an attempt is made to write to any of these registers during this period. Page 930 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.3.4 Section 22 PCI Controller (PCIC) Local Register Access Only longword (32-bit) access of the PCIC's internal local registers and configuration registers from the CPU is supported. (It is possible to use PIO transfers to perform byte, word, and longword access of the memory space and I/O space on the PCI bus.) If an attempt is made to access these registers using other than the prescribed access size, zero is returned when reading and writing is ignored. The same is true if you attempt to access the reserved areas in the register area in the PCIC. Some of the configuration registers and local registers can be accessed both from the CPU and from the PCI device(s). Therefore, arbitration is performed for both types of access and either the CPU or PCI device access made to wait according to the access timing. In the read bus cycle from the CPU, the internal bus cycle for the peripheral module is made to wait until the data is actually ready. In the write bus cycle, the bus cycle of the internal bus for peripheral modules ends with the data having been written to the interface (register located immediately after the PCIC input) register on the internal bus for peripheral modules, but the data is not actually written to the local register(s) or PCI bus until the following clock cycle. If it is necessary to check that the data has actually been written, read the register to which the data was to have been written. This is because the read cycle must be after the write cycle has completed. When accessing from a PCI device, the PCI bus cycle is caused to wait until the read or write operation has actually completed. The internal bus for peripheral modules used for read/write operations from the CPU operates only with big endians. 22.3.5 Host Functions The PCIC has the following PCI bus host functions (host devices): • • • • • Inter-PCI device arbitration function Configuration register access function Special cycle generation function Reset output function Clock output function R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 931 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Inter-PCI Device Arbitration: The PCI bus arbitration circuit in the PCIC can be used when the PCIC is operating as the host device. The arbitration circuit can be connected to up to four external PCI devices (devices that can operate as master devices) that request bus privileges. If multiple bus privilege requests are made simultaneously by the PCI devices, the bus privilege is grated in the predetermined order of priority. There are two orders of priority: fixed, and pseudo round robin. The mode is selected by setting the bus master arbitration mode control bit (BMABT) of the PCI control register (PCICR). • Priority-fixed mode (BMABT = 0) In priority-fixed mode, the priority order of bus privilege requests is fixed and cannot be changed. The order is as follows: PCIC (device 0) > device 1 > device 2 > device 3 > device 4 That is, the PCIC has the highest order of priority and device 4 has the lowest. When bus privilege requests occur simultaneously, the device with the highest order of priority takes precedence. Here, device 1 is the PCI device using bus privilege request pins PCIREQ1 and PCIGNT1, device 2 uses PCIREQ2 and PCIGNT2, device 3 uses PCIREQ3 and PCIGNT3, and device 4 uses PCIREQ4 and PCIGNT4. When the PCIC is operating as the host device, no bus privilege request signals are output from the PCIC to the PCI bus arbitration circuit. • Pseudo round-robin mode (BMABT = 1) In pseudo round-robin mode, when a device takes the bus privilege, the priority order of that device becomes lowest. In the initial state, the priority order is set to the same as in the fixed mode. Here, device 1 outputs a bus privilege request, after which the priority order changes to … PCIC > device 2 > device 3 > device 4 > device 1. If the PCIC then outputs a bus privilege request and takes the bus privilege, the priority order changes to … Device 2 > device 3 > device 4 > device 1 > PCIC. Likewise, if device 3 outputs a bus privilege request and takes the bus privilege, the priority order becomes … Device 2 > device 4 > device 1 > PCIC > device 3. In this way, the priority order of the master device that takes the bus privilege always changes to lowest after the data transfer is completed. Page 932 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 1. Initial order of priority (transfer by device 1) PCIC > device 1 > device 2 > device 3 > device 4 2. Order of priority after transfer (transfer by PCIC) PCIC > device 2 > device 3 > device 4 > device 1 3. Order of priority after transfer (transfer by device 3) device 2 > device 3 > device 4 > device 1 > PCIC 4. Order of priority after transfer device 2 > device 4 > device 1 > PCIC > device 3 When the PCIC is operating as the host device, the PCIC performs the PCI bus parking (bus drive when not in use). When 3 or fewer master devices are connected, set the level of the unused pins of PCIREQ [4:1] high. In non-host mode, the PCI bus arbitration function of the PCIC is disabled. PCI bus arbitration is performed according to the specifications of the connected PCI bus arbiter. For details, see section 22.3.6, PCI Bus Arbitration in Non-host Mode. Configuration Register Access: The configuration register of external PCI devices can be accessed when the PCIC is operating as the host device. The PIO address register (PCIPAR) and PIO data register (PCIPDR) are used to generate a configuration read/write transfer for accessing the configuration register. The PCIC supports the configuration mechanism stipulated in the PCI local bus spec. First, specify in the PCIPAR the address of the configuration register of the external PCI device to be accessed. See section 22.2, PCIC Register Descriptions, for how to set the PCIPAR. Next, read data from the PCIPDR or write data to the PCIPDR. Only longword (32-bit) access of the PCIPDR is supported. Special Cycle Generation: When the PCIC operates as the host device, a special cycle is generated by setting H'8000FF00 in the PCIPAR and writing to the PCIPDR. Reset Output: When the PCIC is operating as the host device, PCIRST can be used to reset the PCI bus. See section 22.5, Resetting, for details of PCIRST. Clock Output: When the PCIC is operating as the host device and the bus clock (CKIO pin) is selected as the PCI bus clock, not only does the PCIC's PCI bus clock operate using the CKIO clock but the CKIO clock can also be used as the PCI bus clock. Thus, there is no requirement for an external PCI clock oscillation circuit. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 933 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group When using the CKIO clock, please note the limitations on CKIO clock frequency, stability, and load capacitance that can be connected to the CKIO pin. Check the clock oscillation circuit and electrical characteristics in section 10, Clock Oscillation Circuits, and section 23, Electrical Characteristics. 22.3.6 PCI Bus Arbitration in Non-host Mode When operating in non-host mode, the PCI bus arbitration function in the PCIC is disabled and PCI bus arbitration is performed according to the specifications of the externally connected PCI bus arbiter. In this case, the PCIC must request PCI bus privileges from the PCI bus arbiter (system host device). The PCIGNT1/REQOUT pins are used for the bus request signals, and the PCIREQ1/GNTIN pins are used for the bus grant signals. When the bus grant signals are asserted when the bus request signals are not asserted, the PCIC performs bus parking. Also, when the PCIC is used as a target device that does not request bus privileges, the PCIREQ1/GNTIN pins must be fixed at the high level. 22.3.7 PIO Transfers PIO transfer is a data transfer mode in which a peripheral bus is used to access the memory space and I/O space of the PCI bus. The following commands are supported in PIO transfer mode: • Memory read, memory write, I/O read, and I/O write • Locked transfer (High-speed back-to-back transfers are not supported.) In PIO transfer mode, only single transfers are supported. 32-byte burst transfers are not supported. In memory transfers and I/O transfers, the supported, so generate byte enable signals (BE[3:0]) to match the respective access sizes and output these signals to the PCI bus. Access sizes are byte, word, and longword. Locked transfers are supported only in the case of memory transfers and I/O transfers. High-speed back-to-back transfers are not supported. Page 934 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Memory Transfers: This section describes how PIO transfers are used to access memory space. 16MB between H'FD000000 and H'FDFFFFFF of area P4 (H'1D000000 to H'1DFFFFFF in area 7) is allocated as PCI memory address space. This space is used as the least significant 24 bits of the PCI address. However, in memory transfers, the two low bits of the PCI address are ignored, and B'00 is output to the PCI bus. The most significant 8 bits (MBR [31:24]) of the memory space base register (PCIMBR) are used as the most significant bits of the PCI address. These two addresses are combined to specify a 32-bit PCI address. To transfer to the memory space, first specify the most significant 8 bits of the PCI address in the PCIMBR, then access the PCI memory address space. If within the 16MB space, the PCI memory address space can be consecutively accessed simply by setting the PCIMBR once. If it is necessary to access an address space over the 16MB, set PCIMBR again. When performing locked transfers in memory transfer mode, set the PCIMBR memory space lock specification bit (LOCK). While the LOCK bit is set, the memory space is locked. Note the following when performing LOCK transfers: • A LOCK transfer consists of one read transfer and one write transfer. Always start with the read transfer. The system will operate correctly if you start with a write transfer, but the resource LOCK will not be established. Also, the system will operate correctly if you perform two LOCK read transfers, but the LOCK will be released at the next LOCK write transfer. • The minimum resource for which the LOCK is guaranteed is a 16-byte block. However, the system will operate correctly even if LOCK transfers are made to addresses other than where the LOCK is established. • You cannot access other targets while a target is LOCKed (from the LOCK read until the LOCK write). ⎯ PIO LOCK access of another target ends normally and transfers on the PCI bus are also generated. ⎯ Unlocked PIO transfer requests invoked between a LOCK read and LOCK write end normally, but no transfers are generated on the PCI bus. ⎯ DMA transfers are postponed until the LOCK transfer ends. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 935 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group H'FD000000 PCI memory space 16 Mbytes H'FDFFFFFF PCI memory space address 31 24 23 0 H'FD 31 24 23 2 0 00 PCI address 31 24 23 0 PCIMBR LOCK identifier Figure 22.2 PIO Memory Space Access I/O Transfers: This section describes how to access I/O space using PIO transfers. The 256KB from H'FE240000 to H'FE27FFFF of area P4 (H'1E240000 to H'1E27FFFF in area 7) is allocated as PCI I/O address space. This space is used for the least significant 18 bits of the PCI address. The most significant 14 bits (IOBR [31:18]) of the I/O space base register (PCIIOBR) are used as the most significant 14 bits of the PCI address. These two addresses are combined to specify the 32-bit PCI address. For transfers to the I/O space, first specify the most significant 14 bits of the PCI address in PCIIOBR, then access the PCI I/O address space. If within the 256KB space, you can access the PCI I/O address space consecutively simply by setting the PCIIOBR once. If it is necessary to access another address space beyond 256KB, set PCIIOBR again. When performing locked transfers in I/O transfers, set the I/O space lock specification bit (LOCK) in the PCIIOBR. The I/O space is locked while the LOCK bit is set. The same precautions apply to LOCK I/O transfers as to LOCK memory transfers. Page 936 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) H'FE200000 PCI register space 256 Kbytes PIC I/O space 256 Kbytes H'FE23FFFF H'FE240000 H'FE27FFFF 31 18 17 PCI I/O space H'FE24–H'FE27 address 0 31 18 17 0 PCI address 31 18 17 0 PCIIOBR LOCK identifier Figure 22.3 PIO I/O Space Access PIO Transfer Error: An error on the PCI bus that occurs in a transfer during a PIO write operation is not detected. When an error is generated during a PIO read operation, the PIO transfer is forcibly terminated to prevent effects on the DMA transfer and target transfer. However, accuracy of the read data is not guaranteed. 22.3.8 Target Transfers The following commands are available for transferring data in target transfers. • • • • • Memory read and memory write I/O read and I/O write (access to PCIC local registers) Configuration read, configuration write Locked transfer is supported. High-speed back-to-back, is not supported. When the PCIC is operating in non-host mode, no response is made on reception of special cycle commands. Memory Read/Memory Write Commands: In the case of memory read and memory write commands, both single transfers and burst transfers are supported on the PCI bus. Data on the PCI bus is always longword data, but BE[3:0] can be used to control the valid byte lane. In the case of memory read, longword data is always read from the local bus and output to the PCI bus. In the R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 937 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group case of memory write, the internal control allows only the writing of valid byte lane data to the local bus. Only the linear mode is supported for addressing for burst transfers, and the 2 least significant bits of the PCI address are regarded as B'00. If a memory read line command or memory read multiple command is received, they operate as memory reads. Similarly, when a memory write invalidate command is received, it functions as a memory write. Data must be set in the following registers prior to performing target transfers using memory read or memory write commands: PCI configuration register 5 (PCICNF5), PCI configuration register 6 (PCICNF6), PCI local space register 0 (PCILSR [0]), PCI local space register 1 (PCILSR [1]), PCI local address register 0 (PCILAR [0]), and PCI local address register 1 (PCILAR [1]). PCICONF5 (PCICONF6) 31 20 19 0 PCI address 31 0 PCIC access adjudication PCILSR0 (PCILSR1) PCILAR0 (PCILAR1) 31 28 20 19 0 000001111 31 28 20 19 0 31 28 0 Local address Figure 22.4 Local Address Space Accessing Method The PCIC supports two local address spaces (address space 0 and address space 1). A certain range of the address space on the PCI bus corresponds to the local address space. The local address space 0 is controlled by the PCICONF5, PCILAR0 and PCISR0. Figure 22.4 shows the method of accessing the local address space. Page 938 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) The PCICONF5 indicates the starting address of the memory space used by the PCI device. The PCILAR0 specifies the starting address of the local address space 0. The PCILSR0 expresses the size of the memory used by the PCI device. Regarding the method of setting each register, refer to section 22.2, PCIC Register Descriptions. For the PCICONF5 and PCILAR0, the most significant address bit that is higher than the memory size set in the PCILSR0 becomes valid. The most significant address bit of the PCICONF5 and the PCI address output from an external PCI device are compared for the purpose of determining whether the access is made to the PCIC. When the addresses correspond, the access to the PCIC is recognized, and a local address is generated from the most significant address bit of the PCILAR0 and the least significant bit of the PCI address output from the external PCI device. The PCI command is executed for this local address. If the most significant address bit of the PCI address output from the external PCI device does not correspond with the most significant address bit of the PCICONF5, the PCIC does not respond to the PCI command. Address space 1 is, like address space 0, controlled by the PCICONF6, PCILSR1, and PCILAR1. In this way, it is possible to set two address spaces. In systems with two or less local bus areas that can be accessed from the PCI bus, separate address spaces can be allocated to each of them. To make it possible to access two or more areas from the PCI bus, set the address spaces so that multiple areas are covered. In this case, we can assume that the address space includes areas for which no memory is installed. Note that, in this case, it is not possible to disable target transfers to areas for which no memory is installed. Note: See 22.3.11 (2), Target Read/Write Cycle Timing. I/O-Read and I/O-Write Commands: The local registers of the PCIC are accessed by means of a target transfer triggered by an I/O-read or I/O-write command. In the SH7751, accessing the local registers by means of I/O transfer is made possible by setting a base address that specifies 1 Mbyte of I/O space* in PCI configuration register 4 (PCICONF4). In the SH7751R, a base address that specifies 256 bytes of I/O space should be set. I/O-read and I/O-write commands only supports single transfers. The values of the byte-enable signals (BE [3:0]) are ignored, and longword accesses are carried out inside the PCIC. When executing an I/O-read and I/O-write commands transfer, specify B'0000 as the BE [3:0] value. Note that some of the local registers are not accessible from the PCI bus. For details, see section 22.2, PCIC Register Descriptions. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 939 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Note: * In version 2.1 of the PCI specifications the I/O space for PCI devices is defined as being no more than 256 bytes. As a result, when the SH7751 is used in a PCI non-host device, for example on an add-in card, it may be identified as an unusable device during device configuration because it requires an I/O space larger than 256 bytes. Configuration-Read and Configuration-Write Commands: When the PCIC operates as a nonhost device, the configuration registers of the PCIC are accessed by using configuration-read and configuration-write commands. Configuration access only supports single transfers. In the SH7751, the values of the byte-enable signals (BE [3:0]) are ignored, and longword accesses are carried out inside the PCIC*. In the SH7751R, the values of BE[3:0] are enabled. When executing a configuration-write operation, specify B'0000 as the BE [3:0] value. Note: * Version 2.1 of the PCI specifications specifies that any combination of byte-enable signal (BE[3:0]) values must be allowed when accepting a configuration access. As a result, when byte or word access is specified by the combination of BE[3:0], the remaining portion of the data in the longword unit is also overwritten by the write operation. Locked Transfer: Locked transfers are supported, but the locked space becomes the whole memory of the PCIC in the case of memory transfers, and becomes the whole register space in the case of I/O transfers or configuration transfers. While the memory is locked, retry is returned for all memory accesses of the PCIC from other PCI devices. Register access is, however, accepted. Similarly, while the registers are locked, retry is returned for all I/O accesses or configuration accesses of the PCIC from another PCI device, but memory access is accepted. 22.3.9 DMA Transfers DMA transfers allow the high-speed transfer of data between devices connected to the local bus and PCI bus when the PCIC has bus privileges as master. The following commands are supported in the case of DMA transfers: • Memory read, memory write, I/O read, and I/O write (Locked transfers are not supported.) (High-speed back-to-back transfers are not supported.) There are four DMA channels. In each channel, a maximum of 64MB can be set for each transfer, the number of transfer bytes and the starting address for the transfer being set at a longword boundary. Page 940 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) In DMA transfers, all transferred data is handled in long word units, so the number of transfer bytes and the low 2 bits of the transfer initial address are ignored and B'0000 is always output for BE[3:0]. Also, in DMA transfers, because burst transfers are effected using linear addressing, the low 2 bits of the output PCI address are always B'00. Note that locked transfers are not supported in the case of DMA transfers. Starting DMA Transfer: The following registers exist to control DMA transfers: PCI DMA transfer arbitration register (PCIDMABT) and, for four channels, the PCI DMA transfer PCI address register [3:0] (PCIDPA [3:0]), PCI DMA transfer local bus starting address register [3:0] (PCIDLA [3:0]), PCI DMA transfer count register [3:0] (PCIDTC [3:0]), and PCI DMA control register [3:0] (PCIDCR [3:0]). Set the arbitration mode in PCIDMABT prior to starting the DMA transfer. Also select the DMA channel to be used, set the PCI bus starting address and local bus starting address in the appropriate PCIDPA and PCIDLA for the selected channel, respectively, set the number of bytes in the transfer in PCIDTC, set the DMA transfer mode in the PCIDCR, and specify a transfer start request. The transfer starting address and the number of bytes in the transfer can be set on byte or word boundaries, but because the least significant two bits of these registers are ignored, the transfer is performed in longword units. Also, note that the local bus starting address set in PCIDLA is the physical address. PCIDPA, PCIDLA, and PCIDTC are updated during data transfer. If another DMA transfer is to be performed on completion of one DMA transfer, new values must be set in these registers. The registers controlling DMA transfers can be set from both CPU and PCI device. Note that the DMA channel allocated to the CPU and PCI device must be predetermined when configuring the system. When performing DMA transfers, the address of the local bus and the size of data to be transferred can be set to a 32-byte boundary to ensure that data transfers on the local bus are as efficient as possible. PCIDCR can be used to control the abortion of DMA transfers, the direction of DMA transfers, to select PCI commands (memory/I/O) whether to update the PCI address, whether to update the local address, whether to use transfer termination interrupts, and, when the local bus is big endian, the method of alignment. Figure 22.5 shows an example of DMA transfer control register settings. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 941 of 1128 Section 22 PCI Controller (PCIC) 31 SH7751 Group, SH7751R Group 1 0 PCIDMABT Arbitration mode H'0000 0000 H'0000 0004 31 28 0 PCIDLA Local address . . . . 0: Fixed priority 1: Pseudo round-robin External memory space Area 0: H'00000000 to H'03FFFFFF Area 1: H'04000000 to H'07FFFFFF Area 2: H'0800 0000 to H'0BFFFFFF Area 3: H'0C000000 to H'0FFFFFFF Area 4: H'10000000 to H'13FFFFFF . . . H'1BFF FFFC Area 5: H'14000000 to H'17FFFFFF Area 6: H'18000000 to H'1BFFFFFF 32 bits 31 26 25 0 DMA transfer PCIDTC Transfer count PCI memory/ I/O space H'0000 0000 H'0000 0004 H'0000 000C . . . 31 0 PCIDPA PCI address . . . H'FFFF FFFC 32 bits 31 11 10 0 Transfer control PCIDCR Figure 22.5 Example of DMA Transfer Control Register Settings Page 942 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) DMA Transfer End: The following describes the status on termination of a DMA transfer. • Normal termination DMA transfer ends after the set number of bytes has been transferred. In the case of normal termination, the DMA end status bit (DMAST) of the PCIDCR and the DMA transfer start control bit (DMASTART) are cleared, and the DMA transfer termination interrupt status bit (DMAIS) is set. If the DMA transfer interrupt mask bit (DMAIM) is set to 1, the DMA transfer termination interrupt is issued. Note that the DMAIS bit is set even if the DMAIM bit is set to 0. The DMAIS bit is maintained until it is cleared. Therefore, the DMAIS bit must be cleared before starting the next DMA transfer. • Abnormal termination The DMA transfer may terminate abnormally if an error on the PCI bus is detected during data transfer or the DMA transfer is forcibly terminated. ⎯ Error in data transfer When an error occurs during DMA transfer, the DMA transfer is forcibly terminated on the channel in which the error occurred. There is no effect on data transfers on other channels. ⎯ Forced termination of DMA transfer When the PCIDCR and DMASTOP bits for a channel are set, data transfer on that channel is forcibly terminated. However, when the DMASTOP bit is set, do not write 1 to the DMASTRT bit. Also, in control bits other than the DMASTOP bit, write the value at the time of transfer started. In the case of an abnormal termination, the DMA termination status bit (DMAST) in the PCIDCR is set when the cause of that abnormal termination (error detection or forced termination of DMA transfer) occurs. After the data transfer terminates, the DMA transfer start control bit (DMASTART) is cleared and the DMA transfer termination interrupt status bit (DMAIS) is set. If the DMA transfer interrupt mask bit (DMAIM) is set to 1, the DMA transfer termination interrupt is issued. In the event of an abnormal termination, the transferred data is not guaranteed. Figure 22.6 shows an example of DMA transfer flowchart. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 943 of 1128 Section 22 PCI Controller (PCIC) DMA transfer start SH7751 Group, SH7751R Group DMA transfer starts when 1 is set in the DMASTRT bit of the PCIDCR register. DMA transfer (⇔ FIFO) Transfer address update The PCIDPA and PCIDLA registers are updated (increment/fixed) by the LAHOLD bit of the PCIDCR register. Transfer count decrement The PCIDTC decrements at a rate equaling the number of transfer bytes (4 bytes). Is transfer error detected? Yes No DMASTOP = 1? No Yes Yes DMA transfer is forcibly stopped when 1 is set in the DMASTOP bit of the PCIDCR register. (Do not set 1 in the DMASTRT bit at the same time.) PCIDTC > 0? No DMAST = 0 DMAST = 1 Normal ending Abnormal ending After DMA transfer completion, the DMASTRT bit of the PCIDCR register is cleared to 0, and the DMAIS bit of the PCIDCR register is set to 1. Figure 22.6 Example of DMA Transfer Flowchart Page 944 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) • Termination by software reset When the RSTCTL bit of the PCICR is asserted, the PCIC is reset and DMA transfers are forcibly terminated. Note, however, that when transfers are terminated by a software reset, the PCIDCR is also reset and the DMA transfer control registers are all cleared. DMA Arbitration: If transfer requests are made simultaneously on multiple DMA channels in the PCI, transfer arbitration is required. There are two modes that can be selected to determine order of priority of the DMA transfers on the four channels: fixed order of priority and pseudo roundrobin. The mode is selected using the DMABT bit of the PCI's DMA transfer arbitration register (PCIDMABT). For arbitration to be performed in such a way as to maintain high-speed data transfer, there are 4 FIFOs (32-byte × 2 buffer structure) for the four DMA transfer channels. The FIFOs have a 2buffer structure, enabling one buffer to be accessed from the PCI bus while the other is being accessed from the local bus. Depending on the direction of the transfer, the input port of the FIFO for DMA transfers. Transfers are possible in both directions between the local bus and PCI bus by selecting the transfer direction. The arbitration circuit monitors the data transfer requests (data write requests to the FIFO when the FIFO is empty and read requests from the FIFO when it is full) 4 DMA transfer channels to control the data transfers. For each transfer request, a transfer of up to 32 bytes of data is performed. If a DMA transfer request occurs at the same time as a PIO transfer request, the PIO transfer takes precedence over transfers on the four DMA channels, regardless of the specified mode of DMA transfer priority order. Fixed Priority Mode (DMABT = 0): In fixed priority mode, the order of priority of data transfer requests is fixed and cannot be changed. The order is as follows: Channel 0 DMA transfer > channel 1 DMA transfer > channel 2 DMA transfer > channel 3 DMA transfer DMA transfer on channel 0. Take the highest priority and channel 3 DMA transfers take the lowest priority. When data transfer requests occur simultaneously, the data transfer with the highest priority takes precedence. Let's look at data transfers from the local bus to the PCI bus in fixed priority mode. The arbitration circuit monitors the transfer requests from the respective data transfer control circuits and writes data read from the local bus to the data transfer FIFO that not only is empty but also has the highest priority. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 945 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group On the other hand, it checks if transfer data exists in the respective FIFOs and reads that data from the data transfer FIFO in which there is data and which has the highest priority, and outputs that data to the PCI bus. For example, if channel 1 FIFO is empty, the arbitration circuit writes the data from the local bus into the channel 1 FIFO. Next, if data of 32 bytes or more is in the channel 1 FIFO, it outputs that data to the PCI bus. If data has been written to both buffers of the channel 1 FIFO, the channel 1 FIFO is busy while data is output from one of those buffers to the PCI bus. While it is busy, data is written from the local bus to the channel 2 FIFO, which has the next highest order of priority. When all data has been output from the channel 1 FIFO to the PCI bus, data is output from the channel 2 FIFO, which still contains data, to the PCI bus. Thus, in fixed priority mode, execution alternates between the two data transfers with the highest priority. That is, if DMA transfers are performed simultaneously on 4 channels, the data transfers start with alternation between channels 1 and 2 and then move to alternating between 2 and 3 when all the data in channel 1 has been transferred. Likewise, execution moves to alternation between channels 3 and 4 on completion of channel 2. This pattern is the same when data is transferred from the PCI bus to the local bus. Pseudo round-robin mode (DMABT = 1): In pseudo round-robin mode, as each time data is transferred, the order of priority is changed so that the priority level of the completed data transfer becomes the lowest. Regarding pseudo round-robin mode operations, refer to section 22.3.5, Host Functions. 22.3.10 Transfer Contention within PCIC No contention occurs in the PCIC in the case of PIO transfer requests from the CPU and memory reads/memory writes due to target transfers. This is because PIO transfers use an internal bus for peripheral modules, and this operates independently of the local bus that has memory accessed by external PCI devices. Contention can occur in the PCIC in the case of PIO transfer requests from the CPU and IO reads/IO writes due to target transfers (PCIC local register access). In this case, however, arbitration is performed in the PCIC such that priority is given to register access by the external PCI device that has the PCI bus rights. Page 946 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.3.11 PCI Bus Basic Interface The PCI interface of the MCU supports a subset of version 2.1 of the PCI specifications and enables connection to a device with a PCI bus interface. While the PCIC is set in host mode, or while set in non-host mode, operation differs according to whether or not bus parking is performed, and whether or not the PCI bus arbiter function is enabled or not. In host mode, the AD, PAR, C/BE signal lines are driven by the PCIC when transfers are not being performed on the PCI bus (bus parking). When the PCIC subsequently starts transfers as master, these signal lines continue to be driven until the end of the address phase. However, in non-host mode, the master performing parking is determined according to the GNT output by the external arbiter. When the master performing parking is not the same master as that starting the subsequent transfer, a high impedance state of at least one clock is generated prior to the address phase. In host mode, the arbiters in the PCICs and the REQ and GNT between PCICs are connected internally. Here, pins PCIREQ1/GNTIN, PCIREQ2/MD9, PCIREQ3/MD10, and PCIREQ4 function as the REQ inputs from the external masters 1 to 4. Similarly, PCIGNT1/REQOUT, PCIGNT2, PCIGNT3, and PCIGNT4 function as the GNT outputs to external masters 1 to 4. Including the PCIC, arbitration of up to five masters is possible. In non-host mode, pins PCIREQ1/GNTIN functions as the GNT input of the PCIC, while PCIGNT1/REQOUT functions as the REQ output of the PCIC. Master Read/Write Cycle Timing: Figures 22.7 is an example of a single-write cycle in host mode. Figure 22.8 is an example of a single read cycle in host mode. Figure 22.9 is an example of a burst write cycle in non-host mode. And Figure 22.10 is an example of a burst read cycle in nonhost mode. Note that the response speed of DEVSEL and TRDY differs according to the connected target device. In PIO transfers, always use single read/write cycles. The issuing of configuration transfers is only possible in host mode. LOCK transfers are possible only using PIO transfers. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 947 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group PCICLK AD31–AD0 Addr D0 AP PAR C/BE3–C/BE0 Com DP0 BE0 PCIFRAME IRDY DEVSEL TRDY PCILOCK LOCKed IDSEL PCIGNT1/REQOUT, PCIGNT2–PCIGNT4 PCIREQ1/GNTIN, PCIREQ2–PCIREQ4 Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 22.7 Master Write Cycle in Host Mode (Single) Page 948 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) PCICLK Addr AD31–AD0 D0 AP PAR C/BE3–C/BE0 Com DPn BE0 PCIFRAME IRDY DEVSEL TRDY PCILOCK LOCKed IDSEL PCIGNT1/REQOUT, PCIGNT2–PCIGNT4 PCIREQ1/GNTIN, PCIREQ2–PCIREQ4 Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 22.8 Master Read Cycle in Host Mode (Single) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 949 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group PCICLK AD31–AD0 Addr PAR C/BE3–C/BE0 Com D0 D1 Dn AP DP0 DPn-1 BE0 BE1 BEn APn PCIFRAME IRDY DEVSEL TRDY PCILOCK IDSEL PCIGNT1/REQOUT PCIREQ1/GNTIN Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 22.9 Master Memory Write Cycle in Non-Host Mode (Burst) Page 950 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) PCICLK D0 Addr AD31–AD0 AP PAR C/BE3–C/BE0 Com BE0 D1 Dn DP0 DPn-1 BE1 DPn BEn PCIFRAME IRDY DEVSEL TRDY PCILOCK IDSEL PCIGNT1/REQOUT PCIREQ1/GNTIN Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 22.10 Master Memory Read Cycle in Non-Host Mode (Burst) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 951 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Target Read/Write Cycle Timing: The PCIC responds to target memory read accesses from an external master by retries until 8 longword data are prepared in the PCIC's internal FIFO. That is, it always responds to the first target read with a retry. Also, if a target memory write access is made, the PCIC responds to all subsequent target memory accesses with a retry until the write data is completely written to local memory. Thus, the content of the data is guaranteed when data written to the target is immediately subject to a target read operation. The following restrictions apply to the SH7751. With the SH7751R, in the following case the values of data are discarded for a target read that is executed immediately after a target write because the data read in an earlier read operation that was carried out by a different PCI device are discarded. [Restrictions] In a system in which access is made to the same address*1 in local memory by two or more PCI devices, the data cannot be guaranteed when a target read is performed immediately after a target write. The possibility of an error occurs when the target read immediately after the target write gets bus privileges at the point the data is ready for a target read by a different PCI device prior to the target write. In this case, the data prior to the target write is read. If such transfers are likely to occur, implement either (a) or (b) below. (a) If using the data that has been read, perform two read operations and use only the data from the second read operation. (b) If not using the data that has been read (if you are performing the read operation in order to determine the timing for actually writing data to the destination), be sure that the read address*2 immediately after writing is different from the write address. Notes: 1. Address matching AD[31:2] in the address phase. 2. The address that does not correspond to the address AD[31:2] on a longword boundary. Only single transfers are supported in the case of target accesses of the configuration space and I/O space. If there is a burst access request, the external master is disconnected on completion of the first transfer. Note that the DEVSEL response speed is fixed at 2 clocks (Medium) in the case of target access of the PCIC. Page 952 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Figure 22.11 shows an example target single read cycle in non-host mode. Figure 22.12 shows an example target single write cycle in non-host mode. Figure 22.13 is an example of a target burst read cycle in host mode. And Figure 22.14 is an example target burst write cycle in host mode. PCICLK Addr AD31–AD0 D0 AP PAR Com C/BE3–C/BE0 DP0 BE0 PCIFRAME IRDY DEVSEL TRDY PCISTOP Disconnect PCILOCK LOCKed IDSEL At Config Access PCIGNT1/REQOUT PCIREQ1/GNTIN Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 22.11 Target Read Cycle in Non-Host Mode (Single) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 953 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group PCICLK Addr AD31−AD0 D0 DP0 AP PAR Com C/BE3−C/BE0 BE0 PCIFRAME IRDY DEVSEL TRDY PCISTOP Disconnect PCILOCK LOCKed IDSEL At Config Access PCIGNT1/REQOUT PCIREQ1/GNTIN Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 22.12 Target Write Cycle in Non-Host Mode (Single) Page 954 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) PCICLK Addr AD31–AD0 D0 AP PAR Com C/BE3–C/BE0 BE0 D1 Dn DP0 DPn-1 BE1 BEn DPn PCIFRAME IRDY DEVSEL TRDY PCISTOP Disconnect PCILOCK LOCKed IDSEL PCIGNTn PCIREQn Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 22.13 Target Memory Read Cycle in Host Mode (Burst) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 955 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group PCICLK Addr AD31–AD0 AP PAR Com C/BE3–C/BE0 D1 D0 DP0 BE0 Dn DPn-1 BE1 DPn BEn PCIFRAME IRDY DEVSEL TRDY PCISTOP Disconnect PCILOCK LOCKed IDSEL PCIGNTn PCIREQn Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 22.14 Target Memory Write Cycle in Host Mode (Burst) Page 956 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Address/Data Stepping Timing: By writing 1 to the WCC bit (bit 7 of the PCICONF1), a wait (stepping) of one clock can be inserted when the PCIC is driving the AD bus. As a result, the PCIC drives the AD bus over 2 clocks. This function can be used when there is a heavy load on the PCI bus and the AD bus does not achieve the stipulated logic level in one clock. When the PCIC operates as the host, it is recommended to use this function for the issuance of configuration transfers. Figure 22.15 is an example of burst memory write cycle with stepping. Figure 22.16 is an example of target burst read cycle with stepping. PCICLK AD31–AD0 Addr D0 AP PAR C/BE3–C/BE0 Com Dn DP0 BE0 DPn-1 DPn BEn PCIFRAME IRDY DEVSEL TRDY Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 22.15 Master Memory Write Cycle in Host Mode (Burst, With Stepping) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 957 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group PCICLK AD31–AD0 Addr D0 AP PAR C/BE3–C/BE0 Com Dn DP0 BE0 DPn-1 DPn BEn PCIFRAME IRDY DEVSEL TRDY Legend: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 22.16 Target Memory Read Cycle in Host Mode (Burst, With Stepping) Page 958 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.4 Endians 22.4.1 Internal Bus (Peripheral Bus) Interface for Peripheral Modules The internal bus (peripheral bus) for the peripheral modules that write data from CPU to the PCIC registers operates in big endians. On the other hand, PCI bus operates in little endian. Therefore, big/little endian conversion is required in PIO transfer, as shown in figure 22.17. The PCIC supports two endian conversion modes, the BYTESWAP bit of the PCI control register (PCICR) switching between these modes. PCI bus Peripheral bus 32 bits Big → little 32 bits 32 bits 32 bits Little → big Big endian Little endian Figure 22.17 Endian Conversion Modes for Peripheral Bus 1. Byte data boundary mode: Big/little endian conversion is performed on the assumption that all data is on byte boundaries. (BYTESWAP = 1) 2. Word/longword (W/LW) boundary mode: Big/little endian conversion is performed according to the size of data accessed. (BYTESWAP = 0) Table 22.10 shows the access sizes supported by the conversion modes at the destination of peripheral bus access. The local registers in the PCIC are always accessed in the word/longword boundary mode regardless of the transfer mode. Figure 22.18 shows the data alignment between peripheral bus and PCI bus in each boundary mode. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 959 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Table 22.10 Access Size Transfer Mode Access Destination Access Size W/LW Boundary Byte Data Mode Boundary Mode PCI external device Memory space B, W, LW Yes Yes I/O space B, W, LW Yes Yes Configuration register LW Yes Yes LW Yes W/LW boundary mode PCIC register Legend: B: Byte W: Word LW: Longword Memory/I/O space access (Peripheral bus ↔ PCI bus) Peripheral bus Size Address Data 31 4n+0 4n+1 PCI bus 0 Data (W/LW boundary mode) Data (Byte data boundary mode) 31 31 0 B0 0 B0 B1 Address BE[3:0] (memory I/O) B0 B1 B1 4n+0/4n+0 1110 4n+0/4n+1 1101 4n+0/4n+2 1011 4n+0/4n+3 0111 4n+0/4n+0 1100 Byte 4n+2 B2 4n+3 4n+0 B2 B3 B2 B3 B0 B1 B3 B0 B1 B1 B0 Word Long Word 4n+2 B2 B3 4n+0 B0 B1 B2 B3 B2 B3 B3 B2 4n+0/4n+2 0011 B0 B1 B2 B3 B3 B2 B1 B0 4n+0/4n+0 0000 Figure 22.18 Peripheral Bus ↔ PCI Bus Data Alignment Page 960 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.4.2 Section 22 PCI Controller (PCIC) Endian Control for Local Bus Big and little endians are supported on the local bus, determined at power-on reset by the external endian specification pin (MD5). Therefore, when transferring data between the local bus and the PCI bus, when the local bus is set for big endian, big/little endian conversion is therefore required. Figure 22.19 shows the block diagram of the local bus endian control. An endian conversion circuit is provided between the local bus and the FIFO. For details of the endian control, refer to section 22.4.3, Endian Control in DMA Transfers, and section 22.4.4, Endian Control in Target Transfers (Memory Read/Memory Write). Local bus FIFO 32 bits LW DMA Big/little → little LW PCI bus 32 bits Target RD FIFO 32 bits Little → big/little LW B, W, LW DMA 32 bits Targer WT Big/little endian Little endian Figure 22.19 Endian Control for Local Bus 22.4.3 Endian Control in DMA Transfers Although only the longword access size is supported in DMA transfers (see table 22.11), the endian conversion mode can be selected from the following four types depending on whether the longword data consists of four byte data units or two word data units. The conversion mode can be switched by the setting of bits 10 and 9 (ALNMD) of the DMA control registers (PCIDCR0 to 3) for PCI. 1. Byte data boundary mode: Big/little endian conversion is performed on the assumption that all data is on a byte boundary. (ALNMD = b'00) 2. Word/longword (W/LW) boundary mode 1: Longword data is transferred as byte data x 4. (ALNMD = b'01) 3. Word/longword (W/LW) boundary mode 2: Longword data is transferred as word data x 2. (ALNMD = b'10) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 961 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 4. Word/longword (W/LW) boundary mode 3: Longword data is transferred as longword data x 1. (ALNMD = b'11) Only longword access size is supported in the case of DMA transfers. Figure 22.20 shows the data alignment in the respective boundary modes in DMA transfers. Table 22.11 DMA Transfer Access Size and Endian Conversion Mode Endian Conversion Mode Local Bus Endian Data Transfer Direction Access Size W/LW Boundary Mode (1 to 3) Byte Data Boundary Mode Big endian Local bus ↔ PCI bus LW Yes Yes Little endian Local bus ↔ PCI bus LW Conversion not required Conversion not required When local bus is big endian Local bus PCI bus Byte data boundary mode Size = LW 31 0 B0 B1 B2 B3 31 0 B3 B2 B1 B0 W/LW W/LW W/LW boundary mode 1 boundary mode 2 boundary mode 3 31 0 B3 B2 B1 B0 31 0 B2 B3 B0 B1 31 0 B0 B1 B2 B3 BE = 0000 When local bus is little endian Local bus Size = LW 31 PCI bus 0 B3 B2 B1 B0 31 0 BE = 0000 B3 B2 B1 B0 Figure 22.20 Data Alignment at DMA Transfer Page 962 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.4.4 Section 22 PCI Controller (PCIC) Endian Control in Target Transfers (Memory Read/Memory Write) In target transfers, for memory read and memory write that perform data transfer between the local bus and the PCI bus, big/little endian conversion is required in the same way as for DMA transfers when the local bus is set for big endians. Word/longword boundary modes are not supported in the case of target transfers. As shown in table 22.12, the byte data boundary mode is used, for all transfers. The access sizes supported in the case of target transfers are as follows: For target reads (local bus to PCI bus), longword only. For target writes (PCI bus to local bus), longword/word/byte. In target write operations, the byte, word and longword data in the PCIC are transferred to the local bus in one or two transfer operations depending on the type of the byte enable signal of the PCI bus. For example, when C/BE = B'1010, byte access to the local bus is generated twice. When C/BE = B'1000, byte access and word access are each generated once. Table 22.12 Target Transfer Access Size and Endian Conversion Mode Endian Conversion Mode Local Bus Endian Data Transfer Direction Access Size W/LW Boundary Mode (1 to 3) Byte Data Boundary Mode Big endian Target read LW No Yes Target write B, W, LW No Yes Target read LW Target write B, W, LW Conversion not required Conversion not required Little endian R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 963 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Target memory read transfers (local bus → PCI bus) when local bus is big endian Local bus Size 31 LW BE PCI bus 0 31 B0 B1 B2 B3 0 B3 B2 B1 B0 H'0 to H'F Target memory write transfers (local bus ← PCI bus) when local bus is big endian Size Local bus 31 B B1 B2 B1 B0 B2 B3 B0 B+B B+B 0111 B3 B0 B1 W 1011 B2 B3 B1 B0 B2 B2 + B3 B3 + B3 B3 1100 0011 B3 B2 + 1110 1101 B1 B B+B 0 B0 B W 31 B0 B BE PCI bus 0 B0 1010 0101 B1 B0 0110 B+B B1 + B2 B2 B1 1001 W+B B0 B1 + B2 B2 B1 B0 1000 W+B B0 B1 + B3 B1 B0 0100 B+W B0 + B2 B3 B3 B2 B0 0010 + B2 B3 B3 B2 B1 B+W B1 — — LW B0 B1 B2 B3 B3 0001 1111 B3 B2 B1 B0 0000 Figure 22.21 (1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus) Page 964 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Target memory read transfers (local bus → PCI bus) when local bus is little endian Local bus Size 31 LW BE PCI bus 0 31 B3 B2 B1 B0 0 B3 B2 B1 B0 H'0 to H'F Target memory write transfers (local bus ← PCI bus) when local bus is little endian Size Local bus 31 B B0 0111 B3 B1 B0 B1 B0 B3 B2 B0 + B1 B+B B2 B2 + B3 B3 B0 + B3 B3 1100 0011 B3 B2 B+B B+B 1011 B2 B3 1110 1101 B1 B2 W W 0 B1 B B 31 B0 B BE PCI bus 0 B0 1010 0101 B1 B0 0110 B+B B1 + B2 B2 B1 1001 W+B B1 B0 + B2 B2 B1 B0 1000 W+B B1 B0 + B3 B1 B0 0100 B0 0010 B+W B0 + B3 B2 B+W B1 — — LW B3 B2 B1 B0 + B3 B2 B3 B3 B2 B3 B2 B1 0001 1111 B3 B2 B1 B0 0000 Figure 22.21 (2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 965 of 1128 Section 22 PCI Controller (PCIC) 22.4.5 SH7751 Group, SH7751R Group Endian Control in Target Transfers (I/O Read/I/O Write) The access size is fixed at longword when accessing the PCIC local register using I/O read or I/O write commands. Addresses are specified using 4-byte boundaries, and BE[3:0] is specified as B'0000. The data alignment in target transfers (I/O read and I/O write) is shown in figure 22.22. Target I/O read transfer data alignment (local register Size Address 31 LW 4n B3 B2 B1 B0 Address LW 4n 31 0 B3 B2 B1 B0 BE PCI bus 0 B3 B2 B1 B0 H'0000 local register) Local register 31 BE PCI bus 0 Target I/O write transfer data alignment (PCI bus Size PCI bus) Local register 31 0 B3 B2 B1 B0 H'0000 Figure 22.22 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian) 22.4.6 Endian Control in Target Transfers (Configuration Read/Configuration Write) The data alignment when accessing the PCIC configuration register using the target configuration read and configuration write commands is shown in figure 22.23. In the SH7751 the access size is fixed at longword. The BE[3:0] value is ignored. In the SH7751R all BE combinations are valid. Page 966 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Target configuration read transfer data alignment (configuration register Configuration register 31 0 B3 B2 B1 B0 31 0 H'0 to H'F B3 B2 B1 B0 SH7751 target configuration write transfer data alignment (PCI bus Configuration register 31 0 B3 B2 B1 B0 31 0 B3 B2 B1 B0 31 0 B3 B2 B1 31 B0 31 0 B3 B2 0 B1 B0 31 0 B3 B1 B0 31 0 B3 31 BE 0 B3 B2 B1 B0 31 B1 31 31 0001 0 B3 B2 B0 31 B0 31 0 B3 0011 31 0 B3 B1 B0 31 0 B3 B1 B0 31 0101 B1 0 B3 B0 31 0111 0 31 B2 B1 31 B2 1001 0 0 B2 B0 31 B2 0 1011 31 B1 B0 31 31 0 31 B1 31 0 1101 0 B0 31 1100 0 B1 B0 31 0 B1 B0 0 1010 0 B2 31 1000 0 B2 B1 B0 31 0 B2 B1 B0 31 0110 0 31 0 0100 0 31 B2 B1 B0 31 0100 0 B3 31 0010 0 B3 0 B3 0000 0 B3 B2 31 B3 configuration register) PCI bus B3 B2 B1 0 B3 B2 H'0 to H'F B3 B2 B1 B0 Configuration register 0 configuration register) BE PCI bus SH7751R target configuration transfer data alignment (PCI bus 31 PCI bus) BE PCI bus 1110 0 1111 Figure 22.23 Data Alignment at Target Configuration Transfer (Both Big Endian and Little Endian) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 967 of 1128 Section 22 PCI Controller (PCIC) 22.5 SH7751 Group, SH7751R Group Resetting This section describes the resetting supported by the PCIC. Power-On Reset when Host: A reset (PCIRST) can be output to the PCI bus when the PCIC is host. The PCIRST pin is asserted when a power-on reset is generated at the RESET pin or when a software reset is generated by setting 1 in the PCIRST output control bit (RSTCTL) of the PCI control register (PCICR). Reset Input in Non-Host Mode: The PCIC has no dedicated reset input pin. A reset signal from the PCI bus can be connected to the RESET pin and a power-on reset applied to this LSI, but the following point must be noted: In the PCI standard, the reset (RST) signal must be asserted for a minimum of 1msec, check the time required for the power-on reset of this LSI (see section 23, Electrical Characteristics), and design the timing of power-on resets so that it satisfies the conditions of the reset period for both. Manual Reset: The PCIC does not support the input of manual reset signals via the MRESET pin. No initialization therefore occurs by manual resets. Software Reset: Software resets are generated by setting 1 in the PCIRST output control bit (RSTCTL) of the PCI control register (PCICR). The PCIRST pin is asserted at the same time as the PCIC is reset. While a software reset is asserted, the PCIC registers cannot be accessed. Assertion requires a minimum of 1ms. Software resets are canceled by setting a 0 to the RSTCTL bit. It is not possible to set 0 in the RSTCTL bit and set other bits of the PCICR at the same time. After setting 0 in the RSTCTL bit, set other bits of the PCICR. Note that not all PCIC registers are reset at a software reset. See section 22.2, PCIC Register Descriptions, for details of which registers are reset. Use software clears as required for any registers that are not cleared by the software reset. Note that, since software resets cannot be asserted while the PCI bus clock is stopped, software resets must be asserted when the PCI bus clock (PCICLK or CKIO) is being input. Note that data cannot be guaranteed if a software reset is used while a data transfer is in progress. Page 968 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.6 Interrupts 22.6.1 Interrupts from PCIC to CPU Section 22 PCI Controller (PCIC) There are 8 interrupts, as shown in the following, that can be generated by the PCIC for the CPU. The interrupt controller also controls the individual interrupt priority levels and interrupt masks, etc. See the section 19, Interrupt Controller (INTC), for details. Table 22.13 Interrupts Interrupt Source Function INTPRI00 PCISERR SERR error interrupt [3:0] PCIERR ERR error interrupt [7:4] PCIPWDWN Power-down request interrupt PCIPWON Power-on request interrupt PCIDMA0 DMA0 transfer end interrupt PCIDMA1 DMA1 transfer end interrupt PCIDMA2 DMA2 transfer end interrupt PCIDMA3 DMA3 transfer end interrupt Priority High High Low Low System Error (SERR) Interrupt (PCISERR): This interrupt shows detection of the SERR pin being asserted. This interrupt is generated only when the PCIC is operating as host. When the PCIC is operating as non-host, the SERR bit in the PCI control register (PCICR) is used to notify the host device of the system error (assertion of SERR pin). The SERR pin can be asserted when the SERR bit is asserted and when an address parity error is detected in a target transfer. When the SER bit of the PCI configuration register 1 (PCICONF1) is set to 0, the SERR pin is not asserted. Error Interrupt (PCIERR): Shows error detection by the PCIC. The error interrupt is asserted when either of the following errors is detected: • Interrupts detected by PCI interrupt register (PCIINT) • Interrupts detected by PCI arbiter interrupt register (PCIAINT) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 969 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group The interrupts that can be detected by these two registers can also be masked. The PCI interrupt mask register (PCIINTM) masks the PCIINT interrupts, and the PCI arbiter interrupt mask register (PCIAINTM) masks the PCIAINT interrupts. See section 22.2, PCIC Register Descriptions, for details. The following are also set in relation to error interrupts: of the PCI configuration register 1 (PCICONF1), the parity error output status (DPE) the system error output status (SSE), the master abort reception status (RMA), the target abort reception status (RTA), the target abort execution status (STA) and the data parity status (DPD). DMA Channel 0 Transfer Termination Interrupt (PCIDMA0): The DMA termination interrupt status (DMAIS) bit of the DMA control register 0 (PCIDCR0) is set. The interrupt mask is set by the DMA termination interrupt mask (DMAIM) bit of the same register. DMA Channel 1 Transfer Termination Interrupt (PCIDMA1): The DMA termination interrupt status (DMAIS) bit of the DMA control register 1 (PCIDCR1) is set. The interrupt mask is set by the DMA termination interrupt mask (DMAIM) bit of the same register. DMA Channel 2 Transfer Termination Interrupt (PCIDMA2): The DMA termination interrupt status (DMAIS) bit of the DMA control register 2 (PCIDCR2) is set. The interrupt mask is set by the DMA termination interrupt mask (DMAIM) bit of the same register. DMA Channel 3 Transfer Termination Interrupt (PCIDMA3): The DMA termination interrupt status (DMAIS) bit of the DMA control register 3 (PCIDCR3) is set. The interrupt mask is set by the DMA termination interrupt mask (DMAIM) bit of the same register. Power Management Interrupt (Transition Request to Normal Status) (PCIPWON): The power state D0 (PWRST_D0) bit of the PCI power management interrupt register (PCIPINT) is set. The power state D0 interrupt mask can be set using the power state D0 (PWRST_D0) bit of the PCI power management interrupt mask register (PCIPINTM). Power Management Interrupt (Transition Request to Power-Down Mode) (PCIPWDWN): The power state D3 (PWRST_D3) bit of the PCI power management interrupt register (PCIPINT) is set. The power state D3 interrupt mask can be set using the power state D3 (PWRST_D3) bit of the PCI power management interrupt mask register (PCIPINTM). 22.6.2 Interrupts from External PCI Devices To receive interrupt signals from external PCI devices, etc., while the PCIC is operating as the host device, use the IRL [3:0] pin. The PCIC has no dedicated external interrupt input pin. Page 970 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.6.3 Section 22 PCI Controller (PCIC) INTA When the PCIC is operating as a non-host device, the INTA output can be used for interrupts to the host device. INTA can be asserted (Low output)/negated (High output) using the INTA output soft control bit (INTA) of the PCI control register (PCICR). INTA is open collector output. 22.7 Error Detection The PCIC can store error information generated on the PCI bus. The address information (ALOG [31:0]) at the time of the error is stored in the PCI error address data register (PCIALR). The PCI error command information register (PCICLR) stores the type of transfer (MSTPIO, MSTDMA0, MSTDMA1, MSTDMA2, MSTDMA3, TGT) at the time of the error, and the PCI command (CMDLOG [3:0]). When the PCIC is operating as host, the PCI error bus master information register (PCIBMLR) stores the bus master information (REQ4ID, REQ3ID, REQ2ID, REQ1ID, REQ0ID) at the time of the error. The error information storage circuit can only store information for one error. Therefore, when errors occur consecutively, no information is stored for the second or subsequent errors. Error information is cleared by resets. 22.8 PCIC Clock Three clocks are used with the PCIC. The peripheral module clock (Pck) is used for PCIC register access and PIO transfers. The bus clock (Bck) is used for local bus control. The PCI bus clock is used for PCI bus operation. The peripheral module clock and PCI bus clock do not need to be in sync, and there is no particular limit on the frequency ratio. However, in PIO transfers and when registers are being accessed, etc., circuits operating with the peripheral module clock and circuits operating with the PCI bus clock and circuits that synchronize both clocks are used, so the transfer speed depends on the frequency of the peripheral module clock as well. The bus clock (Bck) and PCI bus clock do not need to be in sync. However, the PCI bus clock should be set to the same frequency as the bus clock (Bck) or lower. The maximum PCI bus clock is 66 MHz. Either of the following can be selected using MD9 as the PCI bus clock: the CKIO feedback input clock and the clock input from the external input pin (PCICLK). R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 971 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group External Input Pin (PCICLK) Operating Mode: In this mode the PCI bus clock is input from outside. This mode requires the provision of an external oscillation module for the PCI. CKIO Operating Mode: In this mode, the clock output from the CKIO pin is used as the PCI bus clock. The feedback input from the CKIO pin is used as the PCI bus clock. This mode can only be used when the PCIC is operating as the host bridge. It cannot be used in non-host mode. When using this mode, note the CKIO load capacitance and only use it within the prescribed load stated in the manual. Note, too, that the clock frequency of CKIO cannot be guaranteed until the PLL oscillation stabilizes after a power-on reset or the clock frequency is changed. Also, in standby mode, the clock stops. This mode should only be employed after checking that these points do not cause any problems from the viewpoint of the system configuration. In CKIO operating mode, the maximum Bck frequency is 66 MHz. When not using the PCICLK pin, fix the pin level high. 66 MHz Compatibility: The PCIC is not necessarily fully compatible with the 66 MHz bus standard of the PCI. For details, see section 23, Electrical Characteristics. In the electrical characteristics of the PCI bus-related pins, the permissible delay on the board is extremely short. For this reason, the on-board load capacitance and impedance matching should be considered before connecting to a 66MHz-compatible PCI device. Note, too, that only one PCI device can be connected. In the PCI standard, there are two methods for checking if a PCI device can operate at 66 MHz: checking the 66 MHz operating status in the configuration register 1, and monitoring the M66ENB pin in the PCI bus standard. The PCIC supports the 66 MHz operating status (66M) bit of the configuration register 1 (PCICONF1). The PCIC does not have a special pin for directly monitoring the M66ENB pin. Also, there is no control output pin for switching between 33 MHz and 66 MHz when an external oscillator is used. A special external circuit is required to effect these controls. 22.9 Power Management 22.9.1 Power Management Overview The PCIC supports the PCI power management (version 1.0 compatible) configuration registers. These are as follows: Page 972 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) • Support for the PCI power management control configuration register; • Support for the power-down/restore request interrupts from hosts on the PCI bus. There are three configuration registers for PCI power management control. PCI configuration register 13 shows the address offset (CAPPTR) of the configuration registers for power management. In the PCIC, this offset is fixed at CAPPTR = H'40. PCI configuration register 16 and PCI configuration register 17 are power management registers. They support two states: power state D0 (normal) and power state D3 (power down mode). The PCIC detects when the power state (PWRST) bit of the PCI configuration register 17 changes (when it is written to from an external PCI device), and issues a power management interrupt. To control the power management interrupts, there are a PCI power management interrupt register (PCIPINT) and PCI power management interrupt mask register (PCIPINTM). Of the power management interrupts, the power state D3 (PWRST_D3) interrupt detects a transition from the power state D0 to D3, while power state D0 (PWRST_D0) interrupt detects a transition from the power state D3 to D0. Interrupt masks can be set for each interrupt. No power state D0 interrupt is generated at a power-on reset. The following cautions should be noted when the PCIC is operating in non-host mode and a power down interrupt is received from the host: In PCI power management (version 1.0 compatible), the PCI bus clock stops within a minimum of 16 clocks after the host device has instructed a transition to power state D3. After detecting a power state D3 (power down) interrupt, do not, therefore, attempt to read or write to local registers that can be accessed from the CPU and PCI bus. Because these registers operate using the PCI bus clock, the read/write cycle for these registers will not be completed if the clock stops. 22.9.2 Stopping the Clock Power savings can be achieved by stopping the bus clock used by the PCIC and the PCI bus clock. The PCI clock control register (PCICLKR) is provided for controlling the PCIC clock. Regarding the control register for stopping the peripheral module clock (Pck) in the PCIC, refer to section 9, Power-Down Modes. The method of stopping the clock differs according to the operating mode of the PCI bus clock. See table 22.14. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 973 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Table 22.14 Method of Stopping Clock per Operating Mode PCIC Master Clock operating status Normal operation/ sleep LSI (Other than PCIC) PCICLK Operation CKIO Operation PCICLK Operation Bck Normal operation Normal operation Normal operation Normal operation Pck Normal operation Normal operation Normal operation Normal operation PCICLK Not used Normal operation Not used Normal operation Stopped Stopped Stopped Stopped Pck Normal operation Normal operation Normal operation Normal operation PCICLK Not used Normal operation Not used Normal operation Bck Stopped Stopped Stopped Stopped Pck Stopped Stopped Stopped Stopped PCICLK Not used Stopped Not used Stopped Deep sleep Bck Standby Transition/ Deep sleep Transition Sleep Recovery command Page 974 of 1128 Slave Bck stopped Bck and from LSI PCICLK stopped from LSI PCI command + interrupt (PCIC → LSI) + Bck restarted from LSI Recovery Not used 1 PME interrupt (connected to IRL) + Bck restarted from LSI PME interrupt (connected to IRL) + Bck and PCICLK restarted from LSI PCI command + interrupt (PCIC → LSI) + Bck restarted from LSI Recovery NMI, IRL, 2 and RESET on-chip peripheral interrupt NMI, IRL, RESET + Bck restarted from LSI NMI, IRL, RESET + Bck and PCICLK restarted from LSI NMI, IRL, RESET + Bck restarted from LSI + wait for PCI command (recovery) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) PCIC Master LSI (Other than PCIC) Transition/ Standby Recovery Slave PCICLK Operation CKIO Operation PCICLK Operation Transition Standby command Standby command PCICLK stopped from LSI + standby command PCI command + interrupt (PCIC → LSI) + standby command Recovery Not used 1 PME interrupt (connected to IRL) PME interrupt (connected to IRL) + PCICLK restarted from LSI Power-on reset Recovery NMI, IRL, 2 and RESET on-chip peripheral interrupt NMI, IRL, NMI, IRL, and RESET RESET + PCICLK restarted from LSI NMI, IRL, RESET + wait for PCI command (recovery) Notes: Recovery 1: Recovery from PCI bus Recovery 2: Recovery from other than PCI bus External Input Pin (PCICLK) Operating Mode: The PCI bus clock can be stopped by writing 1 to the PCICLKSTOP bit. The bus clock can be stopped by writing 1 to the BCLKSTOP bit. It requires a minimum of 2 clocks of the PCI bus clock for the clock to actually stop after writing to PCICLKR (setting the PCICLKSTOP bit to 1). It takes a similar time for the clock to restart. Bus Clock (CKIO) Operating Mode: Both the PCI bus clock and bus clock can be stopped by writing 1 to the BCLKSTOP bit. It requires a minimum of 2 clocks of the bus clock for the clock to actually stop after writing to PCICLKR (setting the BCLKSTOP bit to 1). It takes a similar time for the clock to restart. While the PCI bus clock is stopped, it is not possible to access the local registers that can be accessed both from the peripheral module internal bus and from the PCI bus. Neither writing nor reading can be performed correctly. Also, the following cautions must be observed when stopping the bus clock and PCI bus clock while the PCI is in use: R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 975 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group • When operating as host device The clock must be stopped only after stopping the operation of external PCI devices connected to the PCI bus. If you stop the clock prior to stopping the external devices, access from those external devices will cause a hang-up. Stop the clock only after checking that there is no problem in respect to the system configuration. One method of stopping the operation of external PCI devices is to use the PCI power management, as discussed above. Stop the clock after switching the external PCI devices to power state D3 (power-down mode). In this case, all external PCI devices must support PCI power management. • When operating in non-host mode When operating in non-host mode, the PCI bus clock must be in external input operating mode (PCICLK). In this case, the host device is responsible for stopping and restarting the PCI bus clock, so it is not necessary to stop the clock using PCICLKR of the PCIC. Make sure that the CPU receives the interrupt in accordance with the power management sequence. 22.9.3 Compatibility with Standby and Sleep To stop all the PCIC's internal clocks, the SLEEP command must be used to transit to standby mode. When operating in external input pin (PCICLK) operating mode, set the PCICLKSTOP bit to 1 to stop the PCI bus clock, transit to standby, then, after recovering from standby, clear the PCICLKSTOP bit to 0 to prevent hazards occuring in the PCI bus clock. When using the standby command in systems using the PCI bus, first check that the system does not hang up if the clock is stopped. Note that the PCIC clock does not stop after transiting to sleep mode. 22.10 Port Functions When the PCIC is operating in non-host mode, the arbitration pin of the PCI bus can be used as a port. When using the host functions (arbitration), the port functions cannot be used. The following six pins can be used: PCIREQ2, PCIREQ3, PCIREQ4, PCIGNT2, PCIGNT3, and PCIGNT4. The three pins PCIREQ2, PCIREQ3, and PCIREQ4 can be used as I/O ports. The three pins PCIGNT2, PCIGNT3, and PCIGNT4 can be used as output ports. Data is output in synchronous with the bus clock (CKIO). Input data is fetched at the rising edge of the bus clock. Port control is performed by the port control register (PCIPCTR) and port data register (PCIPDTR). PCIPCTR controls the existence of the port function, the switching ON/OFF of the pull-up resistance, and the switching between input and output. PCIPDTR performs the input/output of port data. Page 976 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 22.11 Section 22 PCI Controller (PCIC) Version Management The PCIC version management is written in the revision ID (8 bits) of the PCI configuration register 2 (PCICONF2). 22.12 Usage Notes 22.12.1 Notes on Arbiter Interrupt Usage (SH7751 Only) When the PCIC function of the SH7751 is employed as a host with an arbitration function, care must be exercised as follows with regard to the target bus timeout interrupt and master bus timeout interrupt in the PCI arbiter interrupt register (PCIAINT). Description: On the SH7751, notification of violations of the 16-clock rule or 8-clock rule for external PCI devices (target latency and master data latency clock cycle limitations under the PCI 2.1 specification) are provided by setting bit 12 (target bus timeout interrupt) or bit 11 (master bus timeout interrupt) in the PCI arbiter interrupt register (PCIAINT) of the PCIC. However, on the SH7751 these clock cycle limitations are set to one clock cycle fewer than the values defined in the PCI 2.1 specification. In other words, in the timings described in 1. and 2. below, even though the target latency or master data latency of the external PCI device does not violate the 16-clock rule or 8-clock rule according to the PCI 2.1 specification, the SH7751 judges that a 16-clock rule or 8-clock rule violation has occurred and sets to 1 bit 12 (target bus timeout interrupt) or bit 11 (master bus timeout interrupt) in the PCI arbiter interrupt register (PCIAINT). 1. Target latency: A target bus timeout interrupt occurs (see figures 22.24 and 22.25). During the first data transfer, the external PCI device functioning as the target asserts TRDY or STOP at the sixteenth clock cycle after the data transfer request from the master device (FRAME asserted). Alternately, during the second or a subsequent data transfer, it asserts TRDY or STOP at the eighth clock cycle after the immediately preceding data phase. 2. Master data latency: A master bus timeout interrupt occurs (see figures 22.26 and 22.27). The external PCI device functioning as the master acquires the bus and asserts FRAME, then asserts IRDY at the eighth clock cycle during the first data transfer. Alternately, during the second or a subsequent data transfer, it asserts IRDY at the eighth clock cycle after the immediately preceding data phase. Workarounds: When the PCIC function of the SH7751 is employed as a host with an arbitration function, and an external device is connected that employs the full number of clock cycles permitted under the 16-clock rule or 8-clock rule, use the PCI arbiter interrupt mask register (PCIAINTM) to mask the bus timeout interrupts in the PCI arbiter interrupt register (PCIAINT). R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 977 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 1. If the problem concerns target latency, clear to 0 bit 12 (target bus timeout interrupt mask) in the PCI arbiter interrupt mask register (PCIAINTM) to mask the target bus timeout interrupt. 2. If the problem concerns master data latency, clear to 0 bit 11 (master bus timeout interrupt mask) in the PCI arbiter interrupt mask register (PCIAINTM) to mask the master bus timeout interrupt. Note that if the above interrupts are masked, no interrupt will occur when the 16-clock rule or 8-clock rule of PCI 2.1 specification is violated, even if the violation is detected. 0 1 2 3 4 11 12 13 14 15 16 PCICLK AD[31:0] A C/BE[3:0] C FRAME IRDY DEVSEL TRDY STOP PCIAINT: Bit 12 asserted Figure 22.24 Target Bus Timeout Interrupt Generation Example 1 (Example in which the Target Device Asserts STOP at the Sixteenth Clock Cycle after FRAME Was Asserted) Page 978 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 0 1 2 3 4 5 6 7 8 PCICLK AD[31:0] A D D D D D D D D C/BE[3:0] C BE BE BE BE BE BE BE BE FRAME IRDY DEVSEL TRDY STOP (High) PCIAINT: Bit 12 asserted Figure 22.25 Target Bus Timeout Interrupt Generation Example 2 (Example in which the Target Device Takes 8 Clock Cycles to Prepare for the Third Data Transfer) 0 1 2 3 4 5 6 7 8 PCICLK AD[31:0] A D D D D D D D C/BE[3:0] C BE BE BE BE BE BE BE FRAME IRDY DEVSEL PCIAINT: Bit 11 asserted TRDY STOP (High) Figure 22.26 Master Bus Timeout Interrupt Generation Example 1 (Example in which the Master Device Prepares the Data and Asserts IRDY at the Eighth Clock Cycle after FRAME Was Asserted) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 979 of 1128 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 0 1 2 3 4 5 6 7 8 PCICLK AD[31:0] A D D D D D D D D C/BE[3:0] C BE BE BE BE BE BE BE BE FRAME IRDY DEVSEL PCIAINT: Bit 11 asserted TRDY STOP (High) Figure 22.27 Master Bus Timeout Interrupt Generation Example 2 (Example in which the Master Device Takes 8 Clock Cycles to Prepare for the Third Data Transfer following the Second Data Phase) 22.12.2 Notes on I/O Read and I/O Write Commands (SH7751 Only) See I/O-Read and I/O-Write Commands in 22.3.8. 22.12.3 Notes on Configuration-Read and Configuration-Write Commands (SH7751 Only) See Configuration-Read and Configuration-Write Commands in 22.3.8. 22.12.4 Notes on Target Read/Write Cycle Timing (SH7751 Only) See Target Read/Write Cycle Timing in 22.3.11. 22.12.5 Notes on Parity Error Detection during Master Access Data error may not be detected while TRDY is asserted when the PCIC makes read access as a master. Phenomenon If all the following conditions are satisfied, data parity error cannot be detected. In such a case, the operation is the same as when no error is detected since PERR is not asserted and no detection bit is provided. Page 980 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) • PCIC (Master) operating conditions 1. The PER bit in PCI configuration register 1 is set to 1 (to respond to detected parity error). 2. Master memory read cycle • External PCI device (target) operating conditions 1. Target initiated disconnect (with data): STOP asserted Influence on System When a target initiated disconnect (with data) occurs, a parity error is not detected in the data phase in which disconnection has occurred, and PERR is not asserted. If not all the above conditions are satisfied, a parity error can be properly determined. This phenomenon may be inconvenient during master read access (target data parity error). Preventive Measures There are no preventive measures against this inconvenience that can be taken using the PCIC. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 981 of 1128 Section 22 PCI Controller (PCIC) Page 982 of 1128 SH7751 Group, SH7751R Group R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 Absolute Maximum Ratings Item Symbol Value I/O, RTC, CPG power supply voltage VDDQ, VDD-RTC, VDD-CPG –0.3 to 4.2 VDD, VDD-PLL1/2 –0.3 to 2.5 Internal power supply voltage Unit V 1 –0.3 to 4.6* V –0.3 to 2.1*1 Input voltage Vin –0.3 to VDDQ +0.3 V Operating temperature Topr –20 to 75, –40 to 85* °C Storage temperature Tstg –55 to 125 °C 2 Notes: The LSI may be permanently damaged if the maximum ratings are exceeded. The LSI may be permanently damaged if any of the VSS pins are not connected to GND. For the powering-on and powering-off sequences, see Appendix G, Power-On and PowerOff Procedures. 1. HD6417751R only. 2. HD6417751RBA240HV only. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 983 of 1128 Section 23 Electrical Characteristics 23.2 SH7751 Group, SH7751R Group DC Characteristics Table 23.2 DC Characteristics (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV) Ta = –20 to +75°C*3 Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, deep-sleep mode, standby mode 1.4 1.5 1.6 — 255 660 Sleep mode — 140 180 Standby mode — — 400 — — 800 — 100 145 Sleep mode — 60 115 Standby mode — — 400 — — 800 — 15 25 — 3 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, deep-sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Normal operation Normal operation IDD IDDQ Current dissipation Standby mode IDD-RTC Input voltage RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA mA Ick = 240 MHz μA Ta = 25 °C *1 Ta > 50 °C *1 mA Bck = 120 MHz μA Ta = 25 °C *1 Ta > 50 °C *1 μA RTC off VDDQ × 0.9 — VDDQ +0.3 V PCICLK VDDQ × 0.6 — VDDQ + 0.3 Other PCI input pins VDDQ × 0.5 — VDDQ +0.3 Other input pins 2.0 VDDQ +0.3 Page 984 of 1128 VIH — RTC on *2 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Item Input voltage Section 23 Electrical Characteristics Symbol Min Typ Max VIL –0.3 — VDDQ × 0.1 V PCICLK –0.3 — VDDQ × 0.2 Other PCI input pins –0.3 — VDDQ × 0.3 Other input pins –0.3 — VDDQ × 0.2 RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA Unit Test Conditions Input leak current All input pins |Iin| — — 1 μA Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, |Isti| all output pins (off state) — — 1 μA Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA VOH Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Notes: Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDD is the sum of the VDD and VDD-PLL1/2 currents. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode (There is no need to input a clock from EXTAL2). 2. To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). 3. Ta = –40 to 85°C for the HD6417751RBA240HV. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 985 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.3 DC Characteristics (HD6417751RF240 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, deep-sleep mode, standby mode 1.4 1.5 1.6 — 255 660 Sleep mode — 140 180 Standby mode — — 400 — — 800 — 70 100 Sleep mode — 42 80 Standby mode — — 400 — — 800 — 15 25 — 3 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, deep-sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Normal operation Normal operation IDD IDDQ Current dissipation Standby mode IDD-RTC Input voltage RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA mA Ick = 240 MHz μA Ta = 25 °C*1 Ta > 50 °C*1 mA Bck = 84 MHz μA Ta = 25 °C*1 Ta > 50 °C*1 μA RTC off VDDQ × 0.9 — VDDQ +0.3 V PCICLK VDDQ × 0.6 — VDDQ +0.3 Other PCI input pins VDDQ × 0.5 — VDDQ +0.3 Other input pins 2.0 VDDQ +0.3 Page 986 of 1128 VIH — RTC on*2 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Item Input voltage Section 23 Electrical Characteristics Symbol Min Typ Max VIL –0.3 — VDDQ × 0.1 V PCICLK –0.3 — VDDQ × 0.2 Other PCI input pins –0.3 — VDDQ × 0.3 Other input pins –0.3 — VDDQ × 0.2 RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA Unit Test Conditions Input leak current All input pins |Iin| — — 1 μA Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, |Isti| all output pins (off state) — — 1 μA Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA VOH Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Notes: Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDD is the sum of the VDD and VDD-PLL1/2 currents. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode (There is no need to input a clock from EXTAL2). 2. To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 987 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.4 DC Characteristics (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*3) Ta = –20 to +75°C*4 Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, deep-sleep mode, standby mode 1.35 1.5 1.6 — 210 550 Sleep mode — 115 150 Standby mode — — 400 — — 800 — 85 120 Sleep mode — 50 95 Standby mode — — 400 — — 800 — 15 25 — 3 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, deep-sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Normal operation Normal operation IDD IDDQ Current dissipation Standby mode IDD-RTC Input voltage RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA mA Ick = 200 MHz μA Ta = 25 °C*1 Ta > 50 °C*1 mA Bck = 100 MHz μA Ta = 25 °C*1 Ta > 50 °C*1 μA RTC off VDDQ × 0.9 — VDDQ +0.3 V PCICLK VDDQ × 0.6 — VDDQ +0.3 Other PCI input pins VDDQ × 0.5 — VDDQ +0.3 Other input pins 2.0 VDDQ +0.3 Page 988 of 1128 VIH — RTC on*2 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Item Input voltage Section 23 Electrical Characteristics Symbol Min Typ Max VIL –0.3 — VDDQ × 0.1 V PCICLK –0.3 — VDDQ × 0.2 Other PCI input pins –0.3 — VDDQ × 0.3 Other input pins –0.3 — VDDQ × 0.2 RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA Unit Test Conditions Input leak current All input pins |Iin| — — 1 μA Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, |Isti| all output pins (off state) — — 1 μA Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA VOH Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Notes: Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDD is the sum of the VDD and VDD-PLL1/2 currents. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode (There is no need to input a clock from EXTAL2). 2. To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). 3. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. 4. Ta = –40 to 85°C for the HD6417751RBA240HV. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 989 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.5 DC Characteristics (HD6417751RF200 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, deep-sleep mode, standby mode 1.35 1.5 1.6 — 210 550 Sleep mode — 115 150 Standby mode — — 400 — — 800 — 70 100 Sleep mode — 42 80 Standby mode — — 400 — — 800 — 15 25 — 3 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, deep-sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Normal operation Normal operation IDD IDDQ Current dissipation Standby mode IDD-RTC Input voltage RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA mA Ick = 200 MHz μA Ta = 25 °C*1 Ta > 50 °C*1 mA Bck = 84 MHz μA Ta = 25 °C*1 Ta > 50 °C*1 μA RTC off VDDQ × 0.9 — VDDQ +0.3 V PCICLK VDDQ × 0.6 — VDDQ +0.3 Other PCI input pins VDDQ × 0.5 — VDDQ +0.3 Other input pins 2.0 VDDQ +0.3 Page 990 of 1128 VIH — RTC on*2 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Item Input voltage Section 23 Electrical Characteristics Symbol Min Typ Max VIL –0.3 — VDDQ × 0.1 V PCICLK –0.3 — VDDQ × 0.2 Other PCI input pins –0.3 — VDDQ × 0.3 Other input pins –0.3 — VDDQ × 0.2 RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA Unit Test Conditions Input leak current All input pins |Iin| — — 1 μA Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, |Isti| all output pins (off state) — — 1 μA Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA VOH Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Notes: Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDD is the sum of the VDD and VDD-PLL1/2 currents. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode (There is no need to input a clock from EXTAL2). 2. To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 991 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.6 DC Characteristics (HD6417751BP167 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, standby mode 1.6 1.8 2.0 — 420 750 Sleep mode — 100 130 Standby mode — — 400 — — 800 — 70 100 Sleep mode — 40 80 Standby mode — — 400 — — 800 — — 25 — — 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Normal operation Normal operation IDD IDDQ Current dissipation Standby mode IDD-RTC Input voltage RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA mA Ick = 167 MHz μA Ta = 25°C (RTC on)* Ta > 50°C (RTC on)* mA Ick = 167 MHz, Bck = 84 MHz μA Ta = 25°C (RTC on)* Ta > 50°C (RTC on)* μA RTC off VDDQ × 0.9 — VDDQ +0.3 V PCICLK VDDQ × 0.6 — VDDQ +0.3 Other PCI input pins VDDQ × 0.5 — VDDQ +0.3 Other input pins 2.0 VDDQ +0.3 Page 992 of 1128 VIH — RTC on R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Item Input voltage Section 23 Electrical Characteristics Symbol Min Typ Max VIL –0.3 — VDDQ × 0.1 V PCICLK –0.3 — VDDQ × 0.2 Other PCI input pins –0.3 — VDDQ × 0.3 Other input pins –0.3 — VDDQ × 0.2 RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA Unit Test Conditions Input leak current All input pins |Iin| — — 1 μA Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, |Isti| all output pins (off state) — — 1 μA Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA VOH Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Notes: Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDD is the sum of the VDD and VDD-PLL1/2 currents. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. * To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 993 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.7 DC Characteristics (HD6417751F167 (V)) Ta = –20 to +75°C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, standby mode 1.6 1.8 2.0 — 420 750 Sleep mode — 100 130 Standby mode — — 400 — — 800 — 70 100 Sleep mode — 40 80 Standby mode — — 400 — — 800 — — 25 — — 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Normal operation Normal operation IDD IDDQ Current dissipation Standby mode IDD-RTC Input voltage RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA mA Ick = 167 MHz μA Ta = 25°C (RTC on)* Ta > 50°C (RTC on)* mA Ick = 167 MHz, Bck = 84 MHz μA Ta = 25°C (RTC on)* Ta > 50°C (RTC on)* μA RTC off VDDQ × 0.9 — VDDQ +0.3 V PCICLK VDDQ × 0.6 — VDDQ +0.3 Other PCI input pins VDDQ × 0.5 — VDDQ +0.3 Other input pins 2.0 VDDQ +0.3 Page 994 of 1128 VIH — RTC on R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Item Input voltage Section 23 Electrical Characteristics Symbol Min Typ Max VIL –0.3 — VDDQ × 0.1 V PCICLK –0.3 — VDDQ × 0.2 Other PCI input pins –0.3 — VDDQ × 0.3 Other input pins –0.3 — VDDQ × 0.2 RESET, NMI, TRST, ASEBRK/ BRKACK, MRESET, SLEEP, CA Unit Test Conditions Input leak current All input pins |Iin| — — 1 μA Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, |Isti| all output pins (off state) — — 1 μA Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA VOH Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 kΩ Pin capacitance All pins CL — — 10 pF Notes: Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDD is the sum of the VDD and VDD-PLL1/2 currents. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. * To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 995 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.8 Permissible Output Currents Item Symbol Min Typ Max Unit Permissible output low current (per pin; other than PCI pins) IOL — — 2 mA Permissible output low current (per pin; PCI pins) IOL — — 4 Permissible output low current (total) ΣIOL — — 120 Permissible output high current (per pin; other than PCI pins) –IOH — — 2 Permissible output high current (per pin; PCI pins) –IOH — — 4 Permissible output high current (total) Σ(–IOH) — — 40 mA Note: To protect chip reliability, do not exceed the output current values in table 23.8. 23.3 AC Characteristics In principle, this LSI's input should be synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 23.9 Clock Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV) Item Operating frequency Symbol Min Typ Max Unit f 1 — 240 MHz External bus 1 — 120 Peripheral modules 1 — 60 CPU, FPU, cache, TLB Notes Table 23.10 Clock Timing (HD6417751RF240 (V)) Item Operating frequency Symbol Min Typ Max Unit f 1 — 240 MHz External bus 1 — 84 Peripheral modules 1 — 60 CPU, FPU, cache, TLB Page 996 of 1128 Notes R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Table 23.11 Clock Timing (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*) Item Operating frequency Note: * Symbol Min Typ Max Unit f 1 — 200 MHz External bus 1 — 100 Peripheral modules 1 — 50 CPU, FPU, cache, TLB Notes This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. Table 23.12 Clock Timing (HD6417751RF200 (V)) Item Operating frequency Symbol Min Typ Max Unit f 1 — 200 MHz External bus 1 — 84 Peripheral modules 1 — 50 CPU, FPU, cache, TLB Notes Table 23.13 Clock Timing (HD6417751BP167 (V), HD6417751F167 (V)) Item Operating frequency Symbol Min Typ Max Unit f 1 — 167 MHz External bus 1 — 84 Peripheral modules 1 — 42 CPU, FPU, cache, TLB R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Notes Page 997 of 1128 Section 23 Electrical Characteristics 23.3.1 SH7751 Group, SH7751R Group Clock and Control Signal Timing Table 23.14 Clock and Control Signal Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75°C*2, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation Symbol Min Max Unit fEX 16 34 MHz 14 20 PLL1 12-times/PLL2 operation PLL1/PLL2 not operating Figure 1 34 EXTAL clock input cycle time tEXcyc 30 1000 ns 23.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock input rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 CKIO clock output fOP 25 120 MHz 1 34 MHz PLL1/PLL2 operating PLL1/PLL2 not operating CKIO clock output cycle time tcyc 8.3 1000 ns 23.2(1) CKIO clock output low-level pulse width tCKOL1 1 — ns 23.2(1) CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2(1) CKIO clock output rise time tCKOr — 3 ns 23.2(1) CKIO clock output fall time tCKOf — 3 ns 23.2(1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2(2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2(2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 RESET assert time tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 — μs 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 3 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 3 — ms 23.7 23.8 Standby return oscillation settling time 3 tOSC4 3 — ms 1 tOSC2 2 — ms 1 tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 23.10 TRST reset hold time tTRSTRH 0 — ns 23.3, 23.5 Standby return oscillation settling time 1* Standby return oscillation settling time 2* 1 Page 998 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. 1. When the oscillation settling time of the crystal resonator is 1 ms or less. 2. Ta = –40 to 85°C for the HD6417751RBA240HV. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 999 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.15 Clock and Control Signal Timing (HD6417751RF240 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75°C, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation Symbol Min Max Unit fEX MHz 16 34 PLL1 12-times/PLL2 operation 16 20.0 PLL1/PLL2 not operating 1 34 Figure EXTAL clock input cycle time tEXcyc 30 1000 ns EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock input rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 CKIO clock output fOP 25 84 MHz 1 34 MHz 11.9 1000 ns 23.2 (1) 23.2 (1) PLL1/PLL2 operating PLL1/PLL2 not operating CKIO clock output cycle time tcyc CKIO clock output low-level pulse width tCKOL1 1 — ns CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2 (1) CKIO clock output rise time tCKOr — 3 ns 23.2 (1) CKIO clock output fall time tCKOf — 3 ns 23.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2 (2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 RESET assert time tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 — μs 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 3 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 3 — ms 23.7 Standby return oscillation settling time 3 tOSC4 3 — ms 23.8 Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 23.10 TRST reset hold time tTRSTRH 0 — ns 23.3, 23.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. Page 1000 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. * When the oscillation settling time of the crystal resonator is 1 ms or less. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1001 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.16 Clock and Control Signal Timing (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*2) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75°C*3, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation Symbol Min Max Unit fEX 16 34 MHz 14 17 PLL1 12-times/PLL2 operation PLL1/PLL2 not operating Figure 1 34 EXTAL clock input cycle time tEXcyc 30 1000 ns 23.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock input rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 CKIO clock output fOP 25 100 MHz 1 34 MHz PLL1/PLL2 operating PLL1/PLL2 not operating CKIO clock output cycle time tcyc 10 1000 ns 23.2 (1) CKIO clock output low-level pulse width tCKOL1 1 — ns 23.2 (1) CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2 (1) CKIO clock output rise time tCKOr — 3 ns 23.2 (1) CKIO clock output fall time tCKOf — 3 ns 23.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2 (2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 RESET assert time tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 — μs 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 5 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 5 — ms 23.7 23.8 Standby return oscillation settling time 3 tOSC4 5 — ms 1 tOSC2 2 — ms 1 tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 23.10 TRST reset hold time tTRSTRH 0 — ns 23.3, 23.5 Standby return oscillation settling time 1* Standby return oscillation settling time 2* 1 Page 1002 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. 1. When the oscillation settling time of the crystal resonator is 1 ms or less. 2. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. 3. Ta = –40 to 85°C for the HD6417751RBA240HV. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1003 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.17 Clock and Control Signal Timing (HD6417751RF200 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75°C, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation Symbol Min Max Unit fEX MHz 16 34 PLL1 12-times/PLL2 operation 14 17 PLL1/PLL2 not operating 1 34 Figure EXTAL clock input cycle time tEXcyc 30 1000 ns EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock input rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 CKIO clock output fOP 25 84 MHz 1 34 MHz 11.9 1000 ns 23.2 (1) 23.2 (1) PLL1/PLL2 operating PLL1/PLL2 not operating CKIO clock output cycle time tcyc CKIO clock output low-level pulse width tCKOL1 1 — ns CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2 (1) CKIO clock output rise time tCKOr — 3 ns 23.2 (1) CKIO clock output fall time tCKOf — 3 ns 23.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2 (2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 RESET assert time tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 — μs 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 5 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 5 — ms 23.7 Standby return oscillation settling time 3 tOSC4 5 — ms 23.8 Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 23.10 TRST reset hold time tTRSTRH 0 — ns 23.3, 23.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. Page 1004 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. * When the oscillation settling time of the crystal resonator is 1 ms or less. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1005 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.18 Clock and Control Signal Timing (HD6417751BP167 (V), HD6417751F167 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to 75°C, CL = 30 pF Item EXTAL clock input frequency PLL1/PLL2 operating Symbol Min Max Unit fEX 30 56 MHz 1/2 divider not operating fEX 15 28 2 56 1/2 divider operating fEX PLL1/PLL2 not 1/2 divider operating operating 1/2 divider not operating fEX Figure 1 28 EXTAL clock input cycle time tEXcyc 17.8 1000 ns 23.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock input rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 CKIO clock output PLL2 operating fOP 30 84 MHz PLL2 not operating fOP 1 84 MHz CKIO clock output cycle time tcyc 11.9 1000 ns 23.2 (1) CKIO clock output low-level pulse width tCKOL1 1 — ns 23.2 (1) CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2 (1) CKIO clock output rise time tCKOr — 3 ns 23.2 (1) CKIO clock output fall time tCKOf — 3 ns 23.2 (1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2 (2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2 (2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 RESET assert time tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 — μs 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 10 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 5 — ms 23.7 Standby return oscillation settling time 3 tOSC4 5 — ms 23.8 IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200 μs 23.10 TRST reset hold time tTRSTRH 0 — ns 23.3, 23.5 Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 28 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. Page 1006 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics tEXcyc tEXL tEXH VIH VIH VIH 1/2VDDQ 1/2VDDQ VIL VIL tEXf tEXr Note: When the clock is input from the EXTAL pin Figure 23.1 EXTAL Clock Input Timing tcyc tCKOL1 tCKOH1 VOH VOH VOH 1/2VDDQ 1/2VDDQ VOL VOL tCKOf tCKOr Figure 23.2 (1) CKIO Clock Output Timing tCKOH2 1.5 V tCKOL2 1.5 V 1.5 V Figure 23.2 (2) CKIO Clock Output Timing R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1007 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Stable oscillation CKIO, internal clock VDD min VDD tRESW tOSC1 RESET tOSCMD tMDRH MD10 to MD0 tTRSTRH TRST (High) CA Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 not operating Figure 23.3 Power-On Oscillation Settling Time Standby Stable oscillation CKIO, internal clock tRESW tOSC2 RESET or MRESET Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 not operating Figure 23.4 Standby Return Oscillation Settling Time (Return by RESET or MRESET) Page 1008 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Stable oscillation Internal clock VDD min VDD tRESW tOSC1 RESET tOSCMD tMDRH MD10 to MD0 tTRSTRH TRST CKIO Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 operating Figure 23.5 Power-On Oscillation Settling Time Stable oscillation Standby Internal clock tRESW tOSC2 RESET or MRESET CKIO Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 operating Figure 23.6 Standby Return Oscillation Settling Time (Return by RESET or MRESET) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1009 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Standby Stable oscillation CKIO, internal clock tOSC3 NMI Note: Oscillation settling time when on-chip resonator is used Figure 23.7 Standby Return Oscillation Settling Time (Return by NMI) Stable oscillation Standby CKIO, internal clock tOSC4 IRL3–IRL0 Note: Oscillation settling time when on-chip resonator is used Figure 23.8 Standby Return Oscillation Settling Time (Return by IRL3–IRL0) Page 1010 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Reset or NMI interrupt request Stable input clock Stable input clock EXTAL input tPLL × 2 PLL synchronization PLL synchronization PLL output, CKIO output Internal clock STATUS1– STATUS0 Normal Normal Standby Note: When an external clock is input from EXTAL. Figure 23.9 PLL Synchronization Settling Time in Case of RESET, MRESET or NMI Interrupt IRL3–IRL0 interrupt request Stable input clock Stable input clock EXTAL input PLL synchronization tIRLSTB tPLL × 2 PLL synchronization PLL output, CKIO output Internal clock STATUS1– STATUS0 Normal Standby Normal Note: When an external clock is input from EXTAL. Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1011 of 1128 Section 23 Electrical Characteristics 23.3.2 SH7751 Group, SH7751R Group Control Signal Timing Table 23.19 Control Signal Timing HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751 RBA240HV HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 2 RBA240HV* 1 HD6417751 RF240 (V) 1 * HD6417751 RF200 (V) 1 * 1 * * Item Symbol Min Max Min Max Min Max Min Max Unit Figure BREQ setup time tBREQS 2.0 — 2.5 — 3.5 — 3.5 — ns 23.11 BREQ hold time tBREQH 1.5 — 1.5 — 1.5 — 1.5 — ns 23.11 BACK delay time tBACKD — 5.3 — 5.3 — 6 — 6 ns 23.11 Bus tri-state delay time tBOFF1 — 12 — 12 — 12 — 12 ns 23.11 Bus tri-state delay time to standby mode tBOFF2 — 2 — 2 — 2 — 2 tcyc 23.12 (2) Bus buffer on time tBON1 — 12 — 12 — 12 — 12 ns 23.11 Bus buffer on time from standby tBON2 — 2 — 2 — 2 — 2 tcyc 23.12 (2) STATUS 0/1 delay time tSTD1 — 6 — 6 — 6 — 6 ns 23.12 (1) tSTD2 — 2 — 2 — 2 — 2 tcyc 23.12 (1) (2) tSTD3 — 2 — 2 — 2 — 2 tcyc 23.12 (2) Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta= –20 to 75°C*3, CL = 30 pF, PLL2 on 2. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. 3. Ta = –40 to 85°C for the HD6417751RBA240HV. Page 1012 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Table 23.20 Control Signal Timing HD6417751BP167 (V) HD6417751F167 (V) * Item Symbol Min Max Unit Figure BREQ setup time tBREQS 3.5 — ns 23.11 BREQ hold time tBREQH 1.5 — ns 23.11 BACK delay time tBACKD — 8 ns 23.11 Bus tri-state delay time tBOFF1 — 12 ns 23.11 Bus tri-state delay time to standby mode tBOFF2 — 2 tcyc 23.12 (2) Bus buffer on time tBON1 — 12 ns 23.11 Bus buffer on time from standby tBON2 — 2 tcyc 23.12 (2) STATUS 0/1 delay time tSTD1 — 6 ns 23.12 (1) tSTD2 — 2 tcyc 23.12 (1) (2) tSTD3 — 2 tcyc 23.12 (2) Note: * VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to 75°C, CL = 30 pF, PLL2 on R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1013 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group CKIO tBREQH tBREQH tBREQS tBREQS BREQ tBACKD tBACKD BACK A25–A0, CSn, BS, RD/WR, CE2A, CE2B, RAS, WEn, RD, CASn tBOFF1 tBON1 Figure 23.11 Control Signal Timing Normal operation Reset or sleep mode Normal operation CKIO STATUS1, STATUS0 normal reset or sleep tSTD2 normal tSTD1 Figure 23.12 (1) Pin Drive Timing for Reset or Sleep Mode Page 1014 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Normal operation Reset or sleep mode Normal operation CKIO STATUS1, STATUS0 normal software standby tSTD2 CSn, RD, RD/WR, WEn, BS, RAS CE2A, CE2B, CASn normal tSTD3 tBOFF2 tBON2 A25−A0, D31−D0 DACKn, DRAKn, SCK,* TXD, TXD2, CTS2, RTS2 Note: * These pins can be put into a high-impedance state with STBCR.PHZ. Figure 23.12 (2) Pin Drive Timing for Software Standby Mode R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1015 of 1128 Section 23 Electrical Characteristics 23.3.3 SH7751 Group, SH7751R Group Bus Timing Table 23.21 Bus Timing (1) HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751 RBA240HV HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 2 RBA240HV* 1 HD6417751 RF240 (V) 1 * HD6417751 RF200 (V) 1 * 1 * * Item Symbol Min Max Min Max Min Max Min Max Unit Address delay time tAD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns BS delay time tBSD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns CS delay time tCSD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns RW delay time tRWD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns RD delay time tRSD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns Read data setup time tRDS 2.0 — 2.5 — 3.5 — 3.5 — ns Read data hold time tRDH 1.5 — 1.5 — 1.5 — 1.5 — ns WE delay time (falling edge) tWEDF — 5.3 — 5.3 — 6 — 6 ns WE delay time tWED1 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns Write data delay time tWDD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns RDY setup time tRDYS 2.0 — 2.5 — 3.5 — 3.5 — ns RDY hold time tRDYH 1.5 — 1.5 — 1.5 — 1.5 — ns RAS delay time tRASD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns CAS delay time 1 tCASD1 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns CAS delay time 2 tCASD2 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns SDRAM CKE delay time tCKED 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns SDRAM DQM delay time tDQMD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns SDRAM FRAME delay time tFMD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns MPX IOIS16 setup time tIO16S 2.0 — 2.5 — 3.5 — 3.5 — ns PCMCIA IOIS16 hold time tIO16H 1.5 — 1.5 — 1.5 — 1.5 — ns PCMCIA ICIOWR delay time (falling edge) tICWSDF 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns PCMCIA ICIORD delay time tICRSD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns PCMCIA Page 1016 of 1128 Notes Relative to CKIO falling edge DRAM R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751 RBA240HV HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 2 RBA240HV* 1 HD6417751 RF240 (V) 1 1 * * HD6417751 RF200 (V) 1 * * Item Symbol Min Max Min Max Min Max Min Max Unit DACK delay time tDACD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns DACK delay time (falling edge) tDACDF 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns DTR setup time tDTRS 2.0 — 2.5 — 3.5 — 3.5 — ns DTR hold time tDTRH 1.5 — 1.5 — 1.5 — 1.5 — ns DBREQ setup time tDBQS 2.0 — 2.5 — 3.5 — 3.5 — ns DBREQ hold time tDBQH 1.5 — 1.5 — 1.5 — 1.5 — ns TR setup time tTRS 2.0 — 2.5 — 3.5 — 3.5 — ns TR hold time tTRH 1.5 — 1.5 — 1.5 — 1.5 — ns BAVL delay time tBAVD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns TDACK delay time tTDAD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns ID1, ID0 delay time tIDD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns Notes Relative to CKIO falling edge Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C*3, CL = 30 pF, PLL2 on 2. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. 3. Ta = –40 to 85°C for the HD6417751RBA240HV. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1017 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.22 Bus Timing (2) HD6417751BP167 (V) HD6417751F167 (V) * Item Symbol Min Max Unit Address delay time tAD 1.0 8 ns BS delay time tBSD 1.0 8 ns CS delay time tCSD 1.0 8 ns RW delay time tRWD 1.0 8 ns RD delay time tRSD 1.0 8 ns Read data setup time tRDS 3.5 — ns Read data hold time tRDH 1.5 — ns WE delay time (falling edge) tWEDF 1.0 8 ns WE delay time tWED1 1.0 8 ns Write data delay time tWDD 1.0 8 ns RDY setup time tRDYS 3.5 — ns RDY hold time tRDYH 1.5 — ns RAS delay time tRASD 1.0 8 ns CAS delay time 1 tCASD1 1.0 8 ns DRAM CAS delay time 2 tCASD2 1.0 8 ns SDRAM CKE delay time tCKED 1.0 8 ns SDRAM DQM delay time tDQMD 1.0 8 ns SDRAM FRAME delay time tFMD 1.0 8 ns MPX IOIS16 setup time tIO16S 3.5 — ns PCMCIA IOIS16 hold time tIO16H 1.5 — ns PCMCIA ICIOWR delay time (falling edge) tICWSDF 1.0 8 ns PCMCIA ICIORD delay time tICRSD 1.0 8 ns PCMCIA DACK delay time tDACD 1.0 8 ns DACK delay time (falling edge) tDACDF 1.0 8 ns DTR setup time tDTRS 3.5 ⎯ ns Page 1018 of 1128 Notes Relative to CKIO falling edge Relative to CKIO falling edge R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics HD6417751BP167 (V) HD6417751F167 (V) * Item Symbol Min Max Unit DTR hold time tDTRH 1.5 ⎯ ns DBREQ setup time tDBQS 3.5 ⎯ ns DBREQ hold time tDBQH 1.5 ⎯ ns TR setup time tTRS 3.5 ⎯ ns TR hold time tTRH 1.5 ⎯ ns BAVL delay time tBAVD 1.0 8 ns TDACK delay time tTDAD 1.0 8 ns ID1, ID0 delay time tIDD 1.0 8 ns Note: * Notes VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1019 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group T1 T2 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 CSn RD/WR tRSD tRSD tRSD RD tRDS D31–D0 (read) tWED1 tWEDF tRDH tWEDF WEn tWDD tWDD tWDD D31–D0 (write) tBSD tBSD BS RDY tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) tDACD tDACD tDACD tDACDF tDACD DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (No Wait) Page 1020 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics T1 Tw T2 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 CSn RD/WR tRSD tRSD tRSD RD tRDS D31–D0 tRDH (read) tWED1 tWEDF tWEDF WEn tWDD tWDD tWDD D31–D0 (write) tBSD tBSD BS tRDYS tRDYH RDY tDACD tDACD tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) tDACD tDACDF tDACD DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.14 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1021 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group T1 Tw Twe T2 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 CSn RD/WR tRSD tRSD tRSD RD tRDS D31–D0 (read) tWED1 tWEDF tRDH tWEDF WEn tWDD tWDD tWDD D31–D0 (write) tBSD tBSD BS tRDYS tRDYH RDY tDACD DACKn (SA: IO ← memory) tDACDF tRDYS tDACD tRDYH tDACD tDACDF DACKn (SA: IO → memory) tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) Page 1022 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics TS1 T1 T2 TH1 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 CSn RD/WR tRSD tRSD tRSD RD tRDS D31–D0 (read) tWED1 tWEDF WEn tWDD tRDH tWEDF tWDD tWDD D31–D0 (write) tBSD tBSD BS RDY tDACD tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) DACKn (DA) tDACD tDACD tDACDF tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1023 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CKIO tAD tAD A25–A5 tAD A4–A0 tCSD tCSD tRWD tRWD CSn RD/WR tRSD tRSD tRSD RD tRDS D31–D0 (read) tBSD tRDH tRDS tRDH tBSD BS RDY tDACD tDACD DACKn (SA: IO ← memory) tDACD tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.17 Burst ROM Bus Cycle (No Wait) Page 1024 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tDACD tDACD tDACD Twb tRDH tAD TB1 tRDYH TB2 tRDS tRDYH Twe tRDYS tRSD tRDYS tBSD tRWD tCSD tAD Tw Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) DACKn (SA: IO ← memory) RDY BS D31–D0 (read) RD RD/WR CSn A4–A0 A25–A5 CKIO T1 TB2 TB1 Twb TB2 Twb tRDYS TB1 tRDH tRWD tAD tRDYH tDACD tRDS tRSD tCSD T2 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.18 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait) Page 1025 of 1128 Page 1026 of 1128 tDACD tDACD tBSD tRWD tCSD tAD T1 tRDS tRSD TB2 tDACD tBSD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) DACKn (SA: IO ← memory) RDY BS D31–D0 (read) RD RD/WR CSn A4–A0 A25–A5 CKIO TS1 tDACD tAD TS1 tRDH TH1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 tRDS T2 tDACD tRDH TH1 tRSD tRWD tCSD tAD Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.19 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tBSD tRSD Tw tDACD tDACD TB2 tDACD tRDH tAD TB1 tRDYH tRDS tRDYH Twe tRDYS tDACD tRDYS tBSD tRSD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) DACKn (SA: IO ← memory) RDY BS D31–D0 (read) RD RD/WR CSn A4–A0 A25–A5 CKIO T1 Twb Twbe TB2 TB1 Twb Twbe TB2 tBSD Twb tRDYS tBSD TB1 tRDYS T2 tRDS tRDH tRSD tRWD tCSD tAD tRDYH tDACD tRDYH Twbe SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.20 Burst ROM Bus Cycle (One Internal Wait + One External Wait) Page 1027 of 1128 Page 1028 of 1128 Row Address tRASD tRWD tCASD2 tRASD Trw Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE BS D31–D0 (read) DQMn CASS RAS RD/WR CSn Row Precharge-sel tCSD Row tAD Tr Bank CKIO tDQMD tCASD2 Tc2 column H/L tAD Tc1 tDACD tBSD Tc3 tRDS Tc4/Td1 tRDH tDACD tBSD c1 Td2 tDQMD Td3 Td4 tRWD tCSD tAD Tpc Tpc Tpc Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.21 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tRASD tRWD tCSD Row Row Row tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE BS D31–D0 (read) DQMn CASS RAS RD/WR CSn Address Precharge-sel Bank CKIO Tr tRASD Trw Tc2 tDQMD tCASD2 tCASD2 c1 H/L tAD Tc1 tBSD Tc3 c1 tDACD tRDS Tc4/Td1 tBSD c2 tRDH c5 H/L tAD Td2 Td3 c3 Td4 c4 Td5 c5 Td6 c6 c7 tDQMD Td7 Td8 c8 tDACD tRWD tCSD tAD Tpc Tpc Tpc SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.22 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) Page 1029 of 1128 Page 1030 of 1128 tRASD tRWD Legend: :IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE BS D31–D0 (read) DQMn CASS RAS RD/WR tCSD tRASD tCASD2 tDQMD c1 Row Address CSn H/L Row Precharge-sel tAD Tc1 Row tAD Trw Bank CKIO Tr tCASD2 Tc2 Tc3 tDACD tBSD tRDS Tc4/Td1 c1 tBSD c2 tRDH c5 H/L tAD Td2 Td3 c3 Td4 c4 Td5 c5 Td6 c6 c7 tDQMD Td7 Td8 c8 tDACD tRWD tCSD tAD Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.23 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD [1:0] = 01, CAS Latency = 3) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tRWD tRASD tRASD tRWD tCSD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE BS D31–D0 (read) DQMn CASS RAS RD/WR CSn Address Row Row tAD Tr Precharge-sel H/L Tpc Row tAD Tpr Bank CKIO tCASD2 Trw tDQMD c1 H/L tAD Tc1 tCASD2 Tc2 Tc3 c1 tDACD tBSD tRDS Tc4/Td1 tBSD c2 tRDH c5 H/L tAD Td2 Td3 c3 Td4 c4 Td5 c5 Td6 c6 Td8 c7 tDQMD Td7 c8 tDACD tCSD tAD SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001, CAS Latency = 3) Page 1031 of 1128 Page 1032 of 1128 c1 H/L tDQMD tCASD2 tRASD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE BS D31–D0 (read) DQMn CASS RAS RD/WR CSn Address Precharge-sel Bank CKIO Tc1 tCASD2 Tc2 Tc3 tDACD tBSD tRDS Tc4/Td1 c1 c5 H/L tBSD c2 tRDH tAD Td2 Td3 c3 Td4 c4 Td5 c5 Td6 c6 tDQMD Td7 c7 Td8 c8 tDACD tRASD tRWD tCSD tAD Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (RASD = 1, CAS Latency = 3) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Tr Section 23 Electrical Characteristics Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc CKIO tAD tAD Bank Row Precharge-sel Row H/L Address Row c1 tAD tCSD tCSD CSn tRWD tRWD RD/WR tRASD tRASD RAS tCASD2 tCASD2 tDQMD tDQMD CASS DQMn tWDD D31–D0 (write) tWDD c1 tBSD BS tBSD CKE DACKn (SA: IO → memory) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1033 of 1128 Page 1034 of 1128 tDACD tCASD2 tRASD tCSD Row Row Row tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) CKE BS D31–D0 (write) DQMn CASS RAS RD/WR CSn Address Precharge-sel Bank CKIO Tr tWDD tRASD Trw tBSD c1 tDQMD tCASD2 tRWD c1 H/L tAD Tc1 tBSD c2 tWDD tCASD2 tRWD Tc2 Tc3 c3 Tc4 c4 c5 c5 H/L tAD Tc5 Tc6 c6 c7 tDACD Tc7 Tc8 c8 tDQMD tCSD tAD Trwl Trwl Tpc Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tDACD tRASD tCSD Row Row Row tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) CKE BS D31–D0 (write) DQMn CASS RAS RD/WR CSn Address Precharge-sel Bank CKIO Tr tWDD tRASD Trw tBSD c1 tDQMD tCASD2 tRWD c1 H/L tAD Tc1 tBSD c2 tWDD tCASD2 tRWD Tc2 Tc3 c3 Tc4 c4 c5 c5 H/L tAD Tc5 Tc6 c6 c7 tDACD Tc7 Tc8 c8 tDQMD tCSD tAD Trwl Trwl SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RASD = 1, RCD [1:0] = 01, TRWL [2:0] = 010) Page 1035 of 1128 Page 1036 of 1128 tRASD tRWD tCSD H/L tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) CKE BS D31–D0 (write) DQMn CASS RAS RD/WR CSn Address Precharge-sel Bank CKIO Tpr tRASD tRWD Tpc tDACD Row Row Row tAD Tr tWDD Trw Tc2 tBSD c1 tDQMD tBSD c2 tWDD tCASD2 tCASD2 c1 H/L tAD Tc1 Tc3 c3 Tc4 c4 c5 c5 H/L tAD Tc5 Tc6 c6 c7 tDACD Tc7 Tc8 c8 tDQMD tCSD tAD Trwl Trwl Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.29 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tDACD tRASD tWDD tCASD2 (Tnop) tBSD c1 tDQMD tRWD tCSD c1 H/L tAD Tc1 Tc3 c3 Single address DMA tBSD c2 tWDD tCASD2 tRWD Tc2 Tc4 c4 c5 c5 H/L tAD Tc5 Tc6 c6 c7 tDACD Tc7 Tc8 c8 tDQMD tCSD tAD Trwl Normal write Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the dotted line. DACKn (SA: IO → memory) CKE BS D31–D0 (write) DQMn CASS RAS RD/WR CSn Address Precharge-sel Bank CKIO Tnop Trwl tDACD SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL [2:0] = 010) Page 1037 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Tpr Tpc CKIO tAD tAD Bank Row Precharge-sel H/L Address tCSD tCSD CSn tRWD tRWD tRASD tRASD RD/WR RAS tCASD2 tCASD2 tDQMD tDQMD tWDD tWDD CASS DQMn D31–D0 (write) tBSD BS CKE tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.31 Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001) Page 1038 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group TRr1 TRr2 Section 23 Electrical Characteristics TRr3 TRr4 TRrw TRr5 Trc Trc Trc CKIO tAD tAD Bank Precharge-sel Address tCSD tCSD tCSD tCSD CSn tRWD tRWD RD/WR tRASD tRASD tRASD tCASD2 tCASD2 tCASD2 tRASD RAS tCASD2 CASS tDQMD tDQMD DQMn D31–D0 (write) tWDD tWDD tBSD BS CKE tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1039 of 1128 Section 23 Electrical Characteristics TRs1 TRs2 SH7751 Group, SH7751R Group TRs3 TRs4 TRs5 Trc Trc Trc CKIO tAD tAD Bank Precharge-sel Address tCSD tCSD tCSD tCSD CSn tRWD tRWD RD/WR tRASD tRASD tRASD tRASD RAS tCASD2 tCASD2 tCASD2 tCASD2 CASS tDQMD tDQMD DQMn tWDD tWDD D31–D0 (write) tBSD BS tCKED tCKED CKE tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001) Page 1040 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group TRp1 TRp2 Section 23 Electrical Characteristics TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5 CKIO tAD tAD tAD Bank Precharge-sel Address tCSD tCSD tCSD CSn tRWD tRWD tRWD tRASD tRASD tRASD tCASD2 tCASD2 RD/WR RAS tCASD2 tCASD2 CASS tDQMD tDQMD tWDD tWDD DQMn D31–D0 (write) tBSD BS CKE tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.34 (a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1041 of 1128 Section 23 Electrical Characteristics TRp1 TRp2 SH7751 Group, SH7751R Group TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5 CKIO tAD tAD tAD Bank Precharge-sel Address tCSD tCSD tCSD tRWD tRWD tRWD tRASD tRASD tRASD tCASD2 tCASD2 CSn RD/WR RAS tCASD2 tCASD2 CASS tDQMD tDQMD tWDD tWDD DQMn D31–D0 (write) tBSD BS CKE tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.34 (b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET) Page 1042 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tDACD tDACD tDACD tWDD tRASD tDACD tWDD tCASD1 tRASD tRWD tCSD Row tAD Tr2 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) BS D31–D0 (write) D31–D0 (read) CASn RAS RD/WR CSn A25–A0 CKIO Tr1 tBSD (1) tCASD1 Tc2 tBSD tRDS column tAD Tc1 tDACD tDACD tWDD tRDH tCASD1 tRASD tRWD tCSD tAD Tpc tDACD tDACD tWDD tCASD1 tRASD tRWD tCSD Row tAD Tr1 tDACD tDACD tWDD tRASD Tr2 Trw tBSD tBSD Tc2 tRDS tCASD1 Tcw (2) column tAD Tc1 tDACD tDACD tWDD tRDH tCASD1 tRASD tRWD tCSD tAD Tpc Tpc SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.35 DRAM Bus Cycles (1) RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001 (2) RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 010 Page 1043 of 1128 Page 1044 of 1128 tDACD Tr2 tDACD tRASD Row tCASD1 tRASD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D31–D0 (read) CASn RAS RD/WR CSn Address CKIO Tr1 tBSD tCASD1 tAD Tc1 tBSD column Tc2 tRDS Tce tRDH tCASD1 tRASD tRWD tCSD tAD Tpc Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.36 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TRC [2:0] = 001) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tDACD Tr2 tDACD tRASD Row tCASD1 tRASD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D31–D0 (read) CASn RAS RD/WR CSn Address CKIO Tr1 tBSD tCASD1 tAD Tc1 tBSD c1 Tc2 tRDS tCASD1 Tc1 d1 c2 tRDH tDACD Tc2 Tc1 d2 Tc2 Tc1 tCASD1 c8 Tc2 tRDS Tce d8 tRDH tCASD1 tRASD tRWD tCSD tAD Tpc SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.37 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) Page 1045 of 1128 Page 1046 of 1128 tRASD Row Tr2 tDACD tDACD tCASD1 tRASD tRWD tCSD tAD Tr1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D31–D0 (read) CASn RAS RD/WR CSn Address CKIO tBSD Trw tAD Tc1 tBSD tCASD1 c1 Tcw Tc2 tRDS tCASD1 Tc1 tRDH tDACD d1 tCASD1 c2 Tcw Tc2 Tc1 Tcw Tc2 Tc1 d7 Tc2 c8 tCASD1 Tcw tRDS Tce d8 tRDH tCASD1 tRASD tRWD tCSD tAD Tpc Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.38 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 c1 Tcw Tc2 Tc1 tCASD1 Tcnw c2 Tc2 tRDH Tcw Tcw Tc1 d2 Tcw Tc2 Tc1 tCASD1 Tcnw Tcw c8 Tc2 Tcnw tRDS Tce tAD Tpc tRASD tDACD t DACD tCASD1 tRASD tBSD tCASD1 tRDS tDACD d1 d8 tRDH tCASD1 tRASD tRWD tAD Tc1 tRWD tBSD Trw tCSD Row Tr2 tCSD tAD Tr1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D31–D0 (read) CASn RAS RD/WR CSn Address CKIO SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.39 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) Page 1047 of 1128 Page 1048 of 1128 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D31–D0 (read) CASn RAS RD/WR CSn Address CKIO Tpc tDACD tCASD1 tRASD tRWD tCSD tAD Tr1 tDACD tBSD tRASD Row Tr2 tCASD1 tAD Tc1 tBSD c1 Tc2 tRDS Tc2 tRDH tDACD c2 d1 tCASD1 Tc1 Tc1 d2 Tc2 tCASD1 Tc1 c8 Tc2 tRDS Tce d8 tRDH tCASD1 tRWD tCSD tAD Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.40 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tRWD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) BS D31–D0 (read) CASn RAS RD/WR CSn Address CKIO Tnop tDACD tBSD tCSD tAD Tc1 tBSD tCASD1 c1 Tc2 tRDS tCASD1 tAD Tc1 d1 tRDH tDACD c2 Tc2 Tc1 d2 Tc2 tCASD1 Tc1 T2 c8 tRDS tRASD Tce d8 RAS-down mode ended tRDH tCASD1 tRWD tCSD tAD SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.41 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) Page 1049 of 1128 Page 1050 of 1128 tDACD tDACD tWDD tCASD1 tRASD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) BS D31–D0 (write) D31–D0 (read) CASn RAS RD/WR CSn Address CKIO Tr1 tDACD tDACD tWDD tRASD Row Tr2 tBSD d1 tAD Tc1 tCASD1 tDACD tBSD tRDS c1 Tc2 d1 tDACD tWDD tRDH tCASD1 Tc1 d2 c2 Tc2 d2 Tc1 Tc2 Tc1 d8 tRDS tCASD1 c8 Tc2 d8 tWDD tRDH tCASD1 tRASD tRWD tCSD tAD Tpc Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.42 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tDACD tDACD tWDD tCASD1 tRASD tRWD tCSD tAD Tr1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) BS D31–D0 (write) D31–D0 (read) CASn RAS RD/WR CSn Address CKIO tDACD tDACD tWDD tRASD Row Tr2 Trw tBSD tAD Tc1 tBSD d1 Tc2 tWDD tRDH tCASD1 Tc1 tDACD d1 tDACD tRDS tCASD1 c1 Tcw d2 c2 Tcw Tc2 d2 Tc1 Tcw Tc2 Tc1 d8 Tc2 tRDS tCASD1 c8 Tcw tRDH tWDD d3 tCASD1 tRASD tRWD tCSD tAD Tpc SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.43 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001) Page 1051 of 1128 Page 1052 of 1128 c1 Tcw Tc2 Tc1 tCASD1 Tcnw c2 Tcw Tc2 d2 Tcw Tc1 Tcw Tc2 Tcnw d8 Tc1 c8 Tcw Tc2 tAD Tcnw tDACD tDACD tWDD tWDD tRASD tDACD tDACD tCASD1 tRASD tBSD tBSD d1 tWDD tRDH tDACD d1 tDACD tRDS tCASD1 d2 tRDS tCASD1 Tpc tRDH tWDD d8 tCASD1 tRASD tRWD tAD Tc1 tRWD Trw tCSD Row Tr2 tCSD tAD Tr1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) BS D31–D0 (write) D31–D0 (read) CASn RAS RD/WR CSn Address CKIO Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Tpc Tr1 Section 23 Electrical Characteristics Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 CKIO tAD Address tAD Row tAD c1 c2 c8 tCSD tCSD tRWD tRWD CSn RD/WR tRASD tRASD RAS tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 CASn tRDS D31–D0 (read) tRDH d1 tWDD tWDD D31–D0 (write) tRDS tWDD d1 tBSD tRDH d8 d2 tWDD d2 d8 tBSD BS tDACD tDACD tDACD tDACD tDACD DACKn (SA: IO ← memory) tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.45 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1053 of 1128 Section 23 Electrical Characteristics Tnop SH7751 Group, SH7751R Group Tc1 Tc2 Tc1 Tc1 Tc2 Tc2 Tc1 Tc2 CKIO tAD Address tAD c1 c2 c8 tCSD CSn tRWD RD/WR RAS down mode ended tRASD RAS tCASD1 tCASD1 tCASD1 tCASD1 CASn tRDS D31–D0 (read) tWDD tRDS tRDH d1 tWDD D31–D0 (write) d1 tBSD d2 tRDH d8 d2 tWDD d8 tBSD BS DACKn (SA: IO ← memory) tDACD tDACD tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.46 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000) Page 1054 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group TRr1 Section 23 Electrical Characteristics TRr2 TRr3 TRr4 TRr5 Trc Trc Trc CKIO tAD A25–A0 tCSD CSn tRWD RD/WR tRASD tRASD tRASD RAS tCASD1 tCASD1 tCASD1 CASn tWDD D31–D0 (write) BS DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.47 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 000, TRC [2:0] = 001) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1055 of 1128 Section 23 Electrical Characteristics TRr1 TRr2 SH7751 Group, SH7751R Group TRr3 TRr4 TRr4w TRr5 Trc Trc Trc CKIO tAD A25–A0 tCSD CSn tRWD RD/WR tRASD tRASD tRASD RAS tCASD1 tCASD1 tCASD1 CASn tWDD D31–D0 (write) BS DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 001, TRC [2:0] = 001) Page 1056 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group TRr1 TRr2 Section 23 Electrical Characteristics TRr3 TRr4 TRr5 Trc Trc Trc CKIO tAD A25–A0 tCSD CSn tRWD RD/WR tRASD tRASD tRASD RAS tCASD1 tCASD1 tCASD1 CASn tWDD D31–D0 (write) BS DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1057 of 1128 Page 1058 of 1128 tDACD tBSD tRDS (1) tBSD tWDD tDACD tWDD tRDH tRSD tRWD tCSD tAD tWEDF tRSD Tpcm2 tWEDF tWDD tWED1 tRSD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) RDY BS D15–D0 (write) WE1 D15–D0 (read) RD RD/WR CExx REG (WE0) A25–A0 CKIO Tpcm1 TED tDACD tBSD tWDD tWED1 tRSD tRWD tCSD tAD Tpcm0 tBSD tWDD Tpcm1 tRDYS tWEDF tRSD Tpcm1w (2) tRDYS TEH tWEDF tWDD tRSD tRWD tCSD tAD tDACD tRDH Tpcm2w tRDYH tRDS Tpcm2 tRDYH Tpcm1w Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 Tpci2 tDACD tIO16S tBSD (1) tWDD tDACD tIO16H tBSD tWDD tICWSDF tICWSDF tRDS tRDH tRWD tCSD tAD tICRSD tICRSD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) IOIS16 RDY BS D15–D0 (write) ICIOWR (WE3) D15–D0 (read) ICIORD (WE2) RD/WR CExx REG (WE0) A25–A0 CKIO Tpci1 tDACD tBSD tWDD tICWSDF tICRSD tRWD tCSD tAD Tpci0 tBSD tWDD Tpci1 tRDYS tICWSDF tRDYH Tpci1w (2) tIO16S tRDYS tICRSD Tpci1w tICWSDF tIO16H tWDD tRWD tCSD tAD tDACD tRDH tICRSD Tpci2w tRDYH tRDS Tpci2 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.51 PCMCIA I/O Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait Page 1059 of 1128 Page 1060 of 1128 Tpci1 tBSD tWDD tBSD tWDD tICWSDF tICWSDF tICRSD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high IOIS16 RDY BS D15–D0 (write) ICIOWR (WE3) D15–D0 (read) ICIORD (WE2) RD/WR CExx REG (WE0) A0 A25–A1 CKIO Tpci0 tICWSDF tRDS Tpci2 tIO16S tIO16H tRDYS tRDYH tICRSD Tpci1w tRDH tICRSD Tpci2w tWDD tCSD tAD Tpci0 tWDD tICWSDF Tpci1 tICWSDF Tpci2 tRDYS tRDYH Tpci1w Tpci2w tWDD tRWD tCSD tAD Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.52 PCMCIA I/O Bus Cycle (TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait, Bus Sizing) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 A tCSD tBSD tRDYS tRDYH Tmd1w tDACD tWED1 tRWD tRDYH tRDH tCSD D0 tRDS Tmd1 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD tRDYS tWED1 tWDD tFMD Tmd1w 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tWED1 A tCSD tRWD tWDD tFMD Tm0 (2) tBSD tRDYH tRDH tCSD tRWD D0 tRDS Tmd1 (1) tDACD tBSD tWDD tFMD tRDYS tWED1 tRWD tWDD tFMD Tmd1w Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) BS RDY WEn RD/WR CSn D63–D0 RD/FRAME CKIO Tm1 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.53 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait) Page 1061 of 1128 Page 1062 of 1128 tWED1 tRWD tCSD tWDD tWED1 tRWD tCSD tWDD tDACD tRDYH 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD D0 Tmd1 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD tWDD tFMD tRDYS tWED1 tRWD tCSD A tWDD tFMD Tmd1w (2) tBSD tRDYH D0 tWDD tFMD Tm1 (1) tDACD tBSD tRDYS tWED1 tRWD tCSD A tWDD tFMD Tmd1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) BS RDY WEn RD/WR CSn D63–D0 RD/FRAME CKIO Tm1 (3) tRDYS tBSD D0 tRDYH Tmd1w tCSD tWDD tDACD tWED1 tRWD tRDYH Tmd1 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD tWDD tFMD Tmd1w tRDYS tWED1 tRWD tCSD A tWDD tFMD Tm1 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.54 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tDACD tBSD Tmd1 tBSD D1 Tmd3 D3 D4 (1) Tmd4 Tmd5 D5 Tmd6 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address D2 tRDH Tmd2 tRDYH tWDD tRDS Tmd1w tRDYS tRWD tCSD A tWDD tFMD Tm1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) BS RDY RD/WR CSn D31–D0 RD/FRAME CKIO D6 Tmd7 D7 tFMD Tmd8 tRWD tCSD tDACD D8 tDACD tBSD Tmd1 tBSD D1 Tmd2 D2 (2) Tmd3 D3 tRDYS Tmd7 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tRDH Tmd2w tRDYH tWDD tRDS Tmd1w tRDYS tRWD tCSD A tWDD tFMD Tm1 D7 tRDYH tFMD Tmd8w Tmd8 tRWD tCSD tDACD D8 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.55 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data (No Internal Wait) (2) 1st Data (No Internal Wait), 2nd to 8th Data (No Internal Wait + External Wait Control) Page 1063 of 1128 Page 1064 of 1128 tDACD tBSD tRDYS tRWD tCSD A tWDD tFMD Tm1 tBSD D3 Tmd3 (1) D4 Tmd4 D5 Tmd5 D6 Tmd6 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address D2 Tmd2 tRDYH D1 tWDD Tmd1 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) BS RDY RD/WR CSn D31–D0 RD/FRAME CKIO D7 Tmd7 D8 tFMD Tmd8 tDACD tRWD tCSD tWDD tWDD Tmd1w tBSD tRDYS tDACD tBSD tRWD tCSD A tWDD tFMD Tm1 D1 D2 Tmd2 (2) D3 Tmd3 D7 Tmd7 tRDYS 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address Tmd2w tRDYH Tmd1 D8 Tmd8 tRDYH tFMD Tmd8w tDACD tRWD tCSD tWDD Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Figure 23.56 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 8th Data (No Internal Wait + External Wait Control) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Sep 24, 2013 R01UH0457EJ0301 Rev. 3.01 tDACD tDACD tBSD tWED1 tRDS tRSD T2 (1) tDACD tBSD tWEDF tRSD tRWD tCSD tAD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) DACKn (SA: IO ← memory) RDY BS WEn D31–D0 (read) RD RD/WR CSn A25–A0 CKIO T1 tDACD tDACD tWED1 tRDH tRSD tRWD tCSD tAD tDACD tDACD tBSD tWED1 tRSD Tw (2) tDACD tRDYS tBSD tWEDF tRSD tRWD tCSD tAD T1 tWED1 tRDH tRSD tRWD tCSD tAD tDACD tDACD tRDYH tRDS T2 tDACD tRSD Tw (3) tRDYH Twe tRDYS tDACD tRDYS tBSD tWEDF tDACD tBSD tWED1 tRSD tRWD tCSD tAD T1 tRDH tRSD tRWD tCSD tAD tDACD tDACD tWED1 tRDYH tRDS T2 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Figure 23.57 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait) Page 1065 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group TS1 T1 T2 TH1 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 CSn RD/WR tRSD tRSD tRSD RD D31–D0 (read) tRDS tWED1 tRDH tWED1 tWEDF WEn tBSD tBSD BS RDY tDACD tDACD DACKn (SA: IO ← memory) tDACD tDACD DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.58 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS [0] = 1, AnH [1:0] = 01) Page 1066 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 23.3.4 Section 23 Electrical Characteristics Peripheral Module Signal Timing Table 23.23 Peripheral Module Signal Timing (1) HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751 RBA240HV HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 RBA240HV*3 HD6417751 RF240 (V) HD6417751 RF200 (V) *2 *2 *2 *2 Module Item Symbol Min Max Min Max Min Max Min Max Unit TMU, RTC Timer clock pulse width (high) tTCLKWH 4 — 4 — 4 — 4 — Pcyc*1 23.59 Timer clock pulse width (low) tTCLKWL 4 — 4 — 4 — 4 — Pcyc*1 23.59 Timer clock rise time tTCLKr — 0.8 — 0.8 — 0.8 — 0.8 Pcyc*1 23.59 Timer clock fall time tTCLKf — 0.8 — 0.8 — 0.8 — 0.8 Pcyc*1 23.59 Oscillation settling time tROSC — 3 — 3 — 3 — 3 s Input clock cycle (asynchronous) tScyc 4 — 4 — 4 — 4 — Pcyc*1 23.61 Input clock cycle (synchronous) tScyc 6 — 6 — 6 — 6 — Pcyc*1 23.61 Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tScyc Input clock rise time tSCKr — 0.8 — 0.8 — 0.8 — 0.8 Pcyc*1 23.61 Input clock fall tSCKf time — 0.8 — 0.8 — 0.8 — 0.8 Pcyc*1 23.61 Transfer data delay time tTXD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns 23.62 Receive data tRXS setup time (synchronous) 16 — 16 — 16 — 16 — ns 23.62 Receive data tRXH hold time (synchronous) 16 — 16 — 16 — 16 — ns 23.62 SCI R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Figure Notes 23.60 23.61 Page 1067 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751 RBA240HV HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 RBA240HV*3 HD6417751 RF240 (V) HD6417751 RF200 (V) *2 *2 *2 *2 Module Item Symbol Min Max Min Max Min Max Min Max Unit Figure I/O ports Output data delay time tPORTD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns 23.63 Input data setup time tPORTS 2 — 2.5 — 3.5 — 3.5 — ns 23.63 Input data hold tPORTH time 1.5 — 1.5 — 1.5 — 1.5 — ns 23.63 DREQn setup time tDRQS 2 — 2.5 — 3.5 — 3.5 — ns 23.64 DREQn hold time tDRQH 1.5 — 1.5 — 1.5 — 1.5 — ns 23.64 DRAKn delay time tDRAKD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns 23.64 NMI pulse width (high) tNMIH 5 — 5 — 5 — 5 — tcyc 23.69 Normal or sleep mode 30 — 30 — 30 — 30 — ns 23.69 Standby mode 5 — 5 — 5 — 5 — tcyc 23.69 Normal or sleep mode 30 — 30 — 30 — 30 — ns 23.69 Standby mode DMAC INTC NMI pulse width (low) H-UDI tNMIL Input clock cycle tTCKcyc 50 — 50 — 50 — 50 — ns 23.65, 23.67 Input clock pulse width (high) tTCKH 15 — 15 — 15 — 15 — ns 23.65 Input clock pulse width (low) tTCKL 15 — 15 — 15 — 15 — ns 23.65 Input clock rise time tTCKr — 10 — 10 — 10 — 10 ns 23.65 Input clock fall tTCKf time — 10 — 10 — 10 — 10 ns 23.65 ASEBRK setup time tASEBRKS 10 — 10 — 10 — 10 — tcyc 23.66 ASEBRK hold tASEBRKH time 10 — 10 — 10 — 10 — tcyc 23.66 Page 1068 of 1128 Notes R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics HD6417751 RBP240 (V) HD6417751 RBG240 (V) HD6417751 RBA240HV HD6417751 RBP200 (V) HD6417751 RBG200 (V) HD6417751 RBA240HV*3 HD6417751 RF240 (V) HD6417751 RF200 (V) *2 *2 *2 *2 Module Item Symbol Min Max Min Max Min Max Min Max Unit Figure H-UDI TDI/TMS setup time tTDIS 15 — 15 — 15 — 15 — ns 23.67 TDI/TMS hold time tTDIH 15 — 15 — 15 — 15 — ns 23.67 TDO delay time tTDO 0 10 0 10 0 10 0 10 ns 23.67 ASE-PINBRK pulse width tPINBRK 2 — 2 — 2 — 2 — Pcyc*1 23.68 Notes Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C* , CL = 30 pF, PLL2 on 3. This is the case when the device in use is an HD6417751RBA240HV running at 200 MHz. 4. Ta = –40 to 85°C for the HD6417751RBA240HV. 4 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1069 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.24 Peripheral Module Signal Timing (2) HD6417751BP167 (V) HD6417751F167 (V) 2 * Module Symbol Min Max Unit TMU, RTC Timer clock pulse width (high) tTCLKWH 4 — Pcyc* Timer clock pulse width (low) tTCLKWL 4 — Pcyc* Timer clock rise time tTCLKr — 0.8 Pcyc* Timer clock fall time tTCLKf — 0.8 Oscillation settling time tROSC — Input clock cycle (asynchronous) tScyc Input clock cycle (synchronous) Input clock pulse width SCI Item 23.59 1 23.59 1 23.59 Pcyc* 1 23.59 3 s 23.60 4 — Pcyc* tScyc 6 — tSCKW 0.4 — Input clock rise time tSCKr I/O ports DMAC Figure 1 1 23.61 Pcyc* 1 23.61 0.6 tScyc 23.61 0.8 Pcyc* 1 23.61 1 Input clock fall time tSCKf — 0.8 Pcyc* 23.61 Transfer data delay time tTXD — 30 ns 23.62 Receive data setup time (synchronous) tRXS 0.8 — Pcyc* Receive data hold time (synchronous) tRXH 0.8 — Output data delay time tPORTD — Input data setup time tPORTS Input data hold time tPORTH 1 23.62 Pcyc* 1 23.62 8 ns 23.63 3.5 — ns 23.63 1.5 — ns 23.63 DREQn setup time tDRQS 3.5 — ns 23.64 DREQn hold time tDRQH 1.5 — ns 23.64 DRAKn delay time tDRAKD — 8 ns 23.64 Page 1070 of 1128 Notes R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics HD6417751BP167 (V) HD6417751F167 (V) 2 * Module Item Symbol Min Max Unit Figure Notes INTC NMI pulse width (high) tNMIH 5 — tcyc 23.69 Normal or sleep mode 30 — ns 23.69 Standby mode 5 — tcyc 23.69 Normal or sleep mode 30 — ns 23.69 Standby mode NMI pulse width (low) H-UDI tNMIL Input clock cycle tTCKcyc 50 — ns 23.65, 23.67 Input clock pulse width (high) tTCKH 15 — ns 23.65 Input clock pulse width (low) tTCKL 15 — ns 23.65 Input clock rise time tTCKr — 10 ns 23.65 Input clock fall time — 10 ns 23.65 ASEBRK setup time tASEBRKS 10 — tcyc 23.66 ASEBRK hold time tTCKf 10 — tcyc 23.66 TDI/TMS setup time tTDIS tASEBRKH 15 — ns 23.67 TDI/TMS hold time 15 — ns 23.67 tTDIH TDO delay time tTDO 0 10 ns ASE-PINBRK pulse width tPINBRK 2 — Pcyc* 23.67 1 23.68 Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to 75°C, CL = 30 pF, PLL2 on R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1071 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group TCLK tTCLKWH tTCLKWL tTCLKf tTCLKr Figure 23.59 TCLK Input Timing Oscillation settling time RTC internal clock VDD-RTC VDD-RTC min tROSC Figure 23.60 RTC Oscillation Settling Time at Power-On tSCKW SCK, SCK2 tScyc tSCKf tSCKr Figure 23.61 SCK Input Clock Timing Page 1072 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics tScyc SCK tTXD tTXD TXD RXD tRXS tRXH Figure 23.62 SCI I/O Synchronous Mode Clock Timing CKIO Ports 31–0 (read) tPORTS tPORTH Ports 31–0 (write) tPORTD tPORTD Figure 23.63 I/O Port Input/Output Timing CKIO tDRQH tDRQH DREQn tDRQS DRAKn tDRQS tDRAKD Figure 23.64 (a) DREQ/DRAK Timing R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1073 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group CKIO tDBQS tDBQH DBREQ tBAVD tBAVD BAVL tTRH tTRS TR tDTRS D31 to D0 (READ) (1) tDTRH (2) (1): [2CKIO cycle – tDTRS] (= 18 ns: 100 MHz) (2): DTR = 1CKIO cycle (= 10 ns: 100 MHz) (tDTRS + tDTRH) < DTR < 10 ns Figure 23.64 (b) DBREQ/TR Input Timing and BAVL Output Timing tTCKcyc tTCKL tTCKH VIH VIH VIH 1/2VDDQ 1/2VDDQ VIL VIL tTCKf tTCKr Note: When clock is input from TCK pin Figure 23.65 TCK Input Timing Page 1074 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics RESET tASEBRKS tASEBRKH ASEBRK/ BRKACK Figure 23.66 RESET Hold Timing tTCKcyc TCK tTDIS TDI TMS tTDIH tTDO TDO Figure 23.67 H-UDI Data Transfer Timing tPINBRK ASEBRK Figure 23.68 Pin Break Timing tNMIH tNMIL NMI Figure 23.69 NMI Input Timing R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1075 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group Table 23.25 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1) HD6417751RBP240 (V), HD6417751RBP200 (V), HD6417751RBG240 (V), HD6417751RBG200 (V), HD6417751RBA240HV, HD6417751RF240 (V), HD6417751RF200 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75°C*2, CL = 30 pF 33 MHz 66 MHz Pin Item Symbol Min Max Min Max Unit Figure PCICLK Clock cycle tPCICYC 30 — 15 30 ns 23.70 Clock pulse width (high) tPCIHIGH 11 — 6 — ns 23.70 Clock pulse width (low) tPCILOW 11 — 6 — ns 23.70 Clock rise time tPCIr — 4 — 1.5 ns 23.70 Clock fall time tPCIf — 4 — 1.5 ns 23.70 PCIRST Output data delay time tPCIVAL — 10 — 8 ns 23.71 IDSEL Input hold time tPCIH 1.5 — 1.5 — ns 23.72 3.0 1 (3.5* ) — ns 23.72 Input setup time 1 tPCISU 3.0 (3.5* ) — AD31–AD0 Output data delay time tPCIVAL — 10 — 8 ns 23.71 C/BE3–C/BE0 Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 — 12 ns 23.71 TRDY Input hold time tPCIH 1.5 — 1.5 — ns 23.72 PCISTOP Input setup time tPCISU 3.0 (3.5* ) — 3.0 1 (3.5* ) — ns 23.72 Output data delay time tPCIVAL — 10 — 8 ns 23.71 Tri-state drive delay time tPCION — 10 — 10 ns 23.71 PCIREQ3/ MD10 Tri-state high-impedance delay time tPCIOFF — 12 12 ns 23.71 PCIREQ4/ PCIGNT1/ REQOUT Input hold time tPCIH 1.5 1.5 — ns 23.72 Input setup time tPCISU 3.0 (3.5* ) — 3.0 1 (3.5* ) — ns 23.72 Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 — 12 ns 23.71 PAR PCIFRAME IRDY 1 PCILOCK DEVSEL PERR PCIREQ1/ GNTIN PCIREQ2/MD9 — 1 PCIGNT4– PCIGNT1 SERR INTA Notes: 1. HD6417751RF240 (V), HD6417751RF200 (V) 2. Ta = –40 to 85°C for the HD6417751RBA240HV. Page 1076 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics Table 23.26 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (2) HD6417751BP167 (V), HD6417751F167 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to 75°C, CL = 30 pF 33 MHz 66 MHz Pin Item Symbol Min Max Min Max Unit Figure PCICLK Clock cycle tPCICYC 30 — 15 30 ns 23.70 Clock pulse width (high) tPCIHIGH 11 — 6 — ns 23.70 Clock pulse width (low) tPCILOW 11 — 6 — ns 23.70 Clock rise time tPCIr — 4 — 1.5 ns 23.70 Clock fall time tPCIf — 4 — 1.5 ns 23.70 PCIRST Output data delay time tPCIVAL — 10 — 10 ns 23.71 IDSEL Input hold time tPCIH 1 — 1 — ns 23.72 Input setup time tPCISU 3.0 (3.5*) — 3.0 (3.5*) — ns 23.72 AD31–AD0 Output data delay time tPCIVAL — 10 — 10 ns 23.71 C/BE3–C/BE0 Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 — 12 ns 23.71 TRDY Input hold time tPCIH 1 — 1 — ns 23.72 PCISTOP Input setup time tPCISU 3.0 (3.5*) — 3.0 (3.5*) — ns 23.72 Output data delay time tPCIVAL — 10 — 10 ns 23.71 Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 12 ns 23.71 PAR PCIFRAME IRDY PCILOCK DEVSEL PERR PCIREQ1/ GNTIN PCIREQ2/ MD9 PCIREQ3/ MD10 PCIREQ4/ PCIGNT1/ REQOUT PCIGNT4– PCIGNT1 SERR INTA Note: * Input hold time tPCIH 1 — 1 — ns 23.72 Input setup time tPCISU 3.0 (3.5*) — 3.0 (3.5*) — ns 23.72 Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 — 12 ns 23.71 HD6417751F167 (V) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1077 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group tPCICYC tPCIHIGH VH tPCILOW VH VH 0.5VDDQ 0.5VDDQ VL VL tPCIr tPCIf Figure 23.70 PCI Clock Input Timing 0.4VDDQ PCICLK tPCIVAL 0.4VDDQ Output delay 3-state output tPCION tPCIOFF Figure 23.71 Output Signal Timing Page 1078 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Section 23 Electrical Characteristics PCICLK 0.4VDDQ tPCISU tPCIH 0.4VDDQ Input 0.4VDDQ Figure 23.72 Output Signal Timing Table 23.27 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (1) HD6417751RBP240 (V), HD6417751RBP200 (V), HD6417751RBG240 (V), HD6417751RBG200 (V), HD6417751RBA240HV, HD6417751RF240 (V), HD6417751RF200 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75°C*, CL = 30 pF Pin Item Symbol Min Max Unit Figure PCIREQ2/MD9 tPCIPORTD — 10 ns 23.73 PCIREQ3/MD10 Output data delay time PCIREQ4 Input hold time tPCIPORTH 1.5 — ns 23.73 Input setup time tPCIPORTS 3.5 — ns 23.73 Output data delay time tPCIPORTD — 10 ns 23.73 PCIGNT4–PCIGNT1 Note: * Ta = –40 to 85°C for the HD6417751RBA240HV. Table 23.28 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (2) HD6417751BP167 (V), HD6417751F167 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to 75°C, CL = 30 pF Pin Item Symbol Min Max Unit Figure PCIREQ2/MD9 Output data delay time tPCIPORTD — 10 ns 23.73 PCIREQ3/MD10 PCIREQ4 Input hold time tPCIPORTH 1.5 — ns 23.73 Input setup time tPCIPORTS 3.5 — ns 23.73 Output data delay time tPCIPORTD — 10 ns 23.73 PCIGNT4–PCIGNT1 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1079 of 1128 Section 23 Electrical Characteristics SH7751 Group, SH7751R Group CKIO tPCIPORTS tPCIPORTH PCIREQn (read) tPCIPORTD tPCIPORTD PCIREQn PCIGNTn (write) Figure 23.73 I/O Port Input/Output Timing Page 1080 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group 23.3.5 Section 23 Electrical Characteristics AC Characteristic Test Conditions The AC characteristic test conditions are as follows: • Input/output signal reference level: 1.5 V (VDDQ = 3.3 ±0.3 V) • Input pulse level: VSSQ to 3.0 V (VSSQ to VDDQ for RESET, TRST, NMI, and ASEBRK/BRKACK) • Input rise/fall time: 1 ns The output load circuit is shown in figure 23.74 IOL DUT output LSI output pin VREF CL IOH Notes: 1. CL is the total value, including the capacitance of the test jig, etc. The capacitance of each pin is set to 30 pF. 2. IOL and IOH values are as shown in table 23.10, Permissible Output Currents. Figure 23.74 Output Load Circuit R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1081 of 1128 Section 23 Electrical Characteristics 23.3.6 SH7751 Group, SH7751R Group Change in Delay Time Based on Load Capacitance Figure 23.75 is a chart showing the changes in the delay time (reference data) when a load capacitance equal to or larger than the stipulated value (30 pF) is connected to the LSI pins. When connecting an external device with a load capacitance exceeding the regulation, use the chart in figure 23.75 as reference for system design. Note that if the load capacitance to be connected exceeds the range shown in figure 23.75 the graph will not be a straight line. +4.0 ns Delay time +3.0 ns +2.0 ns +1.0 ns +0.0 ns +0 pF +25 pF +50 pF Load capacitance Figure 23.75 Load Capacitance−Delay Time Page 1082 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix A Address List Appendix A Address List Table A.1 Address List Area 7 1 Address* Power-On Size Reset Manual Reset Synchro Stand- nization Sleep by Clock Module Register P4 Address PCIC PCIMEM H'FD00 0000 H'FD00 0000 8, to to 16, H'FDFF FFFF H'FDFF FFFF 32 According to PCI memory space INTC INTPRI00 H'FE08 0000 H'0000 0000 Held Held Held Pck INTC INTREQ00 H'FE08 0020 H'1E08 0020 32 H'0000 0000 Held Held Held Pck INTC INTMSK00 H'FE08 0040 H'1E08 0040 32 H'0000 03FF Held Held Held Pck INTC INTMSKCLR H'FE08 0060 00 H'1E08 0060 32 Write-only CPG CLKSTP00 CPG CLKSTPCLR H'FE0A 0008 H'1E0A 0008 32 00 Write-only TMU TSTR2 H'FE10 0004 H'1E10 0004 8 H'00 Held Held Held Pck TMU TCOR3 H'FE10 0008 H'1E10 0008 32 H'FFFF FFFF Held Held Held Pck TMU TCNT3 H'FE10 000C H'1E10 000C 32 H'FFFF FFFF Held Held Held Pck TMU TCR3 H'FE10 0010 H'1E10 0010 16 H'0000 Held Held Held Pck TMU TCOR4 H'FE10 0014 H'1E10 0014 32 H'FFFF FFFF Held Held Held Pck TMU TCNT4 H'FE10 0018 H'1E10 0018 32 H'FFFF FFFF Held Held Held Pck TMU TCR4 H'FE10 001C H'1E10 001C 16 H'0000 Held Held Held Pck PCIC PCICONF0 H'FE20 0000 H'1E20 0000 32 H'35051054 (SH7751)/ H'350E1054 (SH7751R) Held Held Held Pck PCIC PCICONF1 H'FE20 0004 H'1E20 0004 32 H'02900080 Held Held Held Pck PCIC PCICONF2 H'FE20 0008 H'1E20 0008 32 Undefined Held Held Held Pck PCIC PCICONF3 H'FE20 000C H'1E20 000C 32 H'00000000 Held Held Held Pck PCIC PCICONF4 H'FE20 0010 H'1E20 0010 32 H'00000001 Held Held Held Pck PCIC PCICONF5 H'FE20 0014 H'1E20 0014 32 H'00000000 Held Held Held Pck 32 H'FE0A 0000 H'1E0A 0000 32 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 H'1E08 0000 H'0000 0000 Pck Pck Held Held Held Pck Pck Page 1083 of 1128 Appendix A Address List SH7751 Group, SH7751R Group Power-On Size Reset Manual Reset Synchro Stand- nization Sleep by Clock Module Register P4 Address Area 7 1 Address* PCIC PCICONF6 H'FE20 0018 H'1E20 0018 32 H'00000000 Held Held Held Pck PCIC PCICONF7 H'FE20 001C H'1E20 001C 32 H'00000000 Held Held Held Pck PCIC PCICONF8 H'FE20 0020 H'1E20 0020 32 H'00000000 Held Held Held Pck PCIC PCICONF9 H'FE20 0024 H'1E20 0024 32 H'00000000 Held Held Held Pck PCIC PCICONF10 H'FE20 0028 H'1E20 0028 32 H'00000000 Held Held Held Pck PCIC PCICON111 Undefined Held Held Held Pck PCIC PCICONF12 H'FE20 0030 H'1E20 0030 32 H'00000000 Held Held Held Pck PCIC PCICONF13 H'FE20 0034 H'1E20 0034 32 H'00000040 Held Held Held Pck PCIC PCICONF14 H'FE20 0038 H'1E20 0038 32 H'00000000 Held Held Held Pck PCIC PCICONF15 H'FE20 003C H'1E20 003C 32 H'00000100 Held Held Held Pck PCIC PCICONF16 H'FE20 0040 H'1E20 0040 32 H'00010001 Held Held Held Pck PCIC PCICONF17 H'FE20 0044 H'1E20 0044 32 H'00000000 Held Held Held Pck PCIC PCICR H'FE20 0100 H'1E20 0100 2 * 32 H'00000000 Held Held Held Pck PCIC PCILSR0 H'FE20 0104 H'1E20 0104 32 H'00000000 Held Held Held Pck PCIC PCILSR1 H'FE20 0108 H'1E20 0108 32 H'00000000 Held Held Held Pck PCIC PCILAR0 H'FE20 010C H'1E20 010C 32 H'00000000 Held Held Held Pck PCIC PCILAR1 H'FE20 0110 H'1E20 0110 32 H'00000000 Held Held Held Pck PCIC PCIINT H'FE20 0114 H'1E20 0114 32 H'00000000 Held Held Held Pck PCIC PCIINTM H'FE20 0118 H'1E20 0118 32 H'00000000 Held Held Held Pck PCIC PCIALR H'FE20 011C H'1E20 011C 32 Undefined Held Held Held Pck PCIC PCICLR H'FE20 0120 H'1E20 0120 32 Undefined Held Held Held Pck PCIC PCIAINT H'FE20 0130 H'1E20 0130 32 H'00000000 Held Held Held Pck PCIC PCIAINTM H'FE20 0134 H'1E20 0134 32 H'00000000 Held Held Held Pck PCIC PCIBLLR H'FE20 0138 H'1E20 0138 32 Undefined Held Held Held Pck PCIC PCIDMABT H'FE20 0140 H'1E20 0140 32 H'00000000 Held Held Held Pck PCIC PCIDPA0 H'FE20 0180 H'1E20 0180 32 H'00000000 Held Held Held Pck PCIC PCIDLA0 H'FE20 0184 H'1E20 0184 32 H'00000000 Held Held Held Pck PCIC PCIDTC0 H'FE20 0188 H'1E20 0188 32 H'00000000 Held Held Held Pck PCIC PCIDCR0 H'FE20 018C H'1E20 018C 32 H'00000000 Held Held Held Pck Page 1084 of 1128 H'FE20 002C H'1E20 002C 32 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix A Address List Power-On Size Reset Manual Reset Synchro Stand- nization Sleep by Clock Module Register P4 Address Area 7 1 Address* PCIC PCIDPA1 H'FE20 0190 H'1E20 0190 32 H'00000000 Held Held Held Pck PCIC PCIDLA1 H'FE20 0194 H'1E20 0194 32 H'00000000 Held Held Held Pck PCIC PCIDTC1 H'FE20 0198 H'1E20 0198 32 H'00000000 Held Held Held Pck PCIC PCIDCR1 H'FE20 019C H'1E20 019C 32 H'00000000 Held Held Held Pck PCIC PCIDPA2 H'FE20 01A0 H'1E20 01A0 32 H'00000000 Held Held Held Pck PCIC PCIDLA2 H'FE20 01A4 H'1E20 01A4 32 H'00000000 Held Held Held Pck PCIC PCIDTC2 H'FE20 01A8 H'1E20 01A8 32 H'00000000 Held Held Held Pck PCIC PCIDCR2 H'FE20 01AC H'1E20 01AC 32 H'00000000 Held Held Held Pck PCIC PCIDPA3 H'FE20 01B0 H'1E20 01B0 32 H'00000000 Held Held Held Pck PCIC PCIDLA3 H'FE20 01B4 H'1E20 01B4 32 H'00000000 Held Held Held Pck PCIC PCIDTC3 H'FE20 01B8 H'1E20 01B8 32 H'00000000 Held Held Held Pck PCIC PCIDCR3 H'FE20 01BC H'1E20 01BC 32 H'00000000 Held Held Held Pck PCIC PCIPAR H'FE20 01C0 H'1E20 01C0 32 Undefined Held Held Held Pck PCIC PCIMBR H'FE20 01C4 H'1E20 01C4 32 Undefined Held Held Held Pck PCIC PCIIOBR H'FE20 01C8 H'1E20 01C8 32 Undefined Held Held Held Pck PCIC PCIPINT H'FE20 01CC H'1E20 01CC 32 H'00000000 Held Held Held Pck PCIC PCIPINTM H'FE20 01D0 H'1E20 01D0 32 H'00000000 Held Held Held Pck PCIC PCICLKR H'FE20 01D4 H'1E20 01D4 32 H'00000000 Held Held Held Pck PCIC PCIBCR1 H'FE20 01E0 H'1E20 01E0 32 H'00000000 Held Held Held Pck PCIC PCIBCR2 H'FE20 01E4 H'1E20 01E4 32 H'00003FFC Held Held Held Pck PCIC PCIBCR3 H'FE20 01F8 H'1E20 01F8 32 H'0000 0001 Held Held Held Pck PCIC PCIWCR1 H'FE20 01E8 H'1E20 01E8 32 H'7777 7777 Held Held Held Pck PCIC PCIWCR2 H'FE20 01EC H'1E20 01EC 32 H'FFFE EFFF Held Held Held Pck PCIC PCIWCR3 H'FE20 01F0 H'1E20 01F0 H'0777 7777 Held Held Held Pck PCIC PCIMCR H'FE20 01F4 H'1E20 01F4 32 H'0000 0000 Held Held Held Pck PCIC PCIPCTR H'FE20 0200 H'1E20 0200 32 H'00000000 Held Held Held Pck PCIC PCIPDTR H'FE20 0204 H'1E20 0204 32 H'00000000 Held Held Held Pck PCIC PCIPDR H'FE20 0220 H'1E20 0220 32 Undefined Held Held Held Pck PCIC PCIIO H'FE24 0000 H'1E24 0000 8, to to 16, H'FE27 FFFF H'1E27 FFFF 32 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 32 According to PCI I/O space Pck Page 1085 of 1128 Appendix A Address List SH7751 Group, SH7751R Group Power-On Size Reset Manual Reset Synchro Stand- nization Sleep by Clock Module Register P4 Address Area 7 1 Address* CCN PTEH H'FF00 0000 H'1F00 0000 32 Undefined Undefined Held Held Ick CCN PTEL H'FF00 0004 H'1F00 0004 32 Undefined Undefined Held Held Ick CCN TTB H'FF00 0008 H'1F00 0008 32 Undefined Undefined Held Held Ick CCN TEA H'FF00 000C H'1F00 000C 32 Undefined Held Held Held Ick CCN MMUCR H'FF00 0010 H'1F00 0010 32 H'0000 0000 H'0000 0000 Held Held Ick CCN BASRA H'FF00 0014 H'1F00 0014 8 Undefined Held Held Held Ick CCN BASRB H'FF00 0018 H'1F00 0018 8 Undefined Held Held Held Ick CCN CCR H'FF00 001C H'1F00 001C 32 H'0000 0000 H'0000 0000 Held Held Ick CCN TRA H'FF00 0020 H'1F00 0020 32 Undefined Undefined Held Held Ick CCN EXPEVT H'FF00 0024 H'1F00 0024 32 H'0000 0000 H'0000 0020 Held Held Ick CCN INTEVT H'FF00 0028 H'1F00 0028 32 Undefined Undefined Held Held Ick CCN PTEA H'FF00 0034 H'1F00 0034 32 Undefined Undefined Held Held Ick CCN QACR0 H'FF00 0038 H'1F00 0038 32 Undefined Undefined Held Held Ick CCN QACR1 H'FF00 003C H'1F00 003C 32 Undefined Undefined Held Held Ick UBC BARA H'FF20 0000 H'1F20 0000 32 Undefined Held Held Held Ick UBC BAMRA H'FF20 0004 H'1F20 0004 8 Undefined Held Held Held Ick UBC BBRA H'FF20 0008 H'1F20 0008 16 H'0000 Held Held Held Ick UBC BARB H'FF20 000C H'1F20 000C 32 Undefined Held Held Held Ick UBC BAMRB H'FF20 0010 H'1F20 0010 8 Undefined Held Held Held Ick UBC BBRB H'FF20 0014 H'1F20 0014 16 H'0000 Held Held Held Ick UBC BDRB H'FF20 0018 H'1F20 0018 32 Undefined Held Held Held Ick UBC BDMRB H'FF20 001C H'1F20 001C 32 Undefined Held Held Held Ick Held Held Held Ick 2 UBC BRCR H'FF20 0020 H'1F20 0020 16 H'0000* BSC BCR1 H'FF80 0000 H'1F80 0000 32 H'0000 0000 Held Held Held Bck BSC BCR2 H'FF80 0004 H'1F80 0004 16 H'3FFC Held Held Held Bck BSC BCR3 H'FF80 0050 H'1F80 0050 16 H'0000 Held Held Held Bck BSC BCR4 H'FE0A 00F0 H'1E0A 00F0 32 H'0000 0000 Held Held Held Bck BSC WCR1 H'FF80 0008 H'7777 7777 Held Held Held Bck BSC WCR2 H'FF80 000C H'1F80 000C 32 H'FFFE EFFF Held Held Held Bck Page 1086 of 1128 H'1F80 0008 32 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix A Address List Power-On Size Reset Manual Reset Synchro Stand- nization Sleep by Clock Module Register P4 Address Area 7 1 Address* BSC WCR3 H'FF80 0010 H'1F80 0010 32 H'0777 7777 Held Held Held Bck BSC MCR H'FF80 0014 H'1F80 0014 32 H'0000 0000 Held Held Held Bck BSC PCR H'FF80 0018 H'1F80 0018 16 H'0000 Held Held Held Bck BSC RTCSR H'FF80 001C H'1F80 001C 16 H'0000 Held Held Held Bck BSC RTCNT H'FF80 0020 H'1F80 0020 16 H'0000 Held Held Held Bck BSC RTCOR H'FF80 0024 H'1F80 0024 16 H'0000 Held Held Held Bck BSC RFCR H'FF80 0028 H'1F80 0028 16 H'0000 Held Held Held Bck BSC PCTRA H'FF80 002C H'1F80 002C 32 H'0000 0000 Held Held Held Bck BSC PDTRA H'FF80 0030 H'1F80 0030 16 Undefined Held Held Held Bck BSC PCTRB H'FF80 0040 H'1F80 0040 32 H'0000 0000 Held Held Held Bck BSC PDTRB H'FF80 0044 H'1F80 0044 16 Undefined Held Held Held Bck BSC GPIOIC H'FF80 0048 H'1F80 0048 16 H'0000 0000 Held Held Held Bck BSC SDMR2 H'FF90 xxxx H'1F90 xxxx 8 Write-only BSC SDMR3 H'FF94 xxxx H'1F94 xxxx 8 DMAC SAR0 H'FFA0 0000 H'1FA0 0000 32 Undefined Undefined Held Held Bck DMAC DAR0 H'FFA0 0004 H'1FA0 0004 32 Undefined Undefined Held Held Bck DMAC DMATCR0 H'FFA0 0008 H'1FA0 0008 32 Undefined Undefined Held Held Bck DMAC CHCR0 H'FFA0 000C H'1FA0 000C 32 H'0000 0000 H'0000 0000 Held Held Bck DMAC SAR1 H'FFA0 0010 H'1FA0 0010 32 Undefined Undefined Held Held Bck DMAC DAR1 H'FFA0 0014 H'1FA0 0014 32 Undefined Undefined Held Held Bck DMAC DMATCR1 H'FFA0 0018 H'1FA0 0018 32 Undefined Undefined Held Held Bck DMAC CHCR1 H'FFA0 001C H'1FA0 001C 32 H'0000 0000 H'0000 0000 Held Held Bck DMAC SAR2 H'FFA0 0020 H'1FA0 0020 32 Undefined Undefined Held Held Bck DMAC DAR2 H'FFA0 0024 H'1FA0 0024 32 Undefined Undefined Held Held Bck DMAC DMATCR2 H'FFA0 0028 H'1FA0 0028 32 Undefined Undefined Held Held Bck DMAC CHCR2 H'FFA0 002C H'1FA0 002C 32 H'0000 0000 H'0000 0000 Held Held Bck DMAC SAR3 H'FFA0 0030 H'1FA0 0030 32 Undefined Undefined Held Held Bck DMAC DAR3 H'FFA0 0034 H'1FA0 0034 32 Undefined Undefined Held Held Bck DMAC DMATCR3 H'FFA0 0038 H'1FA0 0038 32 Undefined Undefined Held Held Bck DMAC CHCR3 H'FFA0 003C H'1FA0 003C 32 H'0000 0000 H'0000 0000 Held Held Bck DMAC DMAOR H'FFA0 0040 H'1FA0 0040 H'0000 0000 H'0000 0000 Held Held Bck R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 32 Bck Bck Page 1087 of 1128 Appendix A Address List SH7751 Group, SH7751R Group Area 7 1 Address* Power-On Size Reset Manual Reset Synchro Stand- nization Sleep by Clock Module Register P4 Address DMAC SAR4 H'FFA0 0050 H'1FA0 0050 32 Undefined Undefined Held Held Bck DMAC DAR4 H'FFA0 0054 H'1FA0 0054 32 Undefined Undefined Held Held Bck DMAC DMATCR4 H'FFA0 0058 H'1FA0 0058 32 Undefined Undefined Held Held Bck DMAC CHCR4 H'FFA0 005C H'1FA0 005C 32 H'0000 0000 H'0000 0000 Held Held Bck DMAC SAR5 H'FFA0 0060 H'1FA0 0060 32 Undefined Undefined Held Held Bck DMAC DAR5 H'FFA0 0064 H'1FA0 0064 32 Undefined Undefined Held Held Bck DMAC DMATCR5 H'FFA0 0068 H'1FA0 0068 32 Undefined Undefined Held Held Bck DMAC CHCR5 H'FFA0 006C H'1FA0 006C 32 H'0000 0000 H'0000 0000 Held Held Bck DMAC SAR6 H'FFA0 0070 H'1FA0 0070 32 Undefined Undefined Held Held Bck DMAC DAR6 H'FFA0 0074 H'1FA0 0074 32 Undefined Undefined Held Held Bck DMAC DMATCR6 H'FFA0 0078 H'1FA0 0078 32 Undefined Undefined Held Held Bck DMAC CHCR6 H'FFA0 007C H'1FA0 007C 32 H'0000 0000 H'0000 0000 Held Held Bck DMAC SAR7 H'FFA0 0080 H'1FA0 0080 32 Undefined Undefined Held Held Bck DMAC DAR7 H'FFA0 0084 H'1FA0 0084 32 Undefined Undefined Held Held Bck DMAC DMATCR7 H'FFA0 0088 H'1FA0 0088 32 Undefined Undefined Held Held Bck DMAC CHCR7 H'FFA0 008C H'1FA0 008C 32 H'0000 0000 H'0000 0000 Held Held Bck CPG FRQCR H'FFC0 0000 H'1FC0 0000 16 * Held Held Held Pck CPG STBCR H'FFC0 0004 H'1FC0 0004 8 H'00 Held Held Held Pck CPG WTCNT H'FFC0 0008 H'1FC0 0008 8/16 H'00 3 * Held Held Held Pck CPG WTCSR H'FFC0 000C H'1FC0 000C 8/16 H'00 3 * Held Held Held Pck CPG STBCR2 H'FFC0 0010 H'1FC0 0010 8 H'00 Held Held Held Pck RTC R64CNT H'FFC8 0000 H'1FC8 0000 8 Held Held Held Held Pck 2 RTC RSECCNT H'FFC8 0004 H'1FC8 0004 8 Held Held Held Held Pck RTC RMINCNT H'FFC8 0008 H'1FC8 0008 8 Held Held Held Held Pck RTC RHRCNT H'FFC8 000C H'1FC8 000C 8 Held Held Held Held Pck RTC RWKCNT H'FFC8 0010 H'1FC8 0010 8 Held Held Held Held Pck RTC RDAYCNT H'FFC8 0014 H'1FC8 0014 8 Held Held Held Held Pck RTC RMONCNT H'FFC8 0018 H'1FC8 0018 8 Held Held Held Held Pck RTC RYRCNT H'FFC8 001C H'1FC8 001C 16 Held Held Held Held Pck Page 1088 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix A Address List Area 7 1 Address* Power-On Size Reset Module Register P4 Address RTC H'FFC8 0020 H'1FC8 0020 8 RTC RTC RSECAR RMINAR RHRAR H'FFC8 0024 H'1FC8 0024 8 H'FFC8 0028 H'1FC8 0028 8 Manual Reset Synchro Stand- nization Sleep by Clock Held* 2 Held Held Held Pck Held* 2 Held Held Held Pck Held* 2 Held Held Held Pck RTC RWKAR H'FFC8 002C H'1FC8 002C 8 Held* 2 Held Held Held Pck RTC RDAYAR H'FFC8 0030 H'1FC8 0030 8 Held* 2 Held Held Held Pck Held* 2 Held RTC RTC RMONAR RCR1 H'FFC8 0034 H'1FC8 0034 8 H'FFC8 0038 H'1FC8 0038 8 H'00* 2 2 Held Held Pck H'00* 2 Held Held Pck H'00* 2 RTC RCR2 H'FFC8 003C H'1FC8 003C 8 H'09* Held Held Pck RTC RCR3 H'FFC8 0050 H'1FC8 0050 8 H'00 Held Held Held Pck RTC RYRAR H'FFC8 0054 H'1FC8 0054 16 Undefined Held Held Held Pck INTC ICR H'FFD0 0000 H'1FD0 0000 16 H'0000* Held Held Pck INTC IPRA H'FFD0 0004 H'1FD0 0004 16 H'0000 H'0000 Held Held Pck INTC IPRB H'FFD0 0008 H'1FD0 0008 16 H'0000 H'0000 Held Held Pck INTC IPRC H'FFD0 000C H'1FD0 000C 16 H'0000 H'0000 Held Held Pck INTC IPRD H'FFD0 0010 H'1FD0 0010 16 H'DA74 H'DA74 Held Held Pck TMU TOCR H'FFD8 0000 H'1FD8 0000 8 H'00 H'00 Held Held TMU TSTR H'FFD8 0004 H'1FD8 0004 8 H'00 TMU TCOR0 H'FFD8 0008 H'1FD8 0008 32 TMU TCNT0 TMU 2 H'0000* Pck 2 Held H'00* H'FFFF FFFF H'FFFF FFFF Held Held Pck H'FFD8 000C H'1FD8 000C 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck TCR0 H'FFD8 0010 H'1FD8 0010 16 H'0000 H'0000 Held Held Pck TMU TCOR1 H'FFD8 0014 H'1FD8 0014 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck TMU TCNT1 H'FFD8 0018 H'1FD8 0018 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck TMU TCR1 H'FFD8 001C H'1FD8 001C 16 H'0000 H'0000 Held Held Pck TMU TCOR2 H'FFD8 0020 H'1FD8 0020 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck TMU TCNT2 H'FFD8 0024 H'1FD8 0024 32 H'FFFF FFFF H'FFFF FFFF Held Held Pck TMU TCR2 H'FFD8 0028 H'1FD8 0028 16 H'0000 Held Held Pck R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 H'00 2 H'0000 Pck Page 1089 of 1128 Appendix A Address List SH7751 Group, SH7751R Group Area 7 1 Address* Power-On Size Reset Manual Reset Synchro Stand- nization Sleep by Clock Module Register P4 Address TMU TCPR2 H'FFD8 002C H'1FD8 002C 32 Held Held Held Held Pck SCI SCSMR1 H'FFE0 0000 H'1FE0 0000 H'00 H'00 Held H'00 Pck SCI SCBRR1 H'FFE0 0004 H'1FE0 0004 8 H'FF H'FF Held H'FF Pck SCI SCSCR1 H'FFE0 0008 H'1FE0 0008 8 H'00 H'00 Held H'00 Pck SCI SCTDR1 H'FFE0 000C H'1FE0 000C 8 H'FF H'FF Held H'FF Pck SCI SCSSR1 H'FFE0 0010 H'1FE0 0010 H'84 H'84 Held H'84 Pck SCI SCRDR1 H'FFE0 0014 H'1FE0 0014 8 H'00 H'00 Held H'00 Pck SCI SCSCMR1 H'FFE0 0018 H'1FE0 0018 8 H'00 H'00 Held H'00 Pck SCI SCSPTR1 H'FFE0 001C H'1FE0 001C 8 Held H'00* 8 8 H'00* 2 H'00* 2 2 Pck SCIF SCSMR2 H'FFE8 0000 H'1FE8 0000 16 H'0000 H'0000 Held Held Pck SCIF SCBRR2 H'FFE8 0004 H'1FE8 0004 8 H'FF H'FF Held Held Pck SCIF SCSCR2 H'FFE8 0008 H'1FE8 0008 16 H'0000 H'0000 Held Held Pck SCIF SCFTDR2 H'FFE8 000C H'1FE8 000C 8 Undefined Undefined Held Held Pck SCIF SCFSR2 H'FFE8 0010 H'1FE8 0010 16 H'0060 H'0060 Held Held Pck SCIF SCFRDR2 H'FFE8 0014 H'1FE8 0014 8 Undefined Undefined Held Held Pck SCIF SCFCR2 H'FFE8 0018 H'1FE8 0018 16 H'0000 H'0000 Held Held Pck SCIF SCFDR2 H'FFE8 001C H'1FE8 001C 16 H'0000 Held Held Pck H'0000 2 SCIF SCSPTR2 H'FFE8 0020 H'1FE8 0020 16 H'0000* SCIF SCLSR2 H'FFE8 0024 H'1FE8 0024 16 H'0000 H-UDI SDIR H'FFF0 0000 16 H'FFFF* H'1FF0 0000 2 H'0000* 2 Held Held Pck H'0000 Held Held Pck Held Held Held Pck H-UDI SDDR H'FFF0 0008 H'1FF0 0008 32 Held Held Held Held Pck Hi-UDI SDINT H'FFF0 0014 H'1FF0 0014 16 H'0000 Held Held Held Pck Notes: 1. With control registers, the above addresses in the physical page number field can be accessed by means of a TLB setting. When these addresses are set directly without using the TLB, operations are limited. 2. Includes undefined bits. See the descriptions of the individual modules. 3. Use word-size access when writing. Perform the write with the upper byte set to H'5A or H'A5, respectively. Byte- and longword-size writes cannot be used. Use byte-size access when reading. Page 1090 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix B Package Dimensions Appendix B Package Dimensions The package dimention that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-HQFP256-28x28-0.40 RENESAS Code PRQP0256LA-B Previous Code FP-256G/FP-256GV MASS[Typ.] 5.4g HD *1 D 192 129 193 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 128 HE b1 c c1 *2 E bp ZE Reference Symbol 65 256 1 Terminal cross section 64 ZD c A2 A F θ L A1 e *3 y bp x L1 M Detail F D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 28 28 3.20 30.4 30.6 30.8 30.4 30.6 30.8 3.95 0.25 0.40 0.50 0.13 0.18 0.23 0.16 0.12 0.17 0.22 0.15 0° 8° 0.4 0.11 0.08 1.40 1.40 0.3 0.5 0.7 1.3 Figure B.1 Package Dimensions (256-pin QFP) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1091 of 1128 Appendix B Package Dimensions JEITA Package Code P-BGA256-27x27-1.27 SH7751 Group, SH7751R Group RENESAS Code PRBG0256DE-B Previous Code BP-256A/BP-256AV MASS[Typ.] 3.0g D A E B ×4 v y1 S y A1 A S S SD e e Y W V U T Reference Symbol R P SE N M L Dimension in Millimeters Min Nom D 27.0 E 27.0 0.20 v K Max w J H A G A1 F 2.5 0.5 e E 0.6 0.7 1.27 0.60 0.75 0.90 D b C x 0.30 B y 0.20 A y1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 φ b φ× M S A B φ0.10 M S 0.35 SD 0.635 SE 0.635 ZD ZE Figure B.2 Package Dimensions (256-pin BGA: Devices Other than HD6417751RBA240HV) Page 1092 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group JEITA Package Code P-FBGA292-17x17-0.80 Appendix B Package Dimensions RENESAS Code PRBG0292GA-A MASS[Typ.] 0.9g Previous Code — E w S A D w S B 4× v y1 S y A1 A S S e ZE B SE e Y W V U T R Reference Symbol P A N Dimension in Millimeters Min Nom D 17.00 K E 17.00 J v M SD L H G F Max 0.15 w 0.20 A 2.00 E A1 D ZD C B b A 1 2 3 4 5 6 7 8 0.35 0.40 0.45 0.80 e 0.45 0.50 0.55 x 0.08 y 0.10 9 10 11 12 13 14 15 16 17 18 19 20 φ b φ ×M S A B y1 0.20 SD 0.40 SE 0.40 ZD 0.9 ZE 0.9 Figure B.3 Package Dimensions (292-pin BGA) R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1093 of 1128 Appendix B Package Dimensions RENESAS Code PRBG0256DM-A Previous Code ⎯ MASS[Typ.] 2.8g w S B JEITA Package Code P-BGA256-27x27-1.27 SH7751 Group, SH7751R Group D w S A ×4 y1 S E E1 D1 v e φb A A1 S y S φ× M S A B Y W V U T R P B N M Dimension in Millimeters L K Reference Symbol J D 27.0 G E 27.0 F v 0.20 E D w 0.30 C A Min Nom Max e H ZE B A1 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A ZD 2.6 0.50 e b 0.60 0.70 1.27 0.65 0.75 0.85 x 0.15 y 0.20 y1 0.35 ZD 1.435 ZE 1.435 D1 24.0 E1 24.0 Figure B.4 Package Dimensions (256-pin BGA: HD6417751RBA240HV) Page 1094 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix C Mode Pin Settings Appendix C Mode Pin Settings The MD10–MD0 pin values are input in the event of a power-on reset via the RESET pin. Clock Modes Table C.1 Clock Operating Modes (SH7751) External Pin Combination Clock Operating Mode MD2 MD1 0 0 0 1 1 2 3 4 1 0 5 6 1 Frequency (vs. Input Clock) MD0 1/2 Frequency Divider PLL2 CPU Clock Bus Clock Peripheral Module Clock PLL1 FRQCR Initial Value 0 Off On On 6 3/2 3/2 H'0E1A 1 Off On On 6 1 1 H'0E23 0 On On On 3 1 1/2 H'0E13 1 Off On On 6 2 1 H'0E13 0 On On On 3 3/2 3/4 H'0E0A 1 Off On On 6 3 3/2 H'0E0A 0 Off Off Off 1 1/2 1/2 H'0808 Notes: 1. The multiplication factor of 1/2 frequency divider is solely determined by the clock operating mode. 2. For the ranges input clock frequency, see the description of the EXTAL clock input frequency (fEX) and the CKIO clock output (fOP) in section 23.3.1, Clock and Control Signal Timing. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1095 of 1128 Appendix C Mode Pin Settings Table C.2 SH7751 Group, SH7751R Group Clock Operating Modes (SH7751R) External Pin Combination Frequency (vs. Input Clock) Clock Operating Mode MD2 MD1 MD0 PLL1 PLL2 CPU Clock Bus Clock Peripheral Module Clock FRQCR Initial Value 0 0 0 0 On (×12) On 12 3 3 H'0E1A 1 On (×12) On 12 3/2 3/2 H'0E2C 1 0 On (×6) On 6 2 1 H'0E13 1 On (×12) On 12 4 2 H'0E13 0 0 On (×6) On 6 3 3/2 H'0E0A 1 On (×12) On 12 6 3 H'0E0A 0 OFF (×6) OFF 1 1/2 1/2 H'0808 1 2 3 4 1 5 6 1 Notes: 1. The multiplication factor of PLL1 is solely determined by the clock operating mode. 2. For the ranges input clock frequency, see the description of the EXTAL clock input frequency (fEX) and the CKIO clock output (fOP) in section 23.3.1, Clock and Control Signal Timing. Table C.3 Area 0 Memory Map and Bus Width Pin Value MD6 MD4 MD3 Memory Type Bus Width 0 0 0 Reserved (Cannot be used) Reserved (Cannot be used) 1 Reserved (Cannot be used) Reserved (Cannot be used) 0 Reserved (Cannot be used) Reserved (Cannot be used) 1 MPX interface 32 bits 0 Reserved (Cannot be used) Reserved (Cannot be used) 1 SRAM interface 8 bits 0 SRAM interface 16 bits 1 SRAM interface 32 bits 1 1 0 1 Table C.4 Endian Pin Value MD5 Endian 0 Big endian 1 Little endian Page 1096 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Table C.5 Appendix C Mode Pin Settings Master/Slave Pin Value MD7 Master/Slave 0 Slave 1 Master Table C.6 Clock Input Pin Value MD8 Clock Input 0 External input clock 1 Crystal resonator Table C.7 PCI Mode Pin Value Mode MD10 MD9 Mode 0 0 0 PCI host with external clock input 1 0 1 PCI host with feedback input clock from CKIO 2 1 0 PCI non-host with external clock input 3 1 1 PCI disabled Note: When exiting standby mode or hardware standby mode using a power-on reset, do not change the PCI mode. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1097 of 1128 Appendix C Mode Pin Settings Page 1098 of 1128 SH7751 Group, SH7751R Group R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix D Pin Functions Appendix D Pin Functions D.1 Pin States Table D.1 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable, Disable Common) Reset (Power-On) Reset (Manual) Pin Name I/O Master Slave Master Slave D0–D31 I/O Z Z* 14 Z 13 14 Z* 7 13 Bus Standby Released 14 Z* 14 Z 13 Z* 13 5 Hardware Standby Notes A2–A17, A0–A25 O Z Z Z* O* Z* Z* O* Z* Z RESET I I I I I I I I BACK/BSREQ O H H H O Z BREQ/BSACK BS I O PI H PI PZ H 12 I* H 12 I* 13 H Z* 4 CKE O H H O* H CS6–CS0 O H PZ H Z* RAS O H PZ O* RD/CASS/FRAME RD/WR RDY CAS3/DQM3 CAS2/DQM2 O O I O O H PZ H PZ PI H PI PZ H PZ 4 4 O* I* 4 O* 4 O* CAS1/DQM1 O H PZ O* CAS0/DQM0 O H PZ O* WE3/IOICWR WE2/IOICRD WE1 WE0/REG DACK1–DACK0 MD7/CTS2 O O O O O I/O H PZ H PZ H PZ H PZ L L 17 I* I* 17 I* MD6/IOIS16 I I* MD5 I I* R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 I* 17 12 I* O* 4 O* 4 O* I* 17 12 I* 17 Z* 13 Z* Z 4 Z 13 Z O* 13 5 Z* Z* O* 13 3 Z* O* 13 3 Z 13 3 Z* O* 13 3 Z* O* Z 13 5 13 Z Z* H* 12 Z* 12 I* I* I 13 3 Z* O* 13 3 Z* O* Z 13 13 3 Z* O* 13 3 Z* O* Z 13 13 3 Z* O* 13 3 Z* O* Z 13 Z* O* 13 3 Z* O* 13 3 Z 13 13 3 Z* O* 13 3 Z* O* Z 13 13 3 Z* O* 13 3 Z* O* Z 13 13 3 Z* O* 13 3 Z* O* Z 13 13 3 13 3 Z* O* Z 11 6 O Z* Z* Z* Z* Z* Z* L 11 I 13 13 Z* L 17 Z Z* 4 Z* H* 13 Z* 4 O* 5 L 4 4 I 13 Z* H* Z* 12 I* 13 13 H 12 Z* O* Z* O* 11 I* 12 I* 13 Z* 11 6 I* O* 12 I* 13 Z* Z DMAC 11 Z SCIF 12 I PCMCIA (I/O) I* O I* 13 Z* Z Page 1099 of 1128 Appendix D Pin Functions SH7751 Group, SH7751R Group Reset (Power-On) Pin Name MD4/CE2B MD3/CE2A I/O Master Slave 1 I/O* 2 I/O* 17 I* 17 I* 17 I* 17 I* Reset (Manual) Master Slave 13 Z* H 13 Z* H 8 Bus Standby Released 13 Z* H* 13 5 13 13 5 Z* Z* 13 Z* 13 Z* H* 8 Z* 8 8 Hardware Standby Notes Z PCMCIA Z PCMCIA CKIO O O O ZO* ZO* ZO* ZO* Z STATUS1– STATUS0 O O O O O O O ZO* IRL3–IRL0 I PI PI I* NMI DREQ1–DREQ0 DRAK1–DRAK0 I I O PI PI L PI PI L 17 12 12 I* 11 I* L 17 RXD I PI PI I* I/O I* MD2/RXD2 TxD I I/O 17 17 I* PI 17 17 I* 17 I* PI 17 11 I* 11 Z* 11 I* 11 Z* O 12 I* 12 I INTC 12 I INTC 11 I* I DMAC O I* 12 I* I* 11 I* 11 6 Z* O* I* I* MD1/TXD2 I* 11 I* PI 11 I* I* PI I* L I/O I/O 12 11 MD0/SCK2 SCK 12 I* 9 Z DMAC I SCIF 11 I SCI 11 Z SCI Z SCIF I* I SCIF O I* Z* O I* O 6 * 11 I* 11 I* 11 Z* 11 I* 11 Z* O 11 I* 11 11 11 11 11 11 I* 11 11 I* Z* O I* O 6 * 11 6 11 Z* O* Z* O 11 11 I* 11 6 Z* O* 11 11 6 Z SCI 11 11 11 I* Z O* I* O 11 MD8/RTS2 I/O I* I* I* Z SCIF TCLK I/O PI PI I* I* I* O I* O Z TMU TDO O O O O O O O Z H-UDI TMS I PI PI PI PI PI PI I H-UDI TCK I PI PI PI PI PI PI I H-UDI TDI I PI PI PI PI PI PI I H-UDI TRST I PI PI PI PI PI PI I H-UDI MRESET I PI PI PI PI PI PI I 11 SLEEP I PI PI I* I* I* I* I CA I I I I I I I I Page 1100 of 1128 12 12 12 12 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Table D.2 Appendix D Pin Functions Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable) Reset (Power On) Host NonHost Reset (Manual) Standby NonHost NonHost Host Hardware Standby Notes I/O AD31–AD31 I/O L Z IOZ IOZ K Z L Z Z CBE3–CBE0 I/O L Z IOZ IOZ K Z L Z Z I/O L Z IOZ SERR I/O PZ PZ IOZ* IOZ K Z Host NonHost Pin Name PAR Host Reset (Software) L Z Z 1 IOZ* 10 Z* 10 Z* 10 PZ PZ Z 1 IOZ* 10 Z* 10 Z* 10 PZ PZ Z Z* 10 Z* 10 PZ PZ Z Z* 10 Z* 10 PZ PZ Z 0 PERR I/O PZ PZ IOZ* 0 PCILOCK PCISTOP I/O I/O PZ PZ PZ PZ IZ* 10 IOZ* IZ* 10 1 IOZ* 10 1 IOZ* 10 Z* 10 Z* 10 PZ PZ Z 1 IOZ* 10 Z* 10 Z* 10 PZ PZ Z 1 IOZ* 10 Z* 10 Z* 10 PZ PZ Z 1 IOZ* 10 Z* 10 Z* 10 PZ PZ Z 10 PI PZ Z 10, 16 (IO* * ) Values in parenthesis are when using PORT 10 PI PZ Z 10, 16 (IO* * ) Values in parenthesis are when using PORT 0 DEVSEL I/O PZ PZ IOZ* 0 TRDY I/O PZ PZ IOZ* 0 IRDY I/O PZ PZ IOZ* 0 PCIFRAME I/O PZ PZ IOZ* 0 PCIREQ4 I/O PI PCIREQ2/ MD9 I/O I* 17 PZ Z* 10 Z* 11, 16 (IO* * ) 17 Z* 10 Z* 11, 16 (IO* * ) I* R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 10 I* 10 Z* 10, 16 (IO* * ) 10 I* 10 Z* 10, 16 (IO* * ) Page 1101 of 1128 Appendix D Pin Functions SH7751 Group, SH7751R Group Reset (Power On) NonHost Pin Name I/O Host PCIREQ3/ MD10 I/O I* PCIREQ1/ I PI PI I* PCIGNT4– PCIGNT2 O Z Z PCIGNT1/ REQOUT O Z Z 17 I* 17 Reset (Manual) Standby NonHost NonHost Host 10 10 Z* 10, 16 (IO* * ) 10 I* 10 I* O Z (K) K O O K 10 10 Host I* Z* Z* 11, 16 (IO* * ) I* 10 Reset (Software) Host NonHost Hardware Standby Notes PI PZ Z 10, 16 (IO* * ) PI PI Z Z (K) Z Z (K) Z K Z H Z 10 Values in parenthesis are when using PORT GNTIN PCICLK I I I I I I I I I Z PCIRST O L L K K K K L L Z IDSEL I PI I PI I PI I PI I Z INTA O PZ PZ ODK 10 * ODK 10 * ODK 10 * ODK 10 * PZ PZ Z Page 1102 of 1128 Values in parenthesis are when using PORT R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Table D.3 Appendix D Pin Functions Pin States in Reset, Power-Down State, and Bus-Released State (PCI Disable) Reset (Power-On) Reset (Manual) Hardware Bus Released Standby Notes Pin Name I/O Master Slave Master Slave Standby AD31–AD0 I/O Z Z Z (K) Z (K) Z* (K) Z* (K) Z CBE3–CBE0 — Z Z Z Z Z Z Z PAR O Z Z Z Z Z Z Z SERR — Z Z Z Z Z Z Z PERR — Z Z Z Z Z Z Z PCILOCK — Z Z Z Z Z Z Z PCISTOP — Z Z Z Z Z Z Z DEVSEL — Z Z Z Z Z Z Z 15 15 TRDY — Z Z Z Z Z Z Z IRDY — Z Z Z Z Z Z Z PCIFRAME — Z Z Z Z Z Z Z PCIREQ4 — Z PCIREQ2/MD9 I/O Z 17 I* Z Z Z Z Z 17 Z Z Z Z Z 17 I* PCIREQ3/MD10 I/O I* I* Z Z Z Z Z PCIREQ1 — Z Z Z Z Z Z Z PCIGNT4–PCIGNT2 O Z Z Z Z Z Z Z 17 PCIGNT1 O Z Z Z Z Z Z Z PCICLK — Z Z Z Z Z Z Z PCIRST O Z Z Z Z Z Z Z IDSEL — Z Z Z Z Z Z Z INTA — Z Z Z Z Z Z Z Values in parenthesis are when using PORT Legend: I: Input O: Output H: High-level output R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1103 of 1128 Appendix D Pin Functions L: Z: K: IZ/IOZ: PZ: PI: ODK: Low-level output High-impedance Output state held Response to access from PCI Pulled up with a built-in pull-up resistance Input pulled up with a built-in pull-up resistance Open-drain output state held Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14 15. 16. 17. D.2 SH7751 Group, SH7751R Group Output when area 5 PCMCIA is used. Output when area 6 PCMCIA is used. Z (I) or O (refresh), depending on register setting (BCR1.HIZCNT). Depends on refresh operation. Z (I) or H (state held), depending on register setting (BCR1.HIZMEM). Z or O, depending on register setting (STBCR.PHZ). Output when refreshing is set. Z or O, depending on register setting (FRQCR.CKOEN). Z or O, depending on register setting (STBCR.STHZ). Pullup, depending on register setting (PCICR.PCIPUP). Pullup, depending on register setting (STBCR.PPU). Pullup, depending on register setting (BCR1.IPUP). Pullup, depending on register setting (BCR1.OPUP). Pullup, depending on register setting (BCR1.DPUP). Pullup, depending on register setting (BCR2.PORTEN). Pullup, depending on register setting (PCIPCTR.PB2PUP to PCIPCTR.PB4PUP). Pullup by on-chip pullup resistor. Note that this cannot be used for pullup of the mode pin during a power-on reset. Pullup or pulldown should be performed externally to this LSI. Handling of Unused Pins • When RTC is not used ⎯ EXTAL2: Pull up to 3.3 V ⎯ XTAL2: Leave unconnected ⎯ VDD-RTC: Power supply ⎯ VSS-RTC: Power supply • When PLL1 is not used ⎯ VDD-PLL1: Power supply ⎯ VSS-PLL1: Power supply Page 1104 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix D Pin Functions • When PLL2 is not used ⎯ VDD-PLL2: Power supply ⎯ VSS-PLL2: Power supply • When on-chip crystal oscillator is not used ⎯ XTAL: Leave unconnected ⎯ VDD-CPG: Power supply ⎯ VSS-CPG: Power supply Table D.4 Handling of Pins When PCI Is Not Used Pin Name I/O Handling AD31–AD0 I/O Pull up to 3.3 V* CBE3–CBE0 I/O Pull up to 3.3 V PAR I/O Pull up to 3.3 V SERR I/O Pull up to 3.3 V PERR I/O Pull up to 3.3 V PCILOCK I/O Pull up to 3.3 V PCISTOP I/O Pull up to 3.3 V DEVSEL I/O Pull up to 3.3 V TRDY I/O Pull up to 3.3 V IRDY I/O Pull up to 3.3 V PCIFRAME I/O Pull up to 3.3 V PCIREQ4–PCIREQ2 I/O Pull up to 3.3 V PCIREQ1 I Pull up to 3.3 V PCIGNT4–PCIGNT2 O Pull up to 3.3 V PCIGNT1 O Pull up to 3.3 V PCICLK I Pull up to 3.3 V PCIRST O Leave unconnected IDSEL I Pull down to low level when IDSEL is not in use O Leave unconnected INTA Note: D.3 * When not used as a general-purpose I/O port. Note on Pin Processing To prevent unwanted effects on other pins when using external pull-up or pull-down resistors, use independent pull-up or pull-down resistors for individual pins. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1105 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group, SH7751R Group Page 1106 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix E Synchronous DRAM Address Multiplexing Tables Appendix E Synchronous DRAM Address Multiplexing Tables (1) BUS 32 AMX 0 (16M: 512k × 16b × 2) × 2 * AMXEXT 0 16M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 4MB Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1107 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables (2) BUS 32 AMX 0 (16M: 512k × 16b × 2) × 2 * AMXEXT 1 16M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle SH7751 Group, SH7751R Group 4MB Synchronous DRAM Address Pins Function A14 A13 A20 A20 A11 BANK selects bank address A12 A21 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Page 1108 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group (3) BUS 32 AMX 1 Appendix E Synchronous DRAM Address Multiplexing Tables (16M: 1M × 8b × 2) × 4 * AMXEXT 0 16M, column-addr-9bit LSI Address Pins RAS Cycle CAS Cycle 8MB Synchronous DRAM Address Pins Function A14 A13 A22 A22 A11 BANK selects bank address A12 A21 H/L A10 Address precharge setting A11 A20 0 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1109 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables (4) BUS 32 AMX 1 (16M: 1M × 8b × 2) × 4 * AMXEXT 1 16M, column-addr-9bit LSI Address Pins RAS Cycle CAS Cycle SH7751 Group, SH7751R Group 8MB Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A22 H/L A10 Address precharge setting A11 A20 0 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used Page 1110 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group (5) BUS 32 AMX 2 Appendix E Synchronous DRAM Address Multiplexing Tables (64M: 1M × 16b × 4) × 2 * 64M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 16MB Synchronous DRAM Address Pins Function A16 A15 A23 A23 A13 A14 A22 A22 A12 A13 A21 0 A11 A12 A20 H/L A10 A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 BANK selects bank address Address precharge setting Address Page 1111 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables (6) BUS 32 AMX 3 (64M: 2M × 8b × 4) × 4 * 64M, column-addr-9bit LSI Address Pins RAS Cycle CAS Cycle SH7751 Group, SH7751R Group 32MB Synchronous DRAM Address Pins Function A16 A15 A24 A24 A13 A14 A23 A23 A12 A13 A22 0 A11 A12 A21 H/L A10 A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used Page 1112 of 1128 BANK selects bank address Address precharge setting Address R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group (7) BUS 32 AMX 4 Appendix E Synchronous DRAM Address Multiplexing Tables (64M: 512k × 32b × 4) × 1 * 64M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 8MB Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 A13 A21 A21 A11 A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 BANK selects bank address Page 1113 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables (8) BUS 32 AMX 5 (64M: 1M × 32b × 2) × 1 * 64M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle SH7751 Group, SH7751R Group 8MB Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 A13 A21 0 A11 A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Page 1114 of 1128 BANK selects bank address R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group (9) BUS 32 AMX 6 Appendix E Synchronous DRAM Address Multiplexing Tables (64M: 4M × 4b × 4) × 8 * (128M: 4M × 8b × 4) × 4 * 64M, column-addr-10bit LSI Address Pins RAS Cycle CAS Cycle 64MB Synchronous DRAM Address Pins Function A15 A25 A25 A13 A14 A24 A24 A12 A13 A23 0 A11 A12 A22 H/L A10 Address precharge setting A11 A21 A11 A9 Address A10 A20 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12 A2 A0 A1 Not used A0 Not used R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 BANK selects bank address Page 1115 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group, SH7751R Group (10) BUS 32 AMX 6 64MB (256M: 4M × 16b × 4) × 2 * AMXEXT1 256M, column-addr-9bit LSI Address Pins RAS Cycle CAS Cycle Synchronous DRAM Address Pins Function A16 A25 A25 A14 A15 A24 A24 A13 A14 A23 0 A12 A13 A22 0 A11 A12 A21 H/L A10 Address precharge setting A11 A20 0 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used Page 1116 of 1128 BANK selects bank address R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group (11) BUS 32 AMX 7 Appendix E Synchronous DRAM Address Multiplexing Tables (16M: 256k × 32b × 2) × 1 * 16M, column-addr-8bit LSI Address Pins RAS Cycle CAS Cycle 2MB Synchronous DRAM Address Pins Function A13 A12 A20 A20 A10 BANK selects bank address A11 A19 H/L A9 Address precharge setting A10 A18 0 A8 Address A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Note: * Example configurations of synchronous DRAM R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1117 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group, SH7751R Group Page 1118 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix F Instruction Prefetching and Its Side Effects Appendix F Instruction Prefetching and Its Side Effects The SH7751 Group is provided with an internal buffer for holding pre-read instructions, and always performs pre-reading. Therefore, program code must not be located in the last 20-byte area of any memory space. If program code is located in these areas, the memory area will be exceeded and a bus access for instruction pre-reading may be initiated. A case in which this is a problem is shown below. Address H'03FFFFF8 H'03FFFFFA Area 0 H'03FFFFFC H'03FFFFFE Area 1 H'04000000 H'04000002 . . . . . ADD R1,R4 JMP @R2 NOP NOP PC (program counter) Instruction prefetch address Figure F.1 Instruction Prefetch Figure F.1 presupposes a case in which the instruction (ADD) indicated by the program counter (PC) and the address H'04000002 instruction prefetch are executed simultaneously. It is also assumed that the program branches to an area other than area 1 after executing the following JMP instruction and delay slot instruction. In this case, the program flow is unpredictable, and a bus access (instruction prefetch) to area 1 may be initiated. Instruction Prefetch Side Effects 1. It is possible that an external bus access caused by an instruction prefetch may result in misoperation of an external device, such as a FIFO, connected to the area concerned. 2. If there is no device to reply to an external bus request caused by an instruction prefetch, hangup will occur. Remedies 1. These illegal instruction fetches can be avoided by using the MMU. 2. The problem can be avoided by not locating program code in the last 20 bytes of any area. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1119 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group, SH7751R Group Page 1120 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix G Power-On and Power-Off Procedures Appendix G Power-On and Power-Off Procedures G.1 Power-On Stipulations 1. Supply power to power supply VDDQ and to I/O, RTC, CPG, PLL1, and PLL2 simultaneously. 2. Perform input to the signal lines (RESET, MRESET, MD0 to MD10, external clock, etc.) after or at the same time power is supplied to VDDQ. Applying input to signal lines before power is supplied to VDDQ could damage the product. ⎯ Drive the RESET signal low when power is first supplied to VDDQ. 3. Apply power such that the voltage of power supply VDD is less than 1.2 V until the voltage of power supply VDDQ reaches 2 V. Note that the on-chip PLL circuit (PLL2) may not operate correctly if this condition is not met. 4. It is recommended to apply power first to power supply VDDQ and then to power supply VDD. 5. In addition to 1., 2., 3., and 4. above, also observe the stipulations in G.3. Furthermore: ⎯ There are no time restrictions on the power-on sequence for power supply VDDQ and power supply VDD with regard to the LSI alone. Refer to figure G.1. Nevertheless, it is recommended that the power-on sequence be completed in as short a time as possible. ⎯ When the LSI is mounted on a board and connected to other elements, ensure that –0.3 V < Vin < VDDQ + 0.3 V. In addition, the time limit for the rise of either power supply VDDQ or power supply VDD from VDDQ ≥ 1.0 V or VDD ≥ 0.5 V, respectively, to above the minimum values in the LSI’s guaranteed operation voltage range (VDDQ (min.) and VDD (min.)) is 100 ms (max.), as shown in figure G.2. The product may be damaged if this time limit is exceeded. It is recommended that the power-on sequence be completed in as short a time as possible. G.2 Power-Off Stipulations 1. Power off power supply VDDQ and I/O, RTC, CPG, PLL1, and PLL2 simultaneously. 2. There are no timing restrictions for the RESET and MRESET signal lines at power-off. 3. Cut off the input signal level for signal lines other than RESET and MRESET in the same sequence as power supply VDDQ. 4. It is recommended to first power off power supply VDD and then power supply VDDQ. 5. In addition to 1., 2., 3., and 4. above, also observe the stipulations in G.3. Furthermore: ⎯ There are no time restrictions on the power-off sequence for power supply VDDQ and power supply VDD with regard to the LSI alone. Refer to figure G.2. Nevertheless, it is recommended that the power-off sequence be completed in as short a time as possible. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1121 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group, SH7751R Group ⎯ When the LSI is mounted on a board and connected to other elements, ensure that –0.3 V < Vin < VDDQ + 0.3 V. In addition, the time limit for the fall of power supply VDDQ and power supply VDD from the minimum values in the LSI’s guaranteed operation voltage range (VDDQ (min.) and VDD (min.)) to VDDQ ≥ 1.0 V or VDD ≥ 0.5 V, respectively, is 150 ms (max.), as shown in figure G.3. The product may be damaged if this time limit is exceeded. It is recommended that the power-off sequence be completed in as short a time as possible. Notes: 1. Note on Power-On If the below conditions (A) are not met during power-on, PLL2 may not oscillate correctly and CKIO may not be output properly. Conditions (A): VDDQ (VDDQ, VDD-CPG, VDD-RTC) is 2.0 V or above when VDD ( VDD, VDD-PLL1, VDD-PLL2) is 1.2 V or above. 2. Workarounds Any of methods (1) to (3) below may be used to avoid the problem by stopping PLL2 oscillation temporarily. (1) As shown in figure G.1, select mode 6*1 immediately after power-on, select the desired clock mode once the above conditions (A) are satisfied, and cancel the power-on reset. (2) After starting with clock operation mode 6*1 selected, change FRQCR to specify the desired frequency clock. Note: It is not possible to use frequency divider 1 when this method is employed. (3) Temporarily stop PLL2 by writing 0 to FRQCR.PLL2EN. After maintaining FRQCR.PLL2EN as 0 for 1 µs or more, write 1 to FRQCR.PLL2EN to restart PLL2. Note: If this method is used, the clock output from CKIO cannot be guaranteed until the above operations are completed. If abnormal signal output is produced, the frequency is higher than normal. Therefore, it is possible that unwanted noise may be generated from the clock line or, if the LSI’s CKIO pin is used to supply a clock to another device, the clock may not be supplied correctly to the external device. When using this method, it is recommended that sufficient verification testing be performed on the actual system. Page 1122 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix G Power-On and Power-Off Procedures RESET MD2−0 Mode 6 *1 *2 Min. 0s 3.3 V 2.0 V VDDQ VDD 1.2 V Period when conditions (A) not satisfied Figure G.1 Method for Temporarily Selecting Clock Operation Mode 6 Notes: 1. Clock operation mode 6 (I) SH7751 (1) External pin combination: MD0 = low, MD1 = high, MD2 = high (2) Frequency dividers 1 and 2 = off, PLL1 = off, PLL2 = off (3) Frequencies (relative to input clock): CPU clock = 1 Bus clock = 1/2 Peripheral module clock = 1/2 (4) Input clock frequency range = 1 to 66.7 MHz (II) SH7751R (1) External pin combination: MD0 = low, MD1 = high, MD2 = high (2) PLL1 = off (×6), PLL2 = off (3) Frequencies (relative to input clock): CPU clock = 1 Bus clock = 1/2 Peripheral module clock = 1/2 (4) Input clock frequency range = 1 to 34 MHz 2. Input to the MD should be high-level and follow the voltage level of the I/O, PLL, RTC, and CPG power supplies. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1123 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables G.3 SH7751 Group, SH7751R Group Common Stipulations for Power-On and Power-Off 1. Always ensure that VDDQ = VDD-CPG = VDD-RTC = VDD-PLL1/2. Refer to 9.9.5, Hardware Standby Mode Timing, regarding VDD-RTC in hardware standby mode. 2. Ensure that –0.3 V < VDD < VDDQ + 0.3 V. 3. Ensure that VSS = VSSQ = VSS-PLL1/2 = VSS-CPG = VSS-RTC = GND (0 V). The product may be damaged if conditions 1., 2., and 3. above are not satisfied. [V] Power supply VDDQ Power-on Power-off Power supply VDD 0.3 V (max) 0.3 V (max) GND [t] Figure G.2 Power-On Procedure 1 [V] Power supply VDDQ Power-on Power-off VDDQ (min) 2.0 V Power supply VDD VDD (min) 1.2 V 1.0 V 0.5 V GND tpwu tpwd tpwu < 100 ms (max) tpwd < 150 ms (max) Unstable period at power-on: tpwu Normal operation period [t] Unstable period at power-off: tpwd Figure G.3 Power-On Procedure 2 Page 1124 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix H Product Lineup Appendix H Product Lineup Table H.1 SH7751/SH7751R Product Lineup Product Name Operating Operating Voltage Frequency Temperature*1 Part Number*2 Package SH7751 1.8 V HD6417751BP167 (V) 256-pin BGA HD6417751F167 (V) 256-pin QFP SH7751R 1.5 V 167 MHz 240 MHz –20 to 75°C –20 to 75°C HD6417751RBP240 (V) 256-pin BGA HD6417751RF240 (V) 256-pin QFP HD6417751RBG240 (V) 292-pin BGA 200 MHz HD6417751RBP200 (V) 256-pin BGA HD6417751RF200 (V) 256-pin QFP HD6417751RBG200 (V) 292-pin BGA Notes: 1. Contact a Renesas sales office regarding product versions with specifications for a wider temperature range (−40 to +85°C). The wide temperature range (−40 to +85°C) is the standard specification for the HD6417751RBA240HV. 2. All listed products are available in lead-free versions. Lead-free products have a “V” appended at the end of the part number. R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1125 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group, SH7751R Group Page 1126 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 SH7751 Group, SH7751R Group Appendix I Version Registers Appendix I Version Registers The configuration of the registers related to the product version is shown below. Table I.1 Register Configuration Name Abbreviation Read/Write Initial value P4 Address Area 7 Address Processor version register PVR R * H'FF000030 H'1F000030 32 Product register PRR R * H'FF000044 H'1F000044 32 Note: * Access Size Refer to table below. PVR and PRR Initial Values Product Name PVR PRR SH7751 H'041100xx H'xxxxxxxx SH7751R H'040500xx H'0000011x Legend: x: Undefined 1. Processor Version Register (PVR) Initial Value Example for SH7751R Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Version information Initial value: 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — Version information Initial value: 0 0 0 0 0 0 0 0 — — — — — — — — R/W: R R R R R R R R — — — — — — — — R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Page 1127 of 1128 Appendix E Synchronous DRAM Address Multiplexing Tables SH7751 Group, SH7751R Group 2. Product Register (PRR) Initial Value Example for SH7751R Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Version information Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — Version information Initial value: 0 0 0 0 0 0 0 1 0 0 0 1 — — — — R/W: R R R R R R R R R R R R — — — — Page 1128 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013 Renesas 32-Bit RISC Microcomputer SH7751 Group, SH7751R Group User's Manual: Hardware Publication Date: 1st Edition, April, 2000 Rev.3.01, September 24, 2013 Published by: Renesas Electronics Corporation http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-651-700, Fax: +44-1628-651-804 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 D üsseldorf, Germany Tel: +49-211-65030, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. 7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898 Renesas Electronics Hong Kong Limited Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2886-9318, Fax: +852 2886-9022/9044 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 © 2013 Renesas Electronics Corporation. All rights reserved. Colophon 1.3 –– SH7751 Group, SH7751R Group User’s Manual: Hardware R01UH0457EJ0301 (Previous Number: REJ09B0370-0400)
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