ISL6590DR-T

ISL6590 ® Data Sheet Digital Multi-Phase PWM Controller for Core-Voltage Regulation Processors that operate above a GHz require fast, intelligent power systems. The Intersil ISL6590 controller offers intelligent digital, multi-phase control that provides high bandwidth, optimal control frequency response, noise immunity and active transient response control algorithms. The design is fully scalable for controlling up to six phases, each featuring the Intersil ISL6580 intelligent power stage. The user can configure and monitor the power system via the Asynchronous Serial Interface (ASI). The ISL6590 controller flexibility can be extended with the addition of an external EEPROM for updating key circuit operating parameters in the control loop and overall system design. The digital architecture reduces the design time for engineers with the use of our software. The software allows the designer the freedom to choose output stage components and still achieve optimized system performance. The ISL6590 digital controller communicates with the ISL6580 integrated power stages via 100% digital signaling. Serial communication allows for separation of the controller and the power stage, providing placement and layout freedom to the power stage. The digital controller implements phase balancing to ensure even distribution of phase currents. The ISL6590 controller configures the ISL6580 power stage current limit, VID reference, nonoverlap period, Active Transient Response (ATR) trigger levels and maximum temperature limit. The digital controller also monitors the ISL6580 power stage peak currents, overtemperature fault, input under voltage, output over/under voltage to ensure proper operation of the power supply. Pinout ISL6590 (QFN) TOP VIEW 33 32 1 Features • Open Architecture features software programmable control loop compensation enabling optimal system performance - User accessible asynchronous serial interface • Intel VR10 - 6-bit Dynamic VID™ - Output voltage regulation range of 0.8375V to 1.600Vdc • 250kHz to 1MHz switching frequency • 100% digital control and signaling • Active Transient Response (ATR) control algorithms for minimized voltage droop and overshoot • Controls up to six ISL6580 intelligent power stages (20A per phase, 120A total system current) • Programmable Adaptive voltage positioning (AVP) load line • Configurable control loop parameters (with optional external EEPROM) • Programmable MOSFET dead time control • High speed voltage and current control loops • PWRGD and OUTEN • Serial interface to ISL6580 power stages for system monitoring and configuration • 64 Ld 9x9 QFN package • QFN Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile. PART NUMBER ISL6590DR TEMP. (oC) 0 to 85 PACKAGE PKG. NO. 64 Ld 9x9 QFN L64.9x9-S TEST 2 ATRL SOC ERR VDD_IO SYS_CLK VDD_IO NC NC VDD_CORE NC NC IDIG6 PWM6 NDRIVE6 TEST1 EXT_RESETB NDRIVE5 PWM5 IDIG5 16 17 NDRIVE4 PWM4 IDIG4 49 48 FN9061 Ordering Information PLL_FILTER PLL_ANALOG_VDD PLL_ANALOG_VSS PLL_DIGITAL_VDD PLL_DIGITAL_VSS OSC_IN OSC_OUT VDD_CORE ARX ATX VDD_IO SCLK SDATA TEST4 TEST3 ATRH 64 01 IDIG1 NDRIVE2 PWM2 IDIG2 VDD_CORE NDRIVE3 PWM3 IDIG3 VDD_IO OUTEN VID [0] VID [1] VID [2] VID [3] VID [4] VID [5] VDD_CORE PWRGD VDD_IO MCLK MDO MDI MCS NDRIVE1 PWM1 April 2003 CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Dynamic VID™ is a trademark of Intersil Americas Inc. ISL6590 Typical Application Circuit 3.3 V 5-12 V 12 V 3.3 V 1.8 V 2.5 V VDD VDD_IO VID[0:5] PWRGD VDRIVEVCC VREF ATRH ATRL VDD_CORE V SENP VSENN ISL6580 ERR SOC SCLK SDATA SYSCLK ERR SOC SCLK SDATA CLK PWM IDIG NDRIVE PWM IDIG NDRIVE ISENSE Vout VSW NGATE OUTEN PGND GND ARX ATX 3.3 V ISL6590 VDD 5-12 V 12 V VDRIVEVCC V SENP VREF ATRH ATRL ATRH ATRL REGULATION CHANNEL VSENN ISL6580 ERR SOC SCLK SDATA CLK OSC_IN OSC_OUT ISENSE VSW NGATE PWM IDIG NDRIVE PWM IDIG NDRIVE TEST1 TEST2 TEST3 TEST4 GND VDRIVEVCC VREF ATRH ATRL MDO ATR CHANNEL 5-12 V 12 V 3.3 V VDD EEPROM PGND V SENP VSENN ISL6580 MDI ERR SOC SCLK SDATA CLK MCS MCLK ISENSE VSW NGATE PWM IDIG NDRIVE PWM IDIG NDRIVE GND CONTROLLER INTERFACE BUS 2 PGND GND UV/OV CHANNEL Vout RTN ISL6590 Absolute Maximum Ratings Thermal Information Supply Voltage (VDD_IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.63V (VDD_Core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.98V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV Thermal Resistance θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . θJA-0 LFPM AIR . . . . . . . . . . . . . . . . . . . θJA-100 LFPM AIR . . . . . . . . . . . . . . . . . θJA-200 LFPM AIR . . . . . . . . . . . . . . . . . θJA-400 LFPM AIR . . . . . . . . . . . . . . . . . θJB . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions Supply Voltage (VDD_IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V ±5% (VDD_Core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V ±5% (Analog PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V ±5% (Digital PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V ±5% Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC (oC/W) 3 29.0 26.6 25.0 23.2 8 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .125oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a “High Effective” Thermal Conductivity Board with “Direct Attach” features. (See Tech Brief TB379 for details.) Operating Conditions: VDDIO = 3.3V, VDDCORE = 1.8V, TA = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 0.8 - - V INPUTS Outen, VID[0:5], VIH 3.3V no internal pull-up/down resistors Outen, VID[0:-5], VIL 3.3V no internal pull-up/down resistors - - 0.4 V MDI, IDIG[1-6], ATRL, ATRH, SOC, ERR VIH 3.3V internal pull-down resistor 2.0 - - V MDI, IDIG[1-6], ATRL, ATRH, SOC, ERR VIL 3.3V internal pull-down resistor - - 0.8 V EXT_RESETB, VIH 3.3V internal pull-up resistor 2.0 - - V EXT_RESETB, VIL 3.3V internal pull-up resistor - - 0.8 V ARX, VIH 3.3V internal pull-up resistor 2.0 - - V ARX, VIL 3.3V internal pull-up resistor - - 0.8 V OSC_IN, VIH No internal pull-up/down resistors 2.0 - - V OSC_IN, VIL No internal pull-up/down resistors - - 0.8 V OUTPUTS MCLK, MDO, MCS, NDRIVE[0:5], PWM[0:5], ATX, VOH No internal pull-up/down resistors, 8mA drive 2.4 - - V MCLK, MDO, MCS, NDRIVE[0:5], PWM[0:5], ATX, VOL No internal pull-up/down resistors, 8mA drive - - 0.4 V SYS_CLK, VOH No internal pull-up/down resistors, 20mA drive 2.4 - - V SYS_CLK, VOL No internal pull-up/down resistors, 20mA drive - - 0.4 V SCLK, VOH No internal pull-up/down resistors, 16mA drive 2.4 - - V SCLK, VOL No internal pull-up/down resistors, 16mA drive - - 0.4 V SDATA, VOH 3.3V pull-up resistor, 16mA drive 2.4 - - V SDATA, VOL 3.3V pull-up resistor, 16mA drive - - 0.4 V SDATA, VIH 3.3V pull-up resistor 2.0 - - V SDATA, VIL 3.3V pull-up resistor - - 0.8 V PWRGD, VOH Open drain, 6mA drive 2.4 - - V PWRGD, VOL Open drain, 6mA drive - - 0.4 V OSC_OUT, VOH No internal pull-up/down resistors, 10mA drive 2.4 - - V OSC_OUT, VOL No internal pull-up/down resistors, 10mA drive - - 0.4 V 3 ISL6590 Operating Conditions: VDDIO = 3.3V, VDDCORE = 1.8V, TA = 25oC, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Vddio Rising 1.4 - - V Vddio Falling - - 2.55 V POWER-ON RESET AND ENABLE POR Threshold OUTEN Threshold Vddcore Rising 0.7 - - V Vddcore Falling - - 1.4 V OUTEN Rising - 0.71 - V OUTEN Falling - 0.64 - V 0.250 - 1 MHz 24 TBD - % OSCILLATOR Adjustment Range Max Duty Cycle NOTE: 1. Reserved for note. Block Diagram Ext_Reset ATX ARX OUTEN PWRGD VID[5:0] POR Feedback Control Asynchronous Serial Interface State Control and Fault Monitor Memory Bus MUX MDO OSC_OUT OSC_IN PLL_FILTER Clock Distribution ATRH Current Loop IDIG[6:1] Voltage Loop Non-Volatile SPI EEPOM Interface MCS PWM Driver ATRL MDI MCLK PWM [6:1] NDRIVE [6:1] State Machine Control/ Status Registers MHz Memory Mapped Registers AVP Backside Serial Bus SOC ERR SCLK SDATA SYS_CLK FIGURE 1. ISL6590 BLOCK DIAGRAM 4 ISL6590 Pin Descriptions PIN NO. 1 2-7 PIN NAME TYPE PIN DESCRIPTION OUTEN Input Output enable high input signal used to command the regulator on and a low input signal turns the regulator off. Voltage identification (6 bit). Programs Vout regulation voltage. VID[0:5] Input VDD_CORE Power IC internal core supply voltage (1.8 VDC logic). 9 PWRGD Output Power Good high output signal to indicate the regulator output voltage is within the specified range. A low signal indicates the voltage is not within range. 10, 25, 42, 44, 54 VDD_IO Power IC I/O input supply voltage (3.3 VDC logic). 11 MCLK Output EEPROM external memory clock, data is clocked out of the IC on the rising edge and data is clocked into the ISL6580 IC on the falling edge. Compliant with SPI™ EEPROMs. 12 MDO Output EEPROM external memory data output. Compliant with SPI EEPROMs. 13 MDI Input EEPROM external memory data input. Compliant with SPI EEPROMs. 14 MCS Output EEPROM external memory chip select (Active low). Compliant with SPI EEPROMs. 15, 18, 22, 26, 30, 34 NDRIVE[1:6] Output Low side drive signal used to initiate the ISL6580 to turn on the LSFET. 16, 19, 23, 27, 31, 35 PWM[1:6] Output PWM performs pulse width modulation which is used to turn on the ISL6580’s power devices. 17, 20, 24, 28, 32, 36 IDIG[1:6] Input 8, 21, 39, 57 29 Current A/D data serial 7-bit digital word (MSB first). The first bit is a start bit (Start = 1). The remaining 6 bits represent the sampled peak current in the drain of the particular ISL6580 P-Channel HSFET. (IDIG word transmission is triggered by the falling edge of the PWM signal.) IDIG is an input that is received at SYSCLK/2, normally 66.6MHz. EXT_Reset Input 33, 48, 50, 51 TEST[1:4] Output Voltage identification (6 bit). Programs Vout regulation voltage. 37, 38, 40, 41 NC N/A 43 SYSCLK Input/Output System clock which runs at a 133.3MHz rate used to clock the ISL6580. This is generated by the internal PLL circuit to create a 4x frequency multiply of the OSC_IN frequency. 45 ERR Input Serial data transmitted at a 66MHz (or SYSCLK/2) rate. This 6 bit voltage error is feedback into the control loop and used to regulate the output voltage. 46 SOC Input Start of Conversion signal initiated by the ISL6580’s Voltage A/D to create the ERR signal. 47 ATRL Input Active Transient Response Low input signal from the ISL6580 indicating a voltage overshoot on the converter output. 49 ATRH Input Active Transient Response High input signal from the ISL6580 indicating a voltage droop on the converter output. 52 SDATA Input/Output Controller serial interface for communication, monitoring, and configuration data between the ISL6580 and ISL6590 controller. 53 SCLK Output Serial digital bus clock supplied for the 16.67MHz clocking that accompanies SDATA via the Backside serial bus. 55 ATX Output Asynchronous Serial Interface Transmit 56 ARX Input Asynchronous Serial Interface Receive 58 OSC_OUT Output 59 OSC_IN Input 60 PLL_DIG_VSS PLL Bypass Ground Input Digital Ground for the 4X clock multiplier PLL. Test mode to bypass PLL input to core. 61 PLL_DIG_VDD Power 1.8V power supply for the 4X clock multiplier PLL clock tree driver (1.8 VDC logic). 62 PLL_ANA_VSS Ground Analog Ground for the 4X clock multiplier PLL. 63 PLL_ANA_VDD Power 1.8V power supply for the 4X clock multiplier PLL (1.8 VDC logic). 64 PLL_Filter 65 GND Test pins for part evaluation These pins have not been bonded out. Only used if part is using a crystal to generate the system clock. Requires a 33.33MHz oscillator or crystal which is used to generate system clock. Analog Input Filter cap for PLL. Ground 5 Paddle IC Ground ISL6590 General Description The ISL6590 is a multiphase digital controller optimized for microprocessor core voltage generation in the 0.8375Vdc 1.600Vdc output range and high current loading up to 150A with a 12Vdc input. It is intended to be used as a chipset with multiple ISL6580 power stages. The current per stage is up to 25A and the switching frequency can operate from 250kHz to 1MHz. The adaptability of having a digital controller with a serial data bus to the power stages means that the control algorithms can be adjusted with software instead of having to make hardware or board changes. All of the features of the ISL6590 are available in applications that require 3-6 phases of PWM (Pulse-Width Modulation) core voltage regulation. For more information on the power stage, consult the ISL6580 data sheet. Block Diagram Overview The ISL6590 contains functionality to control up to 6 power stages with PWM core voltage regulation. The blocks described follow the block diagram shown in Figure 1. For additional help it would be useful to reference the block diagram of the ISL6580, which is located in the ISL6580 data sheet. Asynchronous Serial Interface (ASI) (ATX, ARX) This 2-wire serial data host interface is designed to transfer command information from the designers PC to the controller, such as adjustments to register settings. The ASI is used during the design process to configure and test your power supply settings. It allows the designer to change loop coefficients to achieve the best response for their system design. This serial bus runs at 115K baud rate to interface with a host computer during testing. Backside Serial Bus (BSB) (SDATA, SCLK) The backside serial bus is a 2-wire communication between the ISL6590 controller and the ISL6580 power ICs used for transfer of control and status information. This bus is critical for proper operation of the system, any miscommunications will cause a bus error between the controller and power stages and shutdown the power supply. A bus error can be caused by poor routing of those lines or by a failed ISL6580. Feedback (PWM, NDRIVE, ATR, IDIG, SOC, ERR) The feedback control block implements the loop compensation, hysteretic control, and switch driver. Defaults for the loop compensation coefficients are retained in the memory block. If the default values need to be optimized, they can be adjusted using the ASI. The PWM generator that drives NDRIVE and PWM derives its waveform from a current balancing circuit that balances the current to each phase. The current balancing circuit requires information about the amount of current each phase is supporting. This information is obtained using the 6-bit current ADC in each ISL6580. 6 Each of the ISL6580s contains a 6-bit voltage ADC that can be used to measure the difference between the core voltage at the output and a reference voltage that is set by the VID information. Even though each ISL6580 has the voltage ADC, only one of them is required to use it. When a large change in current occurs at the output load, a large voltage transient also occurs. The ATRH and ATRL levels are designed to trigger a temporary mode in which the PWM generator aligns all phases or removes all phases in order to quickly raise or lower the output voltage. Controller Memory The internal volatile memory provides control and status registers which are reset to default states on each power up. These registers can be altered with commands from the ASI, the State Control and Fault Monitors, or the Serial Interface with the ISL6580 Power ICs. EEPROM Interface (MCS, MCLK, MDI, MDO) An external EEPROM (non-volatile memory) can be used to write custom information to the volatile memory. The nonvolatile memory can be modified via the ASI. The EEPROM contains configuration values for a given design. The ISL6590 uses the standard Serial Peripheral Interface (SPI™) serial protocol for this memory. The EEPROM must be at least a 2K byte memory. Larger memory can be used without problems, however the ISL6590 will utilize only 2K bytes. Clock Distribution (OSC_IN, OSC_OUT) The clock distribution block creates the internal system clock from an external clock source such as a crystal oscillator. It performs a 4x frequency multiplication of the external clock frequency. The maximum clock input is 33.33MHz for an IC sample rate of 133.3MHz. It generates the read/write clock for the ASI. The system clock is provided to the ISL6580s via the SYS_CLK pin. State Control and Fault Monitoring (OUTEN, VID[5:0], PWRGD) Implements control of the power system state and processes fault information from the ISL6580 Power IC. All fault detection within the system is accomplished within each individual ISL6580 and is communicated to the ISL6590 via the Backside Serial Interface. ISL6590 detects the fault through constant polling of the ISL6580 fault registers and responds by tristating the outputs or shutting down the system which then requires a power cycle and initiates a softstart sequence. Memory Bus Multiplexer Controls the priority of data transfer to the volatile memory (control registers) from both the ASI and the state control and fault monitoring. The state control and fault monitoring is given priority over the ASI. ISL6590 VERR AVP0 6-BIT OFFSET BINARY AVP PID (FROM ERR SIGNAL - ISL6580 VOLTAGE ADC) IDIG1 IDIG2 IDIG3 IDIG4 IDIG5 IDIG6 6-BIT SERIAL PIDOUT CURRENT AVERAGING IAVG PWM[6:1] PWM GENERATOR CURRENT BALANCING PARALLEL LINES NDRIVE[6:1] (TO ISL6580s) IERR CURRENT SHARE ISHARE ATRH ATRH ATRL FLASH LOGIC ATRL (FROM ISL6580 ATRH AND ATRL SIGNALS) FIGURE 2. FEEDBACK CONTROL DIAGRAM Block Diagram Details Feedback Control At a minimum, there must be three ISL6580s available to implement the following modes. 1. Regulation Mode (Voltage ADC) 2. Voltage Transient Mode (ATR Window Comparator) 3. Over/Under Voltage Mode (O/U Voltage Comparator) Additional phases 4-6 are in normal conversion mode. Located in the Feedback Control section of the ISL6590 is an interface to the feedback information collected and delivered by the analog ISL6580 power stages. To understand the functionality of the ISL6590 feedback algorithms, key blocks of the ISL6580 must be understood, such as the ADC converters and the window comparator. 6-bit Current ADC (ISL6580) A current ADC (Analog-to-Digital Converter) located in each ISL6580 measures, converts, and transmits that driver’s current back to the ISL6590 serially via the IDIG[6:1] bus. The start of conversion is initiated on the falling edge of the PWM input signal at the ISL6580 and the conversion takes about 8 SYSCLK cycles. The SYSCLK signal is provided by the ISL6590 to the ISL6580 and is equal to 4x the crystal oscillator rate. The 6-bit current ADC is a successive approximation converter, requiring one clock per bit, for a total of 6 clocks. Another clock cycle is for transferring data to the serial register. Since the PWM and SYSCLK may not be phase related, one extra clock cycle may be required depending on the alignment. It is not possible to predict when the serial data will begin to transfer on the IDIG bus, so a start bit is used to notify the ISL6590 that data is coming. The start bit is followed by the six data bits in descending order from the MSB. A bit is transferred every two SYSCLK cycles. Since the PWM signal is used as the start of conversion signal, a significant glitch on the PWM signal during the conversion or data transfer will initiate a new conversion and abort the present conversion. The ISL6590 uses the serial current information on the IDIG bus to calculate the average of all the phases, compare it to the current of each phase, and balance the phases by adjusting each PWM and NDRIVE signal as necessary. Because the start of conversion is dictated by the falling edge of the PWM signal, the effective sample rate of the current information is the PWM rate (typ 120 degrees and gain > 0dB ) or oscillation ( if phase shift > 180 degrees and gain > 0dB ). The trade off in designing the loop compensation is to achieve fast response to transients without excessive overshoot or oscillation. FIGURE 14. DIGITAL CONTROL LOOP BLOCK DIAGRAM The ISL6580 subtracts a reference from the output voltage to produce an error voltage. It converts the error voltage to a 6 bit digital number and sends it to the ISL6590 controller. The controller processes the error number numerically to provide gain (Proportional), phase lag (Integration) and phase lead (Derivative) functions. This forms the digital PID control. FIGURE 15. TYPICAL ANALOG ERROR AMPLIFIER AND COMPENSATION 15 ISL6590 Adjusting The Digital PID FIGURE 16. DIGITAL PID COMPENSATOR Frequency response of the digital PID compensator is determined by the Kp, Ki, Kd factors. These factors are stored in nonvolatile memory and are loaded in the controller at power on reset. The system designer sets the PID compensators frequency response using user interface software. The designer enters the frequencies of the desired poles and zeros and user interface software calculates the Kp, Ki and Kd factors. the software will calculate and display the frequency response of the feedback and the closed loop system. FIGURE 18. SMALL SIGNAL DESIGN WINDOW FIGURE 19. BODE PLOT FZ1 = Frequency of first zero FZ2 = Frequency of second zero FP0 = Gain * frequency of first pole (A DC*F P0) FP1 = Frequency of second pole FIGURE 17. DESIGN PARAMETER INPUT WINDOW RP2 = External Resistor used for third pole CP2 = External Capacitor used for third pole FP2 = 1 / (2 * π* RP2 * CP2 ) The software will calculate the frequency response of the PID controller and the closed loop system as in figures 20 and 21 below. 16 Primarion is a registered trademark of Primarion, Inc. Primarion PowerCode is a trademark of Primarion, Inc ISL6590 0 Compensation Phase Feedback Gain (in DB) 50 40 -10 -20 -30 -40 30 -50 20 -60 -70 10 Phase (in Degrees) 60 -80 0 -90 1 10 100 1000 10000 Frequency (in KHz) FIGURE 20. PID COMPENSATOR FREQUENCY RESPONSE 60 Time Domain It is recommended to place the first zero (FZ1) at the resonant frequency of the output inductors and capacitors (F = 1/(2π√LC = 10kHz in this case). Then increase FZ2 and FP0 to minimize response time over (under) shoot and ringing. The first microseconds of transient response are primarily dependant on the ESR and ESL of the output capacitors. After the affects of ESL and ESR pass the loop must control the response. 400 350 Loop Phase 20 300 0 250 -20 200 -40 150 -60 100 -80 50 -100 0 -120 Phase (in Degrees) 40 Loop Gain (in DB) slightly below 180 degrees at the cross over frequency, the loop will respond to transients with overshoot and ringing. Loop phase shift between 90 and 120 degrees at the cross over frequency (Phase margin = 60 to 90 degrees) results in little or no over shoot and ringing. Large phase margins (>90 degrees) result in slower transient response. -50 1 10 100 1000 10000 Frequency (in KHz) FIGURE 21. FREQUENCY RESPONSE OF THE CLOSED LOOP Compensation Methodology Due to the user interface software interface, it is very easy to change the frequency compensation and see the resulting performance on a scope or network analyzer. Transient response is viewed by applying a transient load and monitoring the output voltage with a scope. Frequency response is viewed by placing a small resistor between the output and the feed back network, applying a small sine wave at the input to the feed back network and measuring the amplitude and phase shift of the resulting sine wave on the output. Sweeping the frequency produces plots similar to those above. Frequency Domain It is recommended to place the first zero (FZ1) at the resonant frequency of the output inductors and capacitors (F = 1/(2π√LC) = 10kHz in this case). Then increase FZ2 and FP0 to maximize DC gain and the frequency at which gain drops below 0dB while keeping the phase margin above 60 degrees. Phase Margin is the difference between 180 degrees and the phase shift of the loop at the frequency where the gain drops below 0dB (cross over frequency). If the loops phase shift reaches 180 degrees and has gain equal to or greater than 0dB, it acts as positive feed back and the loop will oscillate. Even if the loops phase shift is 17 FIGURE 22. TYPICAL RESPONSE TO A LOAD TRANSIENT User Interface Software The ISL6590 controller and the ISL6580 intelligent power stage have programmable values that can be changed using the User Interface Software. The loop configuration and system performance is adjusted using the software. The use of the software allows the engineer to evaluate the system performance without having to physically change components on the board. Primarion PowerCode user interface software (provided by Intersil and our partner Primarion). Below are screen shots showing data entry points, pull down menus, buttons for help and a tutorial. The user interface software allows the designer to adjust the load line, frequency response, ATR and protection modes. ISL6590 FIGURE 23. PRIMARION POWERCODE LOADLINE AND ATR SETTINGS FIGURE 24. PRIMARION POWERCODE LOOP RESPONSE SETTINGS FIGURE 25. PRIMARION POWERCODE MONITOR WINDOW FIGURE 26. PRIMARION POWERCODE DESIGN INPUTS FIGURE 27. PRIMARION POWERCODE DUTY CYCLE LIMIT SELECTION 18 ISL6590 Register Description Tables TABLE 11. ISL6590 MEMORY MAP ADDRESS RANGE NAME R/W/S (NOTE 1) SIZE (BITS) VOLATILE MEMORY R/W/Ws1 SIZE (bits) 0000 - 01FF General Control Registers 0000 Part Number (ASCII character #1) R 8 0001 Part Number (ASCII character #2) R 8 0002 Part Number (ASCII character #3) R 8 0003 Part Number (ASCII character #4) R 8 0004 Version Number (ASCII) R 8 0005 Vendor Name (ASCII character #1) R 8 0006 Vendor Name (ASCII character #2) R 8 0007 Vendor Name (ASCII character #3) R 8 0008 Vendor Name (ASCII character #4) R 8 0009 Reserved 000A SPI Memory Status Register R 3 000B Reserved 000C Serial Polling Enable R/W 1 000D Reserved 000E System Status (LSB) R/Ws 8 000F System Status (MSB) R/Ws 8 0010 Oscillator-In Frequency (LSB) R 8 0011 Oscillator-In Frequency (MSB) R 8 0012 State Control Status (LSB) R/Ws 8 0013 State Control Status (MSB) R/Ws 8 0014 Reserved 0015 Reserved 0016 – 00EF Reserved 00F0 Scratchpad R/W 8 00F1 – 00FF Reserved 0100 - 01FF Reserved 0200 - 02FF Control/Status Registers 0200 Reserved 0201 Feedback Loop Control R/W 6 0202 Open Loop PID (LSB) R/W 8 0203 Open Loop PID (MSB) R/W 7 0204 – 0205 Reserved 0206 ATR Control R/W 4 0207 Phases Used R 4 0208 Phase Enables R/W 8 209 Reserved 19 R/W/Ws1 Size (bits) ISL6590 TABLE 11. ISL6590 MEMORY MAP (Continued) ADDRESS RANGE NAME R/W/S (NOTE 1) SIZE (BITS) R/W 6 R 8 R 8 020A VID_IN_SOFT 020B Alive Found 020D Reserved 020E VCODE_IN 020F VCODE_OUT R/W 8 0210 Enumeration Control R/W 3 0211 Enumeration Done R 4 0212 VID_IN (from VID pins) R 6 0213 OUTEN (from OUTEN pin) R 1 0214 PWRGD R 1 0215 VID_OUT R 7 0216 Voltage Error R 6 0217 Average Peak Channel Current R 6 0218 Overload R 8 0219 AVP Offset R 8 021A Voltage Calibration Offset R/W 5 021B Regulated R 1 021C – 21F Reserved 0220 Peak Channel Current – Phase 1 R 6 0221 Peak Channel Current – Phase 2 R 6 0222 Peak Channel Current – Phase 3 R 6 0223 Peak Channel Current – Phase 4 R 6 0224 Peak Channel Current – Phase 5 R 6 0225 Peak Channel Current – Phase 6 R 6 0226 Peak Channel Current – Phase 7 R 6 0227 Peak Channel Current – Phase 8 R 6 0228 – 022F Reserved 0230 On Time – Phase 1 (upper 8 bits) R 8 0231 On Time – Phase 2 (upper 8 bits) R 8 0232 On Time – Phase 3 (upper 8 bits) R 8 0233 On Time – Phase 4 (upper 8 bits) R 8 0234 On Time – Phase 5 (upper 8 bits) R 8 0235 On Time – Phase 6 (upper 8 bits) R 8 0236 On Time – Phase 7 (upper 8 bits) R 8 0237 On Time – Phase 8 (upper 8 bits) R 8 0238 – 02FF Reserved 0300 - 03FF Reserved 0400 – 07FF Broadcast Write Memory Map 0400 Reserved 20 R/W/Ws1 Size (bits) ISL6590 TABLE 11. ISL6590 MEMORY MAP (Continued) ADDRESS RANGE NAME R/W/S (NOTE 1) SIZE (BITS) 0401 Reserved 0402 HFWND (High ATR Window) W 4 0403 LFWND (Low ATR Window) W 4 0404 VID (7 bit Voltage Identification) W 7 0405 ILIM (Current Limit) W 2 0406 TSD (Thermal Shutdown) W 3 0407 Reserved 0408 TEST W 8 0409 ENABLE1 (Block Enables LSB) W 8 040A ENABLE2 (Block Enables MSB) W 3 040B SPARE1 W 8 040C SPARE2 W 8 040D – 041F Reserved Device 1 Memory Map 0420 Reserved 0421 Bus ID 0422 R/W/Ws1 SIZE (bits) R 4 HFWND (High ATR Window) R/W 4 0423 LFWND (Low ATR Window) R/W 4 0424 VID (7 bit Voltage Identification) R/W 7 0425 ILIM (Current Limit) R/W 2 0426 TSD (Thermal Shutdown) R/W 3 0427 FAULT (Fault Status) R 6 0428 TEST R/W 8 0429 ENABLE1 (Block Enables LSB) R/W 8 042A ENABLE2 (Block Enables MSB) R/W 3 042B SPARE1 R/W 8 042C SPARE2 R/W 8 0440 – 07FF Device n to 31 Memory Map (structure as Device 1) NON-VOLATILE MEMORY R/W/Ws1 Size (bits) 0800 – 09FF General Settings 0800 NVMEMCODE R/W 8 0801 Serial Clock Divider R/W 3 0802 VID_IN Table Select R/W 2 0803 VID_OUT Table Select R/W 2 0804 OffOn Non-Overlap Driver Control R/W 4 0805 OnOff Non-Overlap Driver Control R/W 4 0806 Duty Limit R/W 8 0807 System Configuration R/W 3 0808 Reserved R/W 5 21 ISL6590 TABLE 11. ISL6590 MEMORY MAP (Continued) ADDRESS RANGE NAME R/W/S (NOTE 1) SIZE (BITS) 0809 A/D ID R/W 5 080A WCOMP ID R/W 5 080B OUVP ID R/W 5 080C MG Poll Priority R/W 7 080D State Control R/W 6 080E Reserved R/W 2 080F Phases to be Used R/W 8 0810 POR Wait R/W 5 0811 Regulation Window R/W 6 0812 Regulation Time R/W 8 0813 Voltage Calibration Maximum R/W 6 0814 Reserved R/W 8 0815 Startup Fault Mask R/W 7 0816 Startup Enables 1 R/W 8 0817 Startup Enables 2 R/W 5 0818 Active Fault Mask R/W 7 0819 Active Enables 1 R/W 8 081A Active Enables 2 R/W 5 081B Active Feature Mask R/W 1 081C Reserved 081D Current Limit R/W 6 081E – 083F Reserved 0840 ATR Exit Delay R/W 5 0841 ATR Count Max (LSB) R/W 8 0842 ATR Count Max (MSB) R/W 1 0843 PVID Offset R/W 4 0844 – 086F Reserved 0870 – 08FF Reserved Address Range General Control Registers R/W/Ws1 Size (bits) Phase # Independent Compensation Parameters 0900 Kp AVP R/W 8 0901 Kd AVP R/W 8 0902 Kp PID R/W 6 0903 Ki PID R/W 8 0904 Kd Transient Recovery R/W 8 0905 Vos AVP R/W 6 0906 Ios AVP R/W 8 0907 Kfp PID R/W 6 0908 Kfd PID R/W 6 22 ISL6590 TABLE 11. ISL6590 MEMORY MAP (Continued) ADDRESS RANGE NAME R/W/S (NOTE 1) SIZE (BITS) Phase # Dependent Compensation Parameters 0909 K Current Balancing R/W 8 090A Kd PID R/W 8 090B HFWND R/W 4 090C LFWND R/W 4 090D OUVPLF R/W 4 090E OOVPHF R/W 4 090F ILIM (not phase # dependent) R/W 2 0910 Reserved 0911 Reserved 0912 Switching Frequency Phases=1 (LSB) R/W 8 0913 Switching Frequency Phases=1 (MSB) R/W 4 0914 Switching Frequency Phases=2 (LSB) R/W 8 0915 Switching Frequency Phases=2 (MSB) R/W 4 0916 Switching Frequency Phases=3 (LSB) R/W 8 0917 Switching Frequency Phases=3 (MSB) R/W 4 0918 Switching Frequency Phases=4 (LSB) R/W 8 0919 Switching Frequency Phases=4 (MSB) R/W 4 091A Switching Frequency Phases=5 (LSB) R/W 8 091B Switching Frequency Phases=5 (MSB) R/W 4 091C Switching Frequency Phases=6 (LSB) R/W 8 091D Switching Frequency Phases=6 (MSB) R/W 4 091E Switching Frequency Phases=7 (LSB) R/W 8 091F Switching Frequency Phases=7 (MSB) R/W 4 0920 Switching Frequency Phases=7 (LSB) R/W 8 0921 Switching Frequency Phases=7 (MSB) R/W 4 0922 – 093F Reserved 0940 Custom VID2VCODE0 LUT Entry R/W 8 0941 – 097F Custom VID2VCODE1 to VID2VCODE63 LUT Entries R/W 8 0980 – 09FF Reserved for User 0A00 – FFFF Reserved R/W/Ws1 SIZE (bits) TABLE 12. SECOND SOURCE INFORMATION PART NUMBER TEMP. (oC) PACKAGE PKG. NO Primarion PX3530 0 to 85 64 Ld QFN L64.9x9 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 23 ISL6590 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L64.9x9-S 64 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS 2X 0.10 A C SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - A2 - 0.50 - - 0.30 5, 8 A D D/2 9 D1 2X D1/2 N 0.10 6 C B A3 b INDEX 1 AREA 2 3 E/2 E1/2 9 9.00 BSC - 8.75 BSC - 3.64 E E2 3.74 3.84 7, 8 9.00 BSC - 8.75 BSC 3.64 e B C - D E1 0.10 0.20 D1 D2 E E1 0.25 REF 0.18 3.74 3.84 7, 8 - - 0.50 BSC - B 2X 0.10 C TOP VIEW A 2X 0 4X A2 A // 0.10 0.08 C SEATING PLANE SIDE VIEW A3 A1 C k 0.25 - L 0.30 0.40 0.50 8 L1 - - 0.15 9 C N 64 2 Nd 16 3 Ne 5 0.10 4X b M CA B 7 8 16 - - 0.50 θ - - 8 (DATUM B) Rev. 0 04/03 D2 4X P 3 P D2 2 NX k NOTES: N 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 4X P 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. (DATUM A) (Ne-1)Xe REF. E2 6 INDEX AREA E2/2 3 7 2 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 1 8 NX L N e 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. (Nd-1)Xe REF. BOTTOM VIEW 9. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. A1 NX b 5 SECTION "C-C" SCALE: NONE CL 9 e TERMINAL TIP FOR EVEN TERMINAL/SIDE 24 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. L L1