MPC9658ACR2

3.3V 1:10 LVCMOS PLL Clock Generator MPC9658 NRND NRND – Not Recommend for New Designs DATASHEET The MPC9658 is a 3.3 V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 250 MHz and output skews less than 120 ps the device meets the needs of the most demanding clock applications. The MPC9658 is specified for the temperature range of 0°C to +70°C. Features • • • • • • • • • • • • MPC9658 LOW VOLTAGE 3.3 V LVCMOS 1:10 PLL CLOCK GENERATOR 1:10 PLL based low-voltage clock generator Supports zero-delay operation 3.3 V power supply Generates clock signals up to 250 MHz Maximum output skew of 120 ps Differential LVPECL reference clock input External PLL feedback Drives up to 20 clock lines 32-lead LQFP packaging 32-lead Pb-free Package Available Pin and function compatible to the MPC958 NRND – Not Recommend for New Designs FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX The MPC9658 utilizes PLL technology to frequency lock its outputs onto an 32-LEAD LQFP PACKAGE input reference clock. Normal operation of the MPC9658 requires the connection Pb-FREE PACKAGE of the QFB output to the feedback input to close the PLL feedback path (external CASE 873A-03 feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 50 to 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9658 is running at either 2x or 4x of the reference clock frequency. The MPC9658 has a differential LVPECL reference input along with an external feedback input. The MPC9658 is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9658 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50  transmission lines. For series terminated transmission lines, each of the MPC9658 outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package. MPC9658 REVISION 6 JANUARY 8, 2013 1 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Q0 Q1 VCC PCLK 25 k & PCLK 25 k Ref VCO 0 0 1 0 1 2 1 2 1 Q3 Q4 PLL 200 – 480 MHz FB_IN Q2 Q5 FB Q6 25 k VCC Q7 325 k Q8 PLL_EN VCO_SEL Q9 BYPASS MR/OE QFB 25 k Q2 VCC Q3 GND Q4 VCC Q5 GND Figure 1. MPC9658 Logic Diagram 24 23 22 21 20 19 18 17 GND 25 16 Q6 Q1 26 15 VCC VCC 27 14 Q7 Q0 28 13 GND GND 29 12 Q8 QFB 30 11 VCC VCC 31 10 Q9 VCO_SEL 32 MPC9658 BYPASS PLL_EN 6 7 8 GND FB_IN 5 PCLK 4 PCLK 3 MR/OE 2 VCC_PLL 9 1 GND Figure 2. MPC9658 32-Lead Pinout (Top View) MPC9658 REVISION 6 JANUARY 8, 2013 2 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Table 1. Pin Configurations Number Name Type Description PCLK, PCLK Input LVPECL PECL reference clock signal FB_IN Input LVCMOS PLL feedback signal input, connect to QFB VCO_SEL Input LVCMOS Operating frequency range select BYPASS Input LVCMOS PLL and output divider bypass select PLL_EN Input LVCMOS PLL enable/disable MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) and device reset Q0–9 Output LVCMOS Clock outputs QFB Output LVCMOS Clock output for PLL feedback, connect to FB_IN GND Supply Ground Negative power supply (GND) VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Refer to APPLICATIONS INFORMATION for details. VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. Table 2. Function Table Control Default 0 1 (1) PLL_EN 1 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. MPC9658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Selects the VCO output. BYPASS 1 Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs. MPC9658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Selects the output dividers. VCO_SEL 1 VCO  1 (High frequency range). fREF = fQ0–9 = 2  fVCO VCO  2 (Low output range). fREF = fQ0–9 = 4  fVCO MR/OE 0 Outputs enabled (active) Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (PCLK). 1. PLL operation requires BYPASS = 1 and PLL_EN = 1. Table 3. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.9 V VIN DC Input Voltage –0.3 VCC +0.3 V DC Output Voltage –0.3 VCC +0.3 V 20 mA 50 mA 125 °C VOUT IIN IOUT TS DC Input Current DC Output Current Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. MPC9658 REVISION 6 JANUARY 8, 2013 3 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Table 4. General Specifications Symbol Characteristics Min Typ Max VCC  2 Unit Condition VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V LU Latch-Up Immunity 200 mA CPD Power Dissipation Capacitance 10 pF Per output CIN Input Capacitance 4.0 pF Inputs JA LQFP 32 Thermal resistance junction to ambient JESD 51-3, single layer test board JESD 51-6, 2S2P multilayer test board JC LQFP 32 Thermal resistance junction to case V 83.1 73.3 68.9 63.8 57.4 86.0 75.4 70.9 65.3 59.6 C/W C/W C/W C/W C/W 59.0 54.4 52.5 50.4 47.8 60.6 55.7 53.8 51.5 48.8 C/W C/W C/W C/W C/W 23.0 26.3 C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C) Symbol Characteristics VIH Input High Voltage VIL Input Low Voltage VPP VCMR (1) VOH (PCLK) 250 Common Mode Range (PCLK) 1.0 Output High Voltage Output Low Voltage ZOUT Output Impedance ICC_PLL ICCQ Input Typ 2.0 Peak-to-Peak Input Voltage VOL IIN Min Max Unit VCC + 0.3 V LVCMOS 0.8 V LVCMOS mV LVPECL V LVPECL V IOH = –24 mA(2) V V IOL = 24 mA IOL = 12 mA VCC –0.6 2.4 (3) 0.55 0.30  14 – 17 Current(4) Condition 200 A VIN = VCC or GND Maximum PLL Supply Current 12 20 mA VCC_PLL Pin Maximum Quiescent Supply Current 13 20 mA All VCC Pins 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9658 is capable of driving 50  transmission lines on the incident edge. Each output drives one 50  parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series terminated transmission lines. 3. The MPC9658 output levels are compatible to the MPC958 output levels. 4. Inputs have pull-down resistors affecting the input current. MPC9658 REVISION 6 JANUARY 8, 2013 4 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C)(1) Symbol fREF fVCO Characteristics Min (2) Input reference frequency  2 feedback PLL mode, external feedback  4 feedback(3) Input reference frequency in PLL bypass mode(4) (5) VCO lock frequency range fMAX Output Frequency VPP (3)  2 feedback  4 feedback(4) Typ Max Unit Condition 100 50 250 125 MHz MHz 0 250 MHz 200 500 MHz 100 50 250 125 MHz MHz PLL locked PLL locked PLL locked PLL locked Peak-to-peak input voltage (PCLK) 500 1000 mV LVPECL (6) Common Mode Range (PCLK) 1.2 VCC –0.9 V LVPECL tPW,MIN Width(7) VCMR Input Reference Pulse t() Propagation Delay (static phase offset) tPD Propagation Delay (PLL and divider bypass) tsk(O) Output-to-output 2.0 PCLK to FB_IN fREF = 100 MHz any frequency PCLK to Q0-9 ns PLL locked –70 –125 +80 +125 ps ps 1.0 4.0 ns 120 ps (T  2)+400 ps 1.0 ns Skew(8) Cycle(9) (T  2)–400 T2 DC Output Duty tr, tf Output Rise/Fall Time tPLZ, HZ Output Disable Time 7.0 ns tPZL, LZ Output Enable Time 6.0 ns tJIT(CC) Cycle-to-cycle jitter 80 ps tJIT(PER) Period Jitter 80 ps 5.5 6.5 ps ps tJIT() BW tLOCK 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 0.1 500 MHz and  2 feedback, RMS (1)(10) I/O Phase Jitter fVCO = fVCO = 500 MHz and  4 feedback, RMS (1) PLL closed loop bandwidth(11)  2 feedback(3)  4 feedback(5) Maximum PLL Lock Time 6 – 20 2–8 0.55 to 2.4 V MHz MHz 10 ms AC characteristics apply for parallel output termination of 50  to VTT.  2 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.  4 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE = 0. In bypass mode, the MPC9658 divides the input reference clock. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO  FB. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN  fREF  100% and DCREF,MAX = 100% – DCREF,MIN. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation in PLL zero-delay mode. Output duty cycle is DC = (0.5 ± 400 ps  fOUT) Þ 100%. For example, the DC range at fOUT = 100MHz is 46% < DC < 54%. T = output period. Refer to APPLICATIONS INFORMATION for a jitter calculation for other confidence factors than 1  and a characteristic for other VCO frequencies. –3 dB point of PLL transfer characteristics. MPC9658 REVISION 6 JANUARY 8, 2013 5 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR APPLICATIONS INFORMATION Programming the MPC9658 The MPC9658 supports output clock frequencies from 50 to 250 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500 MHz for stable and optimal operation. Two operating frequency ranges are supported: 50 to 125 MHz and 100 to 250 MHz. Table 7. MPC9658 Configurations (QFB connected to FB_IN) illustrates the configurations supported by the MPC9658. PLL zero-delay is supported if BYPASS = 1, PLL_EN = 1, and the input frequency is within the specified PLL reference frequency range. Table 7. MPC9658 Configurations (QFB connected to FB_IN) BYPASS PLL_EN VCO_SEL Operation 0 X X 1 0 1 0 1 1 Frequency Ratio Output range (fQ0–9) VCO Test mode: PLL and divider bypass fQ0–9 = fREF 0 – 250 MHz n/a 0 Test mode: PLL bypass fQ0–9 = fREF  2 0 – 125 MHz n/a 1 Test mode: PLL bypass fQ0–9 = fREF  4 0 – 62.5 MHz n/a 1 0 PLL mode (high frequency range) fQ0–9 = fREF 100 – 250 MHz fVCO = fREF  2 1 1 PLL mode (low frequency range) fQ0–9 = fREF 50 – 125 MHz fVCO = fREF  4 The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 3 – 5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9658 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Power Supply Filtering The MPC9658 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9658 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9658. Figure 3 illustrates a typical power supply filter scheme. The MPC9658 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 12 mA (20 mA maximum), assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. RF = 5–15  VCC Using the MPC9658 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9658. Designs using the MPC9658 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9658 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. CF = 22F RF VCC_PLL CF 10 nF MPC9658 VCC 33...100 nF Figure 3. VCC_PLL Power Supply Filter MPC9658 REVISION 6 JANUARY 8, 2013 6 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Calculation of Part-to-Part Skew The MPC9658 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9658 are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of –214 ps to 224 ps relative to PCKL (fREF = 100 MHz, FB = ³4, tjit() = 8 ps RMS at fVCO = 400 MHz): tSK(PP) = [–70ps...80ps] + [–120ps...120ps] + [(8ps  –3)...(8ps  3)] + tPD, LINE(FB) tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT()  CF This maximum timing uncertainty consist of four components: static phase offset, output skew, feedback board trace delay, and I/O (phase) jitter: TCLKCommon Due to the frequency dependence of the I/O jitter, Figure 5 can be used for a more precise timing performance analysis. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB tPD,LINE(FB) 20 tjit(f) [ps] RMS —t(ý) QFBDevice 1 tSK(PP) = [–214ps...224ps] + tPD, LINE(FB) tJIT() Any QDevice 1 +tSK(O) Any QDevice 2 tJIT() Figure 4. MPC9658 Max. Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Table 8. Confidence Factor CF Probability of clock edge within the distribution  1 0.68268948  2 0.95449988  3 0.99730007  4 0.99993663  5 0.99999943  6 0.99999999 MPC9658 REVISION 6 JANUARY 8, 2013 250 300 350 400 FCO Frequency [MHz] 450 500 Driving Transmission Lines The MPC9658 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20  the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Freescale Semiconductor Application Note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50  resistance to VCC  2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9658 clock driver. However, for the series terminated case there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 6 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9658 clock driver is effectively doubled due to its capability to drive multiple lines. tSK(PP) CF FB = ³ 2 5 Figure 5. Max. I/O Jitter versus Frequency +tSK(O) Max. skew FB = ³ 4 10 0 200 +t() QFBDevice2 15 7 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR 3.0 MPC958 Output Buffer In RS = 36  14  2.5 ZO = 50  OutA tD = 3.8956 OutB tD = 3.9386 OutA MPC958 Output Buffe In RS = 36  Voltage (V) 2.0 ZO = 50  OutB0 In 1.5 1.0 14  RS = 36  ZO = 50  0.5 OutB1 0 2 Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9658 output buffer is more than sufficient to drive 50  transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9658. The output waveform in Figure 7 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36  series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = Z0 = RS = R0 = VL = = 6 8 Time (ns) 10 12 14 Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering. However, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 8 should be used. In this case, the series terminating resistors are reduced such that, when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. MPC958 Output Buffe VS (Z0  (RS+R0 +Z0)) 50  || 50  36  || 36  14  3.0 (25 (18+14+25) 1.31 V RS = 22  ZO = 50  RS = 22  ZO = 50  14  14 + 22  || 22 = 50  || 50  25  = 25  At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). Pulse Generator Z = 50  4 ZO = 50  Figure 8. Optimized Dual Line Termination MPC9658 DUT ZO = 50  RT = 50  RT = 50  VTT VTT Figure 9. PCLK MPC9658 AC Test Reference MPC9658 REVISION 6 JANUARY 8, 2013 8 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR VCC VCC 2 PCLK GND VCC VPP = 0.8V PCLK VCMR = VCC–1.3V FB_IN VCC VCC 2 VCC 2 GND GND tSK(O) t(PD) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 11. Propagation Delay (t(PD), static phase offset) Test Reference Figure 10. Output-to-Output Skew tSK(O) VCC VCC 2 PCLK GND tP FB_IN T0 DC = tP/T0 x 100% TJIT() = |T0–T1mean| The deviation in t0 for a controlled edge with respect to a T0 mean in a random sample of cycles The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 13. I/O Jitter Figure 12. Output Duty Cycle (DC) TN TN+1 TJIT(CC) = |TN–TN+1| TJIT(PER) = |TN–1/f0| T0 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 14. Cycle-to-Cycle Jitter Figure 15. Period Jitter VCC=3.3 V 2.4 0.55 tF tR Figure 16. Output Transition Time Test Reference MPC9658 REVISION 6 JANUARY 8, 2013 9 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR 4X 0.20 H 6 A-B D D1 PIN 1 INDEX 3 e/2 D1/2 32 A, B, D 25 1 E1/2 A F B 6 E1 E 4 F DETAIL G 8 17 9 7 D/2 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. 4 D A-B D H SEATING PLANE DETAIL G D 4X 0.20 C E/2 28X e 32X C 0.1 C DETAIL AD BASE METAL PLATING b1 c c1 b 8X (θ1˚) 0.20 R R2 A2 5 8 C A-B D SECTION F-F R R1 A M 0.25 GAUGE PLANE A1 (S) L (L1) θ˚ DETAIL AD DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0˚ 7˚ 12 REF 0.08 0.20 0.08 --0.20 REF CASE 873A-03 ISSUE B 32-LEAD LQFP PACKAGE MPC9658 REVISION 6 JANUARY 8, 2013 10 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Revision History Sheet Rev 6 Table Page 1 Description of Change Date NRND – Not Recommend for New Designs 1/8/13 MPC9658 REVISION 6 JANUARY 8, 2013 11 ©2013 Integrated Device Technology, Inc. MPC9658 Data Sheet 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. 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