RT9212GC

Preliminary RT9212 Dual 5V Synchronous Buck PWM DC-DC and Linear Power Controller General Description The RT9212 is a 3-in-one power controller delivers high efficiency and tight regulation from two voltage regulating synchronous buck PWM DC-DC and one linear power controllers. The RT9212 can control two independent output voltages adjustment in range of 0.8V to 4.0V with 180 degrees channel to channel phase operation to reduce input ripple. In dual power supply application the RT9212 monitors the output voltage of both Channel 1 and Channel 2. An independent PGOOD (power good) signal is asserted for each channel after the soft-start sequence has completed, and the output voltage is within ±15% of the set point. The linear controller drives an external transistor to provide an adjustable output voltage. Built-in over-voltage protection prevents the output from going above 137.5% of the set point by holding the lower MOSFET on and the upper MOSFET off. Adjustable overcurrent protection (OCP) monitors the voltage drop across the RDS(ON) of the upper MOSFET for each synchronous buck PWM DC-DC controller individually. Features Operating with Single 5V Supply Voltage Drives All Low Cost N-MOSFETs Voltage Mode PWM Control 300kHz Fixed Frequency Oscillator Fast Transient Response : Full 0% to 100% Duty Ratio Internal Soft-Start Adaptive Non-Overlapping Gate Driver Over-Current Fault Monitor on VCC, No Current Sense Resistor Required RoHS Compliant and 100% Lead (Pb)-Free Applications Graph Card Motherboard, Desktop Servers IA Equipments Telecomm Equipments High Power DC-DC Regulators Pin Configurations (TOP VIEW) UGATE1 BOOT1 PHASE1 NC FB1 COMP1 NC NC GNDA PHASE2 BOOT2 UGATE2 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PGND1 LGATE1 PVCC1 OCSET1/SD OCSET2/SD PGOOD FB2 FBL DRV VCC LGATE2 PGND2 Ordering Information RT9212 Package Type C : TSSOP-24 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. TSSOP-24 DS9212-05 March 2007 www.richtek.com 1 RT9212 Typical Application Circuit Preliminary VIN 2.5V/3.3V/5V VCC 5V C3 VIN( >VOUT1 & VOUT2 ) 2.5V/3.3V/5V + R1 3.48k C1 1nF R2 3.48k C2 1nF 1uF R9 10k D1 1N4148 C9 0.1uF C10 470uF RT9212 Q5 RESET2 RESET1 21 20 3.3V + PHKD6N02LT Q1 L1 1uH C12 to C15 150uF (x 4) + Q6 15 VCC OCSET1/SD PGOOD BOOT1 19 2 1 3 22 23 24 11 12 10 14 13 18 VOUT1 1.8V OCSET2/SD UGATE1 DRV FBL COMP1 PHASE1 PVCC1 LGATE1 PGND1 BOOT2 UGATE2 Q2 16 17 6 C4 100uF VOUT3 2.5V R3 255 2SD1802 C6 100pF + VCC 5V D2 1N4148 C11 0.1uF VIN 2.5V/3.3V/5V C7 5.6nF R5 6.34k C5 470uF PHASE2 5 FB1 LGATE2 PGND2 GNDA C8 15nF 9 FB2 PHKD6N02LT Q3 L2 1uH C16 to C17 150uF (x 2) R4 120 R6 1k VOUT2 1.5V R10 105 + Q4 R7 1.25k R8 100 R11 120 www.richtek.com 2 DS9212-05 March 2007 Preliminary Functional Pin Description UGATE1 (Pin 1) Channel 1 upper gate driver output. Connect to gate of the high-side power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. BOOT1 (Pin 2) Bootstrap supply pin for the upper gate driver. Connect the bootstrap capacitor between BOOT1 pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. PHASE1 (Pin 3) Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. PHASE1 is used to monitor the Voltage drop across the upper MOSFET of the channel 1 regulator for over-current protection. NC (Pin 4, 7, 8) No connection. Don’ t connect any component to this pin. FB1 (Pin 5) Channel 1 feedback voltage. This pin is the inverting input of the error amplifier. FB1 senses the channel 1 through an external resistor divider network. COMP1 (Pin 6) Channel 1 external compensation. This pin internally connects to the output of the error amplifier and input of the PWM comparator. Use a RC + C network at this pin to compensate the feedback loop to provide optimum transient response. GNDA (Pin 9) Signal ground for the IC. All voltage levels are measured with respect to this pin. Ties the pin directly to ground plane with the lowest impedance. PHASE2 (Pin 10) Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. PHASE2 is used to monitor the Voltage drop across the upper MOSFET of the channel 2 regulator for over-current protection. BOOT2 (Pin 11) RT9212 Bootstrap supply pin for the upper gate driver. Connect the bootstrap capacitor between BOOT2 pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. UGATE2 (Pin 12) Channel 2 upper gate driver output. Connect to gate of the high-side power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. PGND2 (Pin 13) Return pin for high currents flowing in low-side power N-MOSFET. Ties the pin directly to the low-side MOSFET source and ground plane with the lowest impedance. LGATE2 (Pin 14) Channel 2 lower gate drive output. Connect to gate of the low-side power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. VCC (Pin 15) Connect this pin to a well-decoupled 5V bias supply. It is also the positive supply for the lower gate driver, LGATE2. DRV (Pin 16) Connect this pin to the base of an external transistor. This pin provides the drive for the linear regulator's pass transistor. FBL (Pin 17) Linear regulator feedback voltage. This pin is the inverting input of the error amplifier and protection monitor. Connect this pin to the external resistor divider network of the linear regulator. FB2 (Pin 18) Channel 2 feedback voltage. This pin is the inverting input of the error amplifier. FB2 senses the channel 2 through an external resistor divider network. DS9212-05 March 2007 www.richtek.com 3 RT9212 PGOOD (Pin 19) Preliminary PVCC1 (Pin 22) Connect this pin to a well-decoupled 5V supply. It is also the positive supply for the lower gate driver, LGATE1. LGATE1 (Pin 23) PGOOD is an open-drain output used to indicate that both the channel 1 and channel 2 regulators are within normal operating voltage ranges. OCSET2/SD (Pin 20), OCSET1/SD (Pin 21) Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET of the supply voltage sets the overcurrent trip point. ROCSET, an internal 40μA current source , and the upper MOSFET on-resistance, (RDS(ON), set the converter over-current trip point (IOCSET) according to the following equation: I OCSET = 40uA × R OCSET Channel 1 power gate drive output. Connect to gate of the low-side power N-Channel MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. PGND1 (Pin 24) Return pin for high currents flowing in low-side power N-MOSFET. Ties the pin directly to the low-side MOSFET source and ground plane with the lowest impedance. R DS(ON) of the upper MOSFET An over-current trip cycles the soft-start function. Pulling the pin to ground resets the device and all external MOSFETs are turned off allowing the two output voltage power rails to float. Function Block Diagram VCC 0.8V Ref. 0.8V FB1 137.5% 62.5% OVP & UVP OV UV Power on Reset POR Bias OC Thermal SHDN 40uA OCSET1/SD SoftStart 1 BOOT1 + OC OV UV Thermal SHDN 300kHz Oscillator Control Logic PWM1 UGATE1 PHASE1 PVCC1 LGATE1 PGND1 PGOOD Power Good ++ EA - COMP1 FB2 Zf FB2 + EA Zc + + PWM2 OC 180 deg OV UV shift Thermal SHDN OV UV POR Control Logic VCC FBL DRV Linear Regulator SoftStart 2 OC GNDA www.richtek.com 4 + + - PGND2 LGATE2 PHASE2 UGATE2 BOOT2 OCSET2/SD 40uA DS9212-05 March 2007 Preliminary Absolute Maximum Ratings (Note 1) RT9212 7V 7V GND-0.3V to 7V 100°C/W 150°C 260°C − 65°C to 150°C 2kV 200V Supply Voltage, VCC ------------------------------------------------------------------------------------------------BOOT, VBOOT - VPHASE ----------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------------------Package Thermal Resistance TSSOP-24, θJA -------------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------- Recommended Operating Conditions (Note 3) Supply Voltage, VCC ------------------------------------------------------------------------------------------------- 5V ± 5 % Ambient Temperature Range --------------------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range --------------------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter VCC Supply Current Nominal Supply Current Shutdown Supply Power-On Reset POR Threshold Hysteresis Reference Error Amp Reference Voltage Tolerance Error Amp Reference Oscillator Free Running Frequency Ramp Amplitude DC Gain Gain-Bandwidth Product Slew Rate Symbol Test Conditions OCSET1/SD, OCSET2/SD = VCC; UGATE1 & 2, LGATE1 & 2 Open (OCSET1/SD, OCSET2/SD) = 0V Min Typ Max Units ICC ICCSD --- 5 3 --- mA mA VCCRTH VOCSET1/SD, OCSET2/SD = 4.5V VCC Rising 3.7 -- 4.1 0.5 4.5 -- V V VCCHYS VOCSET1/SD, OCSET2/SD = 4.5V ΔVEAR -VCC = 5V VCC = 5V 0.784 -0.8 2 0.816 % V VREF fOSC ΔVOSC 275 --- 300 1.9 90 10 6 325 ----- kHz VP-P dB MHz V/μs V1 Error Amplifier (External Compensation) GBW SR COMP = 10pF --- To be continued DS9212-05 March 2007 www.richtek.com 5 RT9212 Parameter V2 Error Amplifier (Internal Compensation) DC Gain Linear Regulator DRV Driver Source PWM Controller Gate Drivers Upper Gate Source (UGATE1 and 2) Upper Gate Sink (UGATE1 and 2) Lower Gate Source (LGATE1 and 2) Lower Gate Sink (LGATE1 and 2) IDS Preliminary Symbol Test Conditions Min Typ Max Units --BOOT = 10V BOOT − VUGATE = 1V VUGATE = 1V VCC − VLGATE = 1V VLGATE = 1V 35 --- dB 100 mA RUGATE RUGATE RLGATE RLGATE ---------- 7 5 4 2 70 50 50 32 -137.5 62.5 40 320 --4 115 85 --------100 -75 46 540 0.2 --120 90 Ω Ω Ω Ω ns ns ns ns ns % % μA ns V ms % % Upper Gate Rising Time (UGATE1 and 2) TR_UGATE CLoad = 3.3nF Upper Gate Falling Time (UGATE1 and 2) TF_UGATE CLoad = 3.3nF Lower Gate Rising Time (LGATE1 and 2) TR_LGATE CLoad = 3.3nF Lower Gate Falling Time (LGATE1 and 2) TF_LGATE CLoad = 3.3nF Dead Time Protection FB1 & FB2 Over-Voltage Trip FB1 & FB2 Under-Voltage Trip OCSET1 & OCSET2 Current Source OCP Blocking Time OCSET/SD Logic-Low Voltage Logic-High Voltage VIL VIH TSS VPG+ VPG– FB1 & FB2 Rising FB1 & FB2 Rising Shutdown Enable ΔFBOVT ΔFBUVT IOCSET FB1 & FB2 Rising FB1 & FB2 Falling VOCSET1/SD, OCSET2/SD = 4.5V TDT 125 -34 --2.0 -110 80 Soft-Start Interval Power Good Upper Threshold Lower Threshold Note 1.Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. www.richtek.com 6 DS9212-05 March 2007 Preliminary Typical Operating Characteristics Power Good Rising RT9212 Power Good Falling V CC (5V/Div) VOUT1 (2V/Div) VOUT2 (2V/Div) PGOOD (5V/Div) V CC (5V/Div) VOUT1 (2V/Div) VOUT2 (2V/Div) PGOOD (5V/Div) Time (5ms/Div) Time (25ms/Div) Power On IOUT1 = IOUT2 = 5A Power Off IOUT1 = IOUT2 = 5A VOUT1 (2V/Div) VOUT2 (2V/Div) UGATE1 (10V/Div) VOUT1 (2/Div) VOUT2 (2/Div) UGATE1 (10/Div) UGATE2 (5V/Div) Time (5ms/Div) UGATE2 (5V/Div) Time (500us/Div) UGATE Phase Shift LGATE Phase Shift UGATE1 (5V/Div) LGATE1 (5V/Div) UGATE2 (5V/Div) LGATE2 (5V/Div) Time (1us/Div) Time (1us/Div) DS9212-05 March 2007 www.richtek.com 7 RT9212 Bootstrap Preliminary Bootstrap UGATE1 (5V/Div) UGATE2 (5V/Div) LGATE1 (5V/Div) LGATE2 (5V/Div) Time (1us/Div) Time (1us/Div) VOUT1 Short VOUT2 Short VOUT1 (2V/Div) UGATE1 (10V/Div) LGATE1 (5V/Div) Time (5ms/Div) VOUT2 (1V/Div) LGATE2 (5V/Div) UGATE2 (10V/Div) Time (5ms/Div) VOUT1 Transient VOUT2 Transient VOUT1 (100mV/Div) VOUT2 (10mV/Div) IOUT1 (5A/Div) IOUT2 (5A/Div) VIN = 5V, VOUT = 3.3V, COUT = 3000μF VIN = 5V, VOUT = 2.5V, COUT = 3000μF Time (250us/Div) Time (250us/Div) DS9212-05 March 2007 www.richtek.com 8 Preliminary RT9212 POR (Start Up) VOUT3 Transient VIN = 5V, VOUT = 1.8V VOUT3 (200mV/Div) V CC (5V/Div) VOUT1 (2V/Div) IOUT3 (2A/Div) Time (2.5ms/Div) VOUT2 (2V/Div) Time (5ms/Div) POR (Rising/Falling) vs. Temperature 4.25 4.2 4.15 Frequency vs. Temperature 315 310 Frequency (kHz) 1 80 110 140 Rising 305 300 295 290 285 POR(V) 4.1 4.05 4 3.95 3.9 -40 -10 20 Falling 50 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Iocset & Temperature 55 Reference vs. Temperature 0.808 0.806 V OUT1 50 0.804 FB voltage(V) 0.802 0.8 0.798 0.796 0.794 0.792 0.79 Iocset ( μ A) 45 V OUT2 40 V OUT1 35 V OUT2 30 -40 -20 0 20 40 60 80 100 120 140 0.788 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) DS9212-05 March 2007 www.richtek.com 9 RT9212 Applications Information Inductor Preliminary The inductor is required to supply constant current to the output load. The inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. A larger value of inductance reduces ripple current and voltage. However, the larger value of inductance has a larger physical size, lower output capacitor and slower transient response time. A good rule for determining the inductance is to allow the peak-to-peak ripple current in the inductor to be approximately 30% of the maximum output current. The inductance value can be calculated by the following equation : (VIN − VOUT) × VOUT L= VIN × FS × ΔIOUT Where VIN is the input voltage, VOUT is the output voltage, FS is the switching frequency, The response time is the time required to slew the inductor current from an initial current value to the transient current level. The inductor limit input current slew rate during the load transient. Minimizing the transient response time can minimize the output capacitance required. The response time is different for application of load and removal of load to a transient. The following equations give the approximate response time for application and removal of a transient load : TRise = Where L × ΔIOUT VIN − VOUT , TFall = L × ΔIOUT VOUT TRise is the response time to the application of load, TFall is the response time to the removal of load, Δ IOUT is the transient load current step. Input Capacitor The input capacitor is required to supply the AC current to the Buck converter while maintaining the DC input voltage. The capacitor should be chosen to provide acceptable ripple on the input supply lines. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current. Place the small ceramic capacitors close to the MOSFETs and between the drain of Q1/Q3 and the source of Q2/Q4. The key specifications for input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and voltage rating of 1.5 times is a conservative guideline. The RMS current rating for the input capacitor of a buck regulator should be greater than approximately 0.5 the DC load current. Δ IOUT is the peak-to-peak inductor ripple current. The inductance value determines the converter's ripple current and the ripple voltage. The ripple current is calculated by the following equations : ΔI = (VIN − VOUT) × VOUT VIN × Fs × L Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values raise the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the RT9212 will provide 0% to 100% duty cycle in response to a load transient. www.richtek.com 10 DS9212-05 March 2007 Preliminary Output Capacitor The output capacitor is required to maintain the DC output voltage and supply the load transient current. The capacitor must be selected and placed carefully to yield optimal results and should be chosen to provide acceptable ripple on the output voltage. The key specification for output capacitor is its ESR. Low ESR capacitors are preferred to keep the output voltage ripple low. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. For transient response, a combination of low value, high frequency and bulk capacitors placed close to the load will be required. High frequency decoupling capacitors should be placed as close to the power pins of the load as possible. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. The capacitor value must be high enough to absorb the inductor's ripple current. The output ripple is calculated as : ΔVOUT = ΔIOUT × ESR Another concern is high ESR induced output voltage ripple may trigger UV or OV protections will cause IC shutdown. MOSFET The MOSFET should be selected to meet power transfer requirements is based on maximum drain-source voltage (VDS), gate-source drive voltage (VGS), maximum output current, minimum on-resistance (RDS(ON)) and thermal management. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The losses can be divided into conduction and switching losses. Conduction losses are related to the on resistance of MOSFET, and increase with the load current. Switching losses occur on each ON/OFF transition. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. RT9212 For the Buck converter the average inductor current is equal to the output load current. The conduction loss is defined as : PCD (high side switch) = IO2 * RDS(ON) * D PCD (low side switch) = IO2 * RDS(ON) * (1-D) The switching loss is more difficult to calculate. The reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turn-off delays and rise and fall times. With a linear approximation, the switching loss can be expressed as : PSW = 0.5 * VDS(OFF) * IO * (TRise + TFall) * F Where VDS(OFF) is drain to source voltage at off time, TRise is rise time, TFall is fall time, F is switching frequency. The total power dissipation in the switching MOSFET can be calculate as : PHigh Side Switch = IO2 * RDS(ON)* D + 0.5 * VDS(OFF)* IO* (TRise + TFall)* F PLow Side Switch = IO2 * RDS(ON) * (1-D) For input voltages of 3.3V and 5V, conduction losses often dominate switching losses. Therefore, lowering the RDS(ON) of the MOSFETs always improves efficiency. Feedback Compensation The RT9212 is a voltage mode controller; the control loop is a single voltage feedback path including an error amplifier and PWM comparator as Figure 1 shows. In order to achieve fast transient response and accurate output regulation, a adequate compensator design is necessary. The goal of the compensation network is to provide adequate phase margin (greater than 45 degrees) and the highest 0dB crossing frequency. And to manipulate loop frequency response that its gain crosses over 0dB at a slope of 20dB/dec. DS9212-05 March 2007 www.richtek.com 11 RT9212 Vin Preliminary Compensation Frequency Equations Lo PWM Vout Co ESR The compensation network consists of the error amplifier and the impedance networks ZC and ZF as Figure 2 shows. Zf C1 Zc R1 Zf + COMP1 R2 C2 VOUT PWM Comparator + - Zc EA + FB1 VREF Rf RT9212 VRAMP Compensator VREF Figure 1 Modulator Frequency Equations FP1 = 0 FZ1 = 1 2π × R2 × C2 1 2π × R2 (C1 // C2) Figure 2 The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This transfer function is dominated by a DC gain and the output filter (LO and CO), with a double pole frequency at FLC and a zero at FESR. The DC gain of the modulator is the input voltage (VIN) divided by the peakto-peak oscillator voltage VRAMP. The first step is to calculate the complex conjugate poles contributed by the LC output filter. The output LC filter introduces a double pole,−40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The Resonant frequency of the LC filter expressed as follows : FP1 = Figure 3 shows the DC-DC converter's gain vs. frequency. The compensation gain uses external impedance networks ZC and ZF to provide a stable, high bandwidth loop. High crossover frequency is desirable for fast transient response, but often jeopardize the system stability. In order to cancel one of the LC filter poles, place the zero before the LC filter resonant frequency. In the experience, place the zero at 75% LC filter resonant frequency.Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The second pole be place at half the switching frequency. 80 80 Loop Gain 60 40 40 20 Gain (dB) 0 -20 0 FP(LC) = 1 2π × LO × CO The next step of compensation design is to calculate the ESR zero. The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor expressed as follows : FZ(ESR) = 1 2π × CO × ESR Compensation Gain Modulator Gain -4040 -6060 1H 0z 10db(vo) v 10z 0H v b c m 2100l ) d(op) vb o d( 1k 10k Feuny rqec Frequency (Hz) 10H .Kz 1Kz 0H 100k 10H 0Kz 10H .Mz 1M Figure 3 www.richtek.com 12 DS9212-05 March 2007 Preliminary Reference Voltage Because one of the RT9212 regulators uses a low 35dB gain error amplifier, shown in Figure 4. The voltage regulation is dependent on VIN & VOUT setting.The FB reference voltage of 0.8V is trimmed at VIN = 5V & VOUT = 2.5V condition. In a fixed VIN = 5V application, the FB reference voltage vs. VOUT voltage can be calculated as Figure 5. R2 FB + - RT9212 2. There are two sets of critical components in a DC-DC converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. The others are the small signal components that connect to sensitive nodes or supply critical bypass current and signal coupling. Make all critical component ground connections with vias to GND plane. 3. Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. Place the output capacitors as close to the load as possible. 4. The inductor, output capacitor and the MOSFET should be as close to each other as possible. This helps to reduce the EMI radiated. 5. Place the switching MOSFET as close to the input capacitors as possible. The MOSFET gate traces to the IC must be as short, straight, and wide as possible. Use copper filled polygons on the top and bottom layers for the PHASE nodes. 6. Place the CBOOT as close as possible to the BOOT and PHASE pins. 7. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. Connect to the GND pin with a single trace, and connect this local GND trace to the output capacitor GND. 8. Minimize the leakage current paths on the OCSET/SD pin and locate the resistor as close to the OCSET/SD pin as possible because the internal current source is only 40μA. 9. In multilayer PCB, use one layer as ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. R1 1K REF 0.8V 56K + EA + - PWM RAMP 1.9V Figure 4 0.815 0.81 0.805 0.8 FB (V) 0.795 0.79 0.785 0.78 0.775 1 1.5 2 2.5 3 3.5 4 4.5 5 VOUT (V) Figure 5 Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. 1. Even though double-sided PCB is usually sufficient for a good layout, four-layer PCB is the optimum approach to reducing the noise. Use the two internal layers as the power and GND planes, the top layer for power connections with wide, copper filled areas, and the bottom layer for the noise sensitive traces. DS9212-05 March 2007 www.richtek.com 13 RT9212 Outline Dimension Preliminary D L E E1 e A A1 b A2 Symbol A A1 A2 b D e E E1 L Dimensions In Millimeters Min 0.850 0.050 0.800 0.190 7.700 0.650 6.300 4.300 0.450 6.500 4.500 0.750 Max 1.200 0.150 1.050 0.300 7.900 Dimensions In Inches Min 0.033 0.002 0.031 0.007 0.303 0.026 0.248 0.169 0.018 0.256 0.177 0.030 Max 0.047 0.006 0.041 0.012 0.311 24-Lead TSSOP Plastic Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com www.richtek.com 14 DS9212-05 March 2007