RT9602PS

RT9602 Dual Channel Synchronous-Rectified Buck MOSFET Driver General Description The RT9602 is a dual power channel MOSFET driver specifically designed to drive four power N-Channel MOSFETs in a synchronous-rectified buck converter topology. These drivers combined with RT9237/A and RT9241A/B series of Multi-Phase Buck PWM controllers provide a complete core voltage regulator solution for advanced microprocessors. The RT9602 can provide flexible gate driving for both high side and low side drivers. This gives more flexibility of MOSFET selection. The output drivers in the RT9602 have the capability to drive a 3000pF load with a 40nS propagation delay and 80nS transition time. This device implements bootstrapping on the upper gates with only a single external capacitor required for each power channel. This reduces implementation complexity and allows the use of higher performance, cost effective, N-Channel MOSFETs. Adaptive shoot-through protect-ion is integrated to prevent both MOSFETs from conducting simultaneously. The RT9602 can detect high side MOSFET drain-to-source electrical short at power on and pull the 12V power by low side MOS and cause power supply to go into over current shutdown to prevent damage of CPU. Features Drives Four N-Channel MOSFETs Adaptive Shoot-Through Protection Internal Bootstrap Devices Small SOP-14 Package 5V to 12V Gate-Drive Voltages for Optimal Efficiency Tri-State Input for Bridge Shutdown Supply Under-Voltage Protection Power ON Over-Voltage Protection RoHS Compliant and 100% Lead (Pb)-Free Applications Core Voltage Supplies for Intel Pentium® 4 and AMD® AthlonTM Microprocessors High Frequency Low Profile DC-DC Converters High Current Low Voltage DC-DC Converters Pin Configurations (TOP VIEW) PWM1 PWM2 GND LGATE1 PVCC PGND LGATE2 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC PHASE1 UGATE1 BOOT1 BOOT2 UGATE2 PHASE2 Ordering Information RT9602 Package Type S : SOP-14 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) SOP-14 Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100%matte tin (Sn) plating. DS9602-08 March 2007 www.richtek.com 1 www.richtek.com 2 RT9602 Optional +5V 1.2uH 12V 1000uF 1uF 12 UGATE1 20 PHB83N03LT 100 1uF 12V 1uF 5 1uF 11 BOOT1 PVCC 14 VCC Typical Application Circuit 10K 2uH PGOOD x1500uF 4 PHB95N03LT +5V 19 13 RT9602 LGATE1 VID4 1 VID3 2 VID4 VDD VID3 PGOOD PHASE1 PWM1 1 VID2 3K 3K 9 VSEN 1000uF GND 2uH ISP2 3K ISN2 16 3K 11 15 1uF x1500uF PHB95N03LT 3 VID2 2.4K VID1 4 VID1 VID0 5 15K 14 1uF 8 7 PHB83N03LT VID0 17 PWM1 18 ISP1 12 ISN1 PWM2 UGATE2 PHASE2 LGATE2 GND PGND BOOT2 10 Optional 2 6 66pF 13 COMP 7 FB 3 6 8 ADJ 2.4K 12V 18K 9 DVD 3K 10 SS 0.1uF PWM2 RT9241A/B VCORE DS9602-08 March 2007 RT9602 Functional Pin Description Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PWM1 PWM2 GND LGATE1 PVCC PGND LGATE2 PHASE2 UGATE2 BOOT2 BOOT1 UGATE1 PHASE1 VCC Channel 1 PWM Input Channel 2 PWM Input Ground Pin Lower Gate Drive of Channel 1 Upper and Lower Gate Driver Power Rail Lower Gate Driver Ground Pin Lower Gate Drive of Channel 2 Connect this pin to phase point of channel 2. Phase point is the connection point of high side MOSFET source and low side MOSFET drain Upper Gate Drive of Channel 2 Floating Bootstrap Supply Pin of Channel 2 Floating Bootstrap Supply Pin of Channel 1 Upper Gate Drive of Channel 1 Connect this pin to phase point of channel 1. Phase point is the connection point of high side MOSFET source and low side MOSFET drain Control Logic Power Supply Pin Function DS9602-08 March 2007 www.richtek.com 3 RT9602 Function Block Diagram VCC PVCC Internal 5V BOOT1 Shoot-Through Protection UGATE1 PHASE1 Power-On OVP 40K Shoot-Through Protection PGND PVCC Shoot-Through Protection 40K PWM2 40K Power-On OVP PVCC Shoot-Through Protection LGATE2 PVCC LGATE1 40K PWM1 Internal 5V Control Logic PGND BOOT2 UGATE2 PHASE2 GND PGND Absolute Maximum Ratings (Note 1) 15V VCC + 0.3V 15V GND - 0.3V to 7V −5V to 15V −10V to 30V 15V −0.3V to VCC+15V −0.3V to 42V VPHASE - 0.3V to VBOOT + 0.3V GND - 0.3V to VPVCC + 0.3V 127.67°C /W 0°C to 70°C 0°C to 125°C −40°C to 150°C 260°C 2kV 200V DS9602-08 March 2007 Supply Input Voltage, VCC ---------------------------------------------------------------------------Supply Voltage, PVCC -------------------------------------------------------------------------------BOOT Voltage, VBOOT-VPHASE ----------------------------------------------------------------------Input Voltage, VPWM -----------------------------------------------------------------------------------PHASE to GND DC ---------------------------------------------------------------------------------------------------------< 200ns --------------------------------------------------------------------------------------------------BOOT to PHASE --------------------------------------------------------------------------------------BOOT to GND DC ---------------------------------------------------------------------------------------------------------< 200ns --------------------------------------------------------------------------------------------------UGATE ---------------------------------------------------------------------------------------------------LGATE ---------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 3) SOP-14, θJA --------------------------------------------------------------------------------------------Ambient Temperature ---------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) --------------------------------------------------------------------------MM (Machine Mode) ----------------------------------------------------------------------------------www.richtek.com 4 RT9602 Electrical Characteristics Parameter VCC Supply Current Bias Supply Current Power Supply Current Power-On Reset VCC Rising Threshold Hysteresis PWM Input Maximum Input Current PWM Floating Voltage PWM Rising Threshold PWM Falling Threshold UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay Shutdown Window Output Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink RUGATE VVCC = 12V, VPVCC = 12V RUGATE VVCC = 12V, VPVCC = 12V RLGATE VVCC = 12V, VPVCC = 12V RLGATE VVCC = VPVCC = 12V ----1.75 2.8 1.9 1.6 3.0 5.0 3.0 3.0 Ω Ω Ω Ω Symbol Test Conditions Min Typ Max Units IVCC IPVCC fPWM = 250kHz, VPVCC = 12V, CBOOT = 0.1μF, RPHASE = 20Ω fPWM = 250kHz, VPVCC = 12V, CBOOT = 0.1μF, RPHASE = 20Ω --- 5.5 5.5 8 10 mA mA 8.6 0.6 9.9 1.35 10.7 -- V V μA V V V ns ns ns ns ns ns V VPWM = 0 or 5V Vcc = 12V 80 1.1 3.3 1.0 127 2.1 3.7 1.26 30 30 40 30 60 45 -- 150 3.7 4.3 1.5 ------3.7 VPVCC = VVCC = 12V, 3nF load VPVCC = VVCC = 12V, 3nF load VPVCC = VVCC = 12V, 3nF load VPVCC = VVCC = 12V, 3nF load VVCC = VPVCC = 12V, 3nF load VVCC = VPVCC = 12V, 3nF load ------1.26 Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θJA i s measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. DS9602-08 March 2007 www.richtek.com 5 RT9602 Application Information The RT9602 has power on protection function which held UGATE and LGATE low before VCC up cross the rising threshold voltage. After the initialization, the PWM signal takes the control. The rising PWM signal first forces the LGATE signal turns low then UGATE signal is allowed to go high just after a non-overlapping time to avoid shootthrough current. The falling of PWM signal first forces UGATE to go low. When UGATE and PHASE signal reach a predetermined low level, LGATE signal is allowed to turn high. The non-overlapping function is also presented between UGATE and LGATE signal transient. The PWM signal is recognized as high if above rising threshold and as low if below falling threshold. Any signal level in this window is considered as tri-state, which causes turn-off of both high side and low-side MOSFET. When PWM input is floating (not connected), internal divider will pull the PWM to 1.9V to give the controller a recognizable level. The maximum sink/source capability of internal PWM reference is 60μA. The PVCC pin provides flexibility of both high side and low side MOSFET gate drive voltages. If 8V, for example, is applied to PVCC, then high side MOSFET gate drive is 8V to 1.5V (approximately, internal diode plus series resistance voltage drop). The low side gate drive voltage is exactly 8V. The RT9602 implements a power on over-voltage protection function. If the PHASE voltage exceeds 1.5V at power on, the LGATE would be turn on to pull the PHASE low until the PHASE voltage goes below 1.5V. Such function can protect the CPU from damage by some short condition happened before power on, which is sometimes encountered in the M/B manufacturing line. Driving power MOSFETs The DC input impedance of the power MOSFET is extremely high. When Vgs at 12V (or 5V), the gate draws the current only few nanoamperes. Thus once the gate has been driven up to “ ON” ON level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. D1 Vi d1 Cgd1 Igd1 Ig1 Igs1 Ig2 Igd2 s1 L VO Cgs1 Cgd2 d2 g1 g2 D2 Igs2 Cgs2 s2 GND Vg1 Vphase +12V t Vg2 +12V t Figure1. The gate driver must supply Igs to Cgs and Igd to Cgd In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V.The operation consists of charging Cgd and Cgs. Cgs1 and Cgs2 are the capacitances from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs is referred as “ Ciss” which is the input capacitance. Cgd1 and Cgd2 are the capacitances from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as "Crss," the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2, are showed below www.richtek.com 6 DS9602-08 March 2007 RT9602 lgs1 = Cgs1 dVg1 Cgs1× 12 = dt tr1 dVg2 Cgs2 × 12 = dt tr2 from equation. (3) and (4) (1) -12 lgs1 = 380 × 10 × 12 = 0.326 (A) 14 × 10-9 (7) lgs2 = Cgs2 (2) lgs2 = According to the design of RT9602, before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET has to be off; and the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode "D2" had been turned on before high side MOSFETs turned on lgd1 = Cg1 dV = Cgd1 12V dt tr1 (3) 500 × 10-12 × (12+12) 30 × 10-9 = 0.4(A) (8) the total current required from the gate driving source is Ig1 = Igs1+Igd1 = (1.428+0.326) = 1.745(A) Ig2 = Igs2 +Igd2 = (0.88+0.4) = 1.28(A) (9) (10) By a similar calculation, we can also get the sink current required from the turned off MOSFET. Layout Consider Before the low side MOSFET is turned on, the Cgd2 have been charged to Vi. Thus, as Cgd2 reverses its polarity and g2 is charged up to 12V, the required current is Figure 2. shows the schematic circuit of a two-phase synchronous-buck converter to implement the RT9602. The converter operates for the input rang from 5V to 12V. D1 L1 R1 14 VCC PVCC 5 C7 10 1uF 12V Vin 12V lgd2 = Cgd2 dV = C Vi+12V gd2 dt tr2 (4) 1.2uH C1 1000uF Q1 L2 C2 1uF Cb1 1uF 11 BOOT1 12 PHB83N03LT UGATE1 PHASE1 It is helpful to calculate these currents in a typical case. Assume a synchronous rectified BUCK converter, input voltage Vi = 12V, Vg1 = Vg2 = 12V. The high side MOSFET is PHB83N03LT whose Ciss = 1660pF, Crss = 380pF,and tr = 14nS. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF, and tr = 30nS, from the equation (1) and (2) we can obtain -12 lgs1 = 1660 × 10 × 12 = 1.428 (A) 14 × 10-9 -12 = 2200 × 10 × 12 = 0.88 (A) 30 × 10-9 13 2uH C5 1500uF Q2 PHB95N03LT PWM1 1 PWM1 RT9602 4 LGATE1 PWM2 9 C3 1000uF Q3 L3 2uH PHB83N03LT 2 PWM2 C4 1uF UGATE2 PHASE2 LGATE2 GND PGND 3 6 8 7 C6 1500uF Q4 Cb2 1uF BOOT2 10 D2 PHB95N03LT (5) V CORE Figure 2. Two- Phase Synchronous-Buck Converter Circuit (6) lgs2 DS9602-08 March 2007 www.richtek.com 7 RT9602 When layout the PCB, it should be very careful. The powercircuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 and Q3, Q4, L4 should be very close. The connection from Q1, and Q3 drain to positive sides of C1, C2, C3, and C4; the connection from Q2, and Q4 source to the negative sides of C1, C2, C3, and C4 should be as short as possible. Next, the trace from Ugate1, Ugate2, Lgate1, and Lgate2 should also be short to decrease the noise of the driver output signals. Phase1 and phase2 signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C7 should be connected to PGND directly. Furthermore, the bootstrap capacitors (Cb1, Cb2) should always be placed as close to the pins of the IC as possible. Select the Bootstrap Capacitor Figure 3. shows part of the bootstrap circuit of RT9602. The VCB (the voltage difference between BOOT1 and PHASE1 on RT9602) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance CB has to be selected properly. It is determined by following constraints. PVCC VIN BOOT1 PWM2 PWM1 RT9602 0.01uF In practice, a low value capacitor C B w ill lead the overcharging that could damage the IC. Therefore to minimize the risk of overcharging and reducing the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low-ESR capacitor should be used to provide good local de-coupling. Here, to adopt either a ceramic or tantalum capacitor is suitable. Power Dissipation For not exceeding the maximum allowable power dissipation to drive the IC beyond the maximum recommended operating junction temperature of 125°C, it is necessary to calculate power dissipation appropriately. This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 4. shows the power dissipation test circuit. CL and CU are the UGATE and LGATE load capacitors, respectively. The bootstrap capacitor value is 0.01μF. +5V or +12V +5V or +12V 0.01uF UGATE1 1uF +12V PHASE1 1uF LGATE1 CL 2N7000 CU 2N7000 33 UGATE1 PHASE1 PVCC LGATE1 PGND CB + VCB PGND UGATE2 2N7000 CU PHASE2 GND LGATE2 CL 2N7000 33 Figure 4. RT9602 Power Dissipation Test Circuit Figure 5. shows the power dissipation of the RT9602 as a function of frequency and load capacitance. The value of the CU and CL are the same and the frequency is varied from 100kHz to 600kHz. PVCC and VCC is 12V and connected together. Figure 6.shows the same characterization for PVCC tied to 5V instead of 12V. Figure 3. Part of Bootstrap Circuit of RT9602 www.richtek.com 8 DS9602-08 March 2007 RT9602 Power Dissipation vs. Frequency 800 The method to improve the thermal transfer is to increase the PCB copper area around the RT9602, first. Then, adding a ground pad under IC to transfer the heat to the peripheral of the board. Power on Over-Voltage Protection Function The RT9602 provides a protect function which can avoid some short condition happened before power on. The following discussion about the power on over-voltage protection function of RT9602 is based on the experiments of the high side MOSFET directly shorted to 12V. The test circuit as shown in the typical application circuit (with RT9241A/B dual-channel synchronous-rectified buck controller) the VCC and the phase signals are measured on the VCC pin and the phase pin of RT9602. The LGATE signal is measured on the gate terminal of MOSEFET. CU=CL 700 600 =5nF CU=CL=4nF CU=CL=3nF CU=CL=2nF CU=CL=1nF Power (mW) 500 400 300 200 100 PVcc=Vcc=12V 0 0 100 200 300 400 500 600 Frequency (kHz) Figure 5. Power Dissipation vs. Frequency (RT9602) Power Dissipation vs. Frequency 250 CU=CL=4nF 240 230 CU=CL =5nF CU=CL=2nF VVcc > PPEASE > Power(mW) 220 210 200 190 180 CU=CL=1nF lLGATE > CU=CL=3nF hrountCurrent > Through 12V RT9809-20CV 170 50 100 150 200 250 300 350 400 450 Time (50ms) Frequency(kHz) Figure 7 High Side Direct Short Figure 6. Power Dissipatin vs. Frequency, PVCC = 5V The operating junction temperature can be calculated from the power dissipation curves (Figure 5 and Figure 6). Assume the RT9602’ s PVCC = VCC=12V, operating frequency is 200kHz, and the CU=CL=1.5nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 5, the power dissipation is 500mW. In RT9602, the package thermal resistance θ JA i s 127.67 °C/W, the operating junction temperature is calculated as: TJ = 127.67°C/W x 500mW+ 25°C = 88.84°C where the 25°C is the ambient temperature. (11) VVcc > PPEAS > lLGATE > l VCORE> Time (50ms) Figure 8. High Side Direct Short DS9602-08 March 2007 www.richtek.com 9 RT9602 VVcc > PPEASE > lLGATE > lPWM1 > Time (25ms) Figure 9. High Side Direct Short Referring to Figure 7, when VCC exceeds 1.5V, RT9602 turns on the LGATE to clamp the Phase through the low side MOSFET. During the turn-on of the low side MOSFET, the current of ATX 12V is limited at 25A although the maximum current of ATX 12V listed on the case of ATX is 15A. After the ATX 12V shuts down, the VCC falls slowly. Please note that the trigger point of RT9602 is at 1.5V VCC, and the clamped value of phase is at about 2.4V. Next, reference to Figure 8, it is obvious that since the Phase voltage increases during the power-on, the VCORE increases correspondingly, but is gradually decreased as LGATE and VCC decrease. In Figure 9, during the turn-on of the low side MOSFET, the VCC is much less than 12V, thus the RT9241A/B keeps the PWM signal at high impedance state. www.richtek.com 10 DS9602-08 March 2007 RT9602 Outline Dimension A H M J B F C I D S ymbol A B C D F H I J M Dimensions In Millimeters Min 8 .534 3 .810 1 .346 0 .330 1 .194 0 .178 0 .102 5 .791 0 .406 Max 8.738 3.988 1.753 0.508 1.346 0.254 0.254 6.198 1.270 Dimensions In Inches Min 0.336 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 Max 0.344 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050 14-Lead SOP Plastic Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com DS9602-08 March 2007 www.richtek.com 11