BD9011KV-E2

BD9775FV TECHNICAL NOTE Large Current External FET Controller Type Switching Regulator Step-down, High-efficiency Switching Regulators (Controller type) BD9011EKN , BD9011KV , BD9775FV ■ BD9011EKN, BD9011KV ●Overview The BD9011EKN/KV is a 2-ch synchronous controller with rectification switching for enhanced power management efficiency. It supports a wide input range, enabling low power consumption ecodesign for an array of electronics. ●Features 1) Wide input voltage range: 3.9V to 30V 2) Precision voltage references: 0.8V±1% 3) FET direct drive 4) Rectification switching for increased efficiency 5) Variable frequency: 250k to 550kHz (external synchronization to 550kHz) 6) Built-in selected OFF latch and auto remove over current protection 7) Built-in independent power up/power down sequencing control 8) Make various application , step-down , step-up and step-up-down 9) Small footprint packages: HQFN36V, VQFP48C ●Applications Car audio and navigation systems, CRTTV，LCDTV，PDPTV，STB，DVD，and PC systems，portable CD and DVD players, etc. ●Absolute Maximum Ratings (Ta=25℃) Parameter EXTVCC Voltage Symbol EXTVCC VCCCL1,2 Voltage VCCCL1,2 CL1,2 Voltage CL1,2 SW1,2 Voltage SW1,2 Unit Parameter Symbol 34 *1 V COMP1,2 Voltage COMP1,2 34 *1 V DET1,2 Voltage DET1,2 V RT､SYNC Voltage RT､SYNC Rating 34 34 *1 V *1 V VREG5 V *2 BOOT1,2 40 BOOT1,2-SW1,2 Voltage BOOT1,2-SW1,2 7 STB, EN1,2 Voltage STB, EN1,2 VCC V VREG5,5A VREG5,5A 7 V VREG33 VREG33 VREG5 V Operating temperature Storage temperature SS1,2､FB1,2 SS1,2､FB1,2 VREG5 V Junction temperature V Unit 0.875 （HQFN36V） BOOT1,2 Voltage *1 Rating Power Dissipation W Pd *2 1.1 （VQFP48C） W Topr -40 to +105 ℃ Tstg -55 to +150 ℃ Tj +150 ℃ *1 Regardless of the listed rating, do not exceed Pd in any circumstances. *2 Mounted on a 70mm x 70mm x 0.8mm glass-epoxy board. De-rated at 7.44mW/℃（HQFN36V） or 8.8mW/℃（VQFP48C） above 25℃. Sep. 2008 ●Operating conditions (Ta=25℃) Parameter Symbol Min. 3.9 Typ. Max. Unit *1 *2 12 30 V Input voltage 1 EXTVCC Input voltage 2 VCC 3.9 *1 *2 12 30 V BOOT－SW voltage BOOT－SW 4.5 5 VREG5 V Carrier frequency OSC 250 300 550 kHz Synchronous frequency SYNC OSC - 550 kHz Synchronous pulse duty Duty 40 50 60 ％ Min OFF pulse TMIN - 100 - nsec ★This product is not designed to provide resistance against radiation. *1 After more than 4.5V, voltage range. *2 In case of using less than 6V, Short to VCC, EXTVCC and VREG5. ●Electrical characteristics (Unless otherwise specified, Ta=25℃ VCC=12V STB=5V EN1,2=5V) Parameter Symbol VIN bias current Shutdown mode current Limit Unit Conditions Min. Typ. Max. IIN - 5 10 mA IST - 0 10 μA Feedback reference voltage VOB 0.792 0.800 0.808 V Feedback reference voltage (Ta=-40 to 105℃) VOB+ 0.784 0.800 0.816 V Open circuit voltage gain Averr - 46 - dB VO input bias current IVo+ - - 1 μA HG high side ON resistance HGhon - 1.5 - Ω HG low side ON resistance HGlon - 1.0 - Ω LG high side ON resistance LGhon - 1.5 - Ω LG low side ON resistance LGlon - 0.5 - Ω Carrier frequency FOSC 270 300 330 kHz RT=100 kΩ Synchronous frequency Fsync - 500 - kHz RT=100 kΩ,SYNC=500kHz CL threshold voltage Vswth 70 90 110 ｍV CL threshold voltage （Ta=-40 to 105℃） Vswth+ 67 90 113 ｍV VREG5 output voltage VREG5 4.8 5 5.2 V IREF=6mA VREG33 reference voltage VREG33 3.0 3.3 3.6 V IREG=6mA VREG5 threshold voltage VREG_UVLO 2.6 2.8 3.0 V VREG:Sweep down VREG5 hysteresis voltage DVREG_UVLO 50 100 200 mV VREG:Sweep up ISS 6.5 10 13.5 μA VSS=1V 14 μA VSS=1V,Ta=-40 to 105℃ VSTB=0V ［Error Amp Block］ Ta=-40 to 105℃ ※ ［FET Driver Block］ ［Oscillator］ ［Over Current Protection Block］ Ta=-40 to 105℃ ※ ［VREG Block］ ［Soft start block］ Charge current Charge current ISS+ 6 10 (Ta=-40 to 105℃) Note: Not all shipped products are subject to outgoing inspection. 2/29 ※ ●Reference data (Unless otherwise specified, Ta=25℃) 100 5.0V 90 5 80 80 70 1.8V 60 2.6V 3.3V 3.3V 1.2V 50 40 30 60 50 40 30 20 20 VIN=12V 10 Io=2A 10 0 1 2 OUTPUT CURRENT：Io[A] 6 3 9 12 15 18 21 INPUT VOLTAGE ： VIN[V] 0.804 0.800 0.796 0.792 0.788 0.784 10 35 60 85 10 20 INPUT VOLTAGE：VIN[V] 330 100 90 80 70 110 AMBIENT TEMPERATURE ： Ta[℃] 5.25 RT=100kΩ 320 310 300 290 280 270 -40 Fig.4 Reference voltage vs. temperature characteristics 30 Fig.3 Circuit current 60 -15 1 0 OSILATING FREQUENCY ： FOSC[kHz] 過電流検出電圧 ： Vswth[mV] 0.808 -40 2 24 110 0.812 -40℃ 3 Fig.2 Efficiency 2 Fig.1 Efficiency 1 0.816 25℃ 105℃ 4 0 0 0 REFERENCE VOLTAGE ： VOB[V] 5.0V 70 EFFICIENCY[%] EFFICIENCY[%] 6 90 CIRCUIT　CURRENT[mA] 100 -15 10 35 60 85 110 -40 -15 10 35 60 85 110 AMBIENT TEMPERATURE ： Ta[℃] AMBIENT TEMPERATURE ： Ta[℃] Fig.5 Over current detection vs. temperature characteristics Fig.6 Frequency vs. temperature characteristics 3.0 6 4.50 4.25 4.00 3.75 VREG33 3.50 2.5 5 VREG5 OUT PUT VOLTAGE ： Vo[V] 4.75 OUT PUT VOLTAGE ： Vo[V] OUT PUT VOLTAGE ： Vo[V] 5.00 5.0V 4 3 3.3V 2 3.00 -40 -15 10 35 60 85 110 LOFF=H 1.0 LOFF=L 0.0 0 0 AMBIENT TEMPERATURE ： Ta[℃] 1.5 0.5 1 3.25 RCL=15mΩ 2.0 Fig.7 Internal Reg vs. temperature characteristics 5 10 15 20 INPUT VOLTAGE ： VIN[V] 0 25 1 2 3 4 5 6 OUTPUT CURRENT: Io[A] Fig.8 Line regulation Fig.9 Load regulation OUTPU T　VOLTAGE ： Vo[V] 6 50mV/div 5 VOUT 50mV/div VOUT 4 105℃ 3 25℃ 2 -40℃ 1 IOUT 0 0 2 4 INPUT VOLTAGE：V EN[V] 1A/div 6 Fig.10 EN threshold voltage Fig.11 Load transient response 1 3/29 IOUT 1A/div Fig.12 Load transient response 2 ●Block diagram (Parentheses indicate VQFP48C pin numbers) EXTVCC STB VCC RT SYNC 10 (25) 15 (33) 16 (34) 22 (41) 32 (7) 5V Reg VREG5 3.3V Reg 24(44) 5(19) B.G 17(35) VCCCL2 31(5) CL2 30(3) BOOT2 29(2) OUTH2 28(1) SW2 27(48) 2.7V 25(46) DGND2 26(47) FB2 SS2 21(39) Set Set DRV Reset Reset TSD UVLO TSD UVLO Q Reset Set － ＋ ＋ PW M COMP Slope Slope PW M COMP BOOT1 OUTH1 SW 1(13) SW1 LOGIC 4(17) VREG5A 3(15) OUTL1 Q Set Reset UVLO Ｏ 2(14) DGND1 6(21) 8(23) FB1 SS1 7(22) COMP1 0.8V 0.8V 20(38) VCCCL1 CL1 35(11) Err Amp Err Amp 33(8) 34(10) 36(12) DRV SW 19(37) COMP2 OCP LOGIC LLM OSC OCP VREG5 OUTL2 TSD TSD UVLO VREG33 SYNC Q Q Set Reset Sequence DET Reset Set Sequence DET 0.56V 0.56V 18 (36) 14 (31) 12 (27) DET2 LOFF EN2 11 (26) (30) 13 (29) 9 (24) EN1 (GNDS) GND DET1 Fig-13 ●Pin configuration ●PIN function table 15 RT Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LOFF 14 LOFF 13 GND 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 RT SYNC LLM DET2 SS2 COMP2 FB2 EXTVCC － VREG5 OUTL2 DGND2 SW2 OUTH2 BOOT2 CL2 VCCCL2 VCC VCCCL1 CL1 BOOT1 OUTH1 24 23 SS2 VREG5 25 COMP2 OUTL2 26 FB2 DGND2 27 EXTVCC SW2 BD9011EKN（HQFN36V） 22 21 20 19 OUTH2 28 18 DET2 BOOT2 29 17 LMM CL2 30 16 SYNC VCCCL2 31 VCC 32 VCCCL1 33 4 5 6 7 8 9 DET1 3 SS1 2 COMP1 1 FB1 10 STB VREG33 OUTH1 36 VREG5A 11 EN1 OUTL1 BOOT1 35 DGND1 12 EN2 SW1 CL1 34 Fig-14 4/29 Pin name Function SW1 DGND1 OUTL1 VREG5A VREG33 FB1 COMP1 SS1 DET1 STB EN1 EN2 GND High side FET source pin 1 Low side FET source pin 1 Low side FET gate drive pin 1 FET drive REG input Reference input REG output Error amp input 1 Error amp output 1 Soft start setting pin 1 FB detector output 1 Standby ON/OFF pin Output 1ON/OFF pin Output 2ON/OFFpin Ground Over current protection OFF latch function ON/OFF pin Switching frequency setting pin External synchronous pulse input pin Built-in pull-down resistor pin FB detector output 2 Soft start setting pin 2 Error amp output 2 Error amp input 2 External power input pin N.C. FET drive REG output Low side FET gate drive pin 2 Low side FET source pin 2 High side FET source pin 2 Hi side FET gate drive pin 2 OUTH2 driver power pin Over current detector setting pin 2 Over current detection VCC2 Input power pin Over current detection VCC1 Over current detector setting pin 1 OUTH1 driver power pin High side FET gate drive pin 1 ●Pin configuration ●Pin function table DET2 LLM SYNC RT N.C LOFF GNDS GND N.C EN2 EN1 STB BD9011KV（VQFP48C） 36 35 34 33 32 31 30 29 28 27 26 25 24 DET1 SS2 37 23 SS1 COMP2 38 FB2 39 22 COMP1 N.C 40 21 FB1 EXTVCC 41 20 N.C N.C 42 19 VREG33 N.C 43 18 N.C 17 VREG5A VREG5 44 16 N.C N.C 45 OUTL2 46 15 OUTL1 DGND2 47 14 DGND1 13 SW1 1 2 3 4 5 6 7 8 9 10 11 12 OUTH2 BOOT2 CL2 N.C VCCCL2 N.C VCC VCCCL1 N.C CL1 BOOT1 OUTH1 SW2 48 Fig-15 ●Block functional descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin name Function OUTH2 BOOT2 CL2 N.C VCCCL2 N.C VCC VCCCL1 N.C CL1 BOOT1 OUTH1 SW1 DGND1 OUTL1 N.C VREG5A N.C VREG33 N.C FB1 COMP1 SS1 DET1 STB EN1 EN2 N.C GND GNDS High side FET gate drive pin 2 OUTH2 driver power pin Over current detection pin 2 Non-connect (unused) pin Over current detection VCC2 Non-connect (unused) pin Input power pin Over current detection CC1 Non-connect (unused) pin Over current detection setting pin 1 OUTH1 driver power pin High side FET gate drive pin 1 High side FET source pin 1 Low side FET source pin 1 Low side FET gate drive pin 1 Non-connect (unused) pin FET drive REG input Non-connect (unused) pin Reference input REG output Non-connect (unused) pin Error amp input 1 Error amp output 1 Soft start setting pin 1 FB detector output 1 Standby ON/OFF pin Output 1 ON/OFF pin Output 2 ON/OFF pin Non-connect (unused) pin Ground Sense ground Over current protection OFF latch function ON/OFF pin Non-connect (unused) pin Switching frequency setting pin External synchronous pulse input pin Built-in pull-down resistor pin FB detector output 2 Soft start setting pin 2 Error amp output 2 Error amp input 2 Non-connect (unused) pin External power input pin Non-connect (unused) pin Non-connect (unused) pin FET drive REG output Non-connect (unused) pin Low side FET gate drive pin 2 Low side FET source pin 2 High side FET source pin 2 31 LOFF 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 N.C RT SYNC LLM DET2 SS2 COMP2 FB2 N.C EXTVCC N.C N.C VREG5 N.C OUTL2 DGND2 SW2 ・Error amp The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which is used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage. ・Oscillator (OSC) Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250kHz and 550kHz. ・ SLOPE The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator. ・PWM COMP The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from the SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum. ・Reference voltage (5Vreg，33Vreg) This block generates the internal reference voltages: 5V and 3.3V. ・External synchronization (SYNC) Determines the switching frequency, based on the external pulse applied. ・Over current protection (OCP) Over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When over current protection is active, Duty is low, and output voltage also decreases. When LOFF=L, the output voltage has fallen to 70% or below and output is latched OFF. The OFF latch mode ends when the latch is set to STB, EN. ・Sequence control (Sequence DET) Compares FB voltage with reference voltage (0.56V) and outputs the result as DET. ・Protection circuits (UVLO/TSD) The UVLO lock out function is activated when VREG falls to about 2.8V, while TSD turns outputs OFF when the chip temperature reaches or exceeds 150℃. Output is restored when temperature falls back below the threshold value. 5/29 ●Application circuit example (Parentheses indicate VQFP48C pin numbers) VIN(12V) 100uF 36 35 34 33 32 31 30 29 28 (12) (11) (10) (8) (7) (5) (3) (2) (1) CL1 VCC VCCCL2 CL2 BOOT2 OUTH1 OUTL1 OUTL2 25(46) 4(17) VREG5A VREG5 24(44) 5(19) VREG33 6(21) FB1 7(22) COMP1 8(23) SS1 9(24) DET1 STB 0.1uF (SLF12565：TDK) 0.1 uF EXTVCC 22(41) FB2 21(39) COMP2 20(38) 19(37) SS2 DET2 10 11 12 13 14 15 16 17 18 (25) (26) (27) (29) (31) (33) (34) (35) (36) 10uH Vo(3.3V/3A) RB051 L-40 220uF (OS ｺﾝ) 47kΩ 1uF 23 LLM 39kΩ 26(47) DGND1 SYNC 13kΩ DGND2 2(14) 3(15) RT 1uF 27(48) LOFF 1uF SW2 GND (OS ｺﾝ) SW1 EN2 220uF 1(13) RB160 VA-40 OUTH2 EN1 RB051 L-40 SP8K2 VCCCL1 0.1 uF 10uH 100Ω 1nF BOOT1 RB160 VA-40 15000pF uF 1nF (SLF12565：TDK) 68kΩ 15mΩ 10 Ω 0.33 100Ω SP8K2 Vo(5V/3A) 15mΩ 0.33uF 15kΩ 39kΩ 15000pF 0.1uF 100kΩ Fig-16A（Step-Down：Cout=OS Capacitor） There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications. VIN(12V) 100uF 1kΩ 30 29 28 (5) (3) (2) (1) VCCCL1 VCC VCCCL2 CL2 BOOT2 1(13) SW1 2(14) DGND1 3(15) 4(17) 5(19) VREG33 6(21) FB1 7(22) COMP1 8(23) 0.1uF 9(24) RB160 VA-40 OUTH2 SW2 27(48) DGND2 26(47) OUTL1 OUTL2 25(46) VREG5A VREG5 24(44) 23 SS1 EXTVCC 22(41) FB2 21(39) COMP2 20(38) 19(37) LLM 10000pF 31 (7) OUTH1 330pF 12kΩ 32 (8) SYNC 1uF 33 RT 1uF 34 (10) LOFF (C2012JB 0J106K ：TDK) 35 (11) GND 30uF 36 (12) EN2 15kΩ 150Ω SP8K2 CL1 RB051 L-40 3300pF 100Ω 1nF BOOT1 RB160 VA-40 0.1 uF 10uH uF 1nF EN1 Vo(1.8V/2A) 23mΩ 10 Ω 0.33 100Ω SP8K2 (SLF10145：TDK) 23mΩ SS2 DET2 10 11 12 13 14 15 16 17 18 (25) (26) (27) (29) (31) (33) (34) (35) (36) DET1 STB (SLF10145：TDK) 0.1 uF 10uH Vo(2.5V/2A) RB051 L-40 30uF 1uF 43 kΩ (C2012JB 0J106K ：TDK) 1000pF 510Ω 0.33uF 330pF 20kΩ 3.3kΩ 3300pF 0.1uF 100kΩ Fig-16B（Step-Down：Cout=Ceramic Capacitor） There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications. 6/29 VIN(12V) 100uF 0.33 100Ω uF ＊REGSPIC 100Ω 1nF 33 32 31 30 29 28 (8) (7) (5) (3) (2) (1) 4(17) VREG5A 5(19) VREG33 6(21) FB1 7(22) COMP1 9(24) VCC VCCCL2 DGND2 26(47) OUTL2 25(46) VREG5 SS1 24(44) 22(41) FB2 21(39) COMP2 20(38) SS2 DET2 11 12 13 14 15 16 17 18 (25) (26) (27) (29) (31) (33) (34) (35) (36) Vo(12V/1A) Co2 EXTVCC 10 DET1 STB (SLF12565：TDK) L2 27uH Do3 0.1 uF 1uF 91 kΩ 220 uF RB051 L-40 23 LLM 8(23) 0.1uF CL1 OUTL1 27(48) SYNC 10kΩ DGND1 SW2 RT 1000pF 2(14) 3(15) OUTH2 LOFF 1uF SW1 GND 1uF 1(13) RB160 VA-40 EN2 5.1kΩ 22000pF 34 (10) OUTH1 680 kΩ 23.5kΩ 35 (11) VCCCL1 1uF 220uF 1000pF 36 (12) BOOT1 RSS 065N03 EN1 Co1 TM SP8K2 1nF CL2 RB051L-40 10mΩ 10 Ω BOOT2 Vo(24V/1A) 10mΩ L1 (SLF12565：TDK) 27uH 3300pF 10kΩ 0.33uF 1000pF 6.2kΩ 4.7kΩ 19(37) 22000pF 0.1uF ＊ 100kΩ REGSPICTM is Trade Mark of RHOM Fig-16C（Step-Down：Low Input Voltage） There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications. VIN(5V) 100uF 4700pF 3.3kΩ 30 29 28 (5) (3) (2) (1) CL1 VCC VCCCL2 CL2 BOOT2 OUTH1 1(13) SW1 2(14) DGND1 3(15) OUTL1 4(17) VREG5A 5(19) VREG33 6(21) FB1 7(22) COMP1 8(23) 0.1uF 9(24) SW2 27(48) DGND2 26(47) OUTL2 25(46) VREG5 24(44) 23 SS1 EXTVCC 22(41) FB2 21(39) COMP2 20(38) SS2 DET2 10 11 12 13 14 15 16 17 18 (25) (26) (27) (29) (31) (33) (34) (35) (36) DET1 STB RB160 VA-40 0.1uF OUTH2 LLM 100pF 12kΩ 31 (7) SYNC 1uF 32 (8) RT 1uF 33 LOFF 100Ω 34 (10) GND (ｾﾗｺﾝ) 35 (11) EN2 30uF 36 VCCCL1 0.1uF SP8K2 EN1 15kΩ 100Ω 1nF (12) BOOT1 RB160 VA-40 RB051 L-40 3300pF uF 1nF (SLF10145：TDK) 6.8uH 23mΩ 10 Ω 0.33 100Ω SP8K2 Vo(1.8V/2A) 23mΩ (SLF10145：TDK) 6.8uH Vo(2.5V/2A) RB051 L-40 30uF (ｾﾗｺﾝ) 1uF 1000pF 300Ω 0.33uF 33pF 19(37) 43 kΩ 20kΩ 10kΩ 2200pF 0.1uF 100kΩ Fig-16D（Step-Up：and Step-Up-Down） There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications. 7/29 ●Application component selection (1) Setting the output L value The coil value significantly influences the output ripple current. Thus, as seen in equation (5), the larger the coil, and the higher the switching frequency, the lower the drop in ripple current. ΔIL Fig-17 ΔIL = （VCC-VOUT）×VOUT L×VCC×f [A]・・・ （5） VCC IL The optimal output ripple current setting is 30% of maximum current. ΔIL = 0.3×IOUTmax.[A]・・・（6） VOUT L Co L= Fig-18 （VCC-VOUT）×VOUT ΔIL×VCC×f （ΔIL：output ripple current Output ripple current [H]・・・ （7） f：switching frequency） ※Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease efficiency. Please establish sufficient margin to ensure that peak current does not exceed the coil current rating. ※Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency. (2) Setting the output capacitor Co value Select the output capacitor with the highest value for ripple voltage (VPP) tolerance and maximum drop voltage (at rapid load change). The following equation is used to determine the output ripple voltage. Vo ΔIL Step down ΔVPP = ΔIL × RESR + 1 × Co × f Vcc [V] Note: f：switching frequency Be sure to keep the output Co setting within the allowable ripple voltage range. ※Please allow sufficient output voltage margin in establishing the capacitor rating. Note that low-ESR capacitors enable lower output ripple voltage. Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please factor in the conditions described in the capacitance equation (9) for output capacitors, below. Co ≦ TSS × (Limit – IOUT) Tss： soft start time ・・・ （9） VOUT ILimit：over current detection value（2/16）reference Note: less than optimal capacitance values may cause problems at startup. (3) Input capacitor selection VIN Cin VOUT L Co The input capacitor serves to lower the output impedance of the power source connected to the input pin (VCC). Increased power supply output impedance can cause input voltage (VCC) instability, and may negatively impact oscillation and ripple rejection characteristics. Therefore, be certain to establish an input capacitor in close proximity to the VCC and GND pins. Select a low-ESR capacitor with the required ripple current capacity and the capability to withstand temperature changes without wide tolerance fluctuations. The ripple current IRMSS is determined using equation (10). IRMS = IOUT × Fig-19 Input capacitor VOUT（VCC - VOUT） [A]・・・ （10） VCC Also, be certain to ascertain the operating temperature, load range and MOSFET conditions for the application in which the capacitor will be used, since capacitor performance is heavily dependent on the application’s input power characteristics, substrate wiring and MOSFET gate drain capacity. 8/29 (4) Feedback resistor design Please refer to the following equation in determining the proper feedback resistance. The recommended setting is in a range between 10kΩ and 330kΩ. Resistance less than 10kΩ risks decreased power efficiency, while setting the resistance value higher than 330kΩ will result in an internal error amp input bias current of 0.2uA increasing the offset voltage. Vo Internal ref. 0.8V Vo = R8 R8 +R9 R9 × 0.8 [V] ・・・（11） FB R9 Fig-20 (5) Setting switching frequency The triangular wave switching frequency can be set by connecting a resistor to the RT 15(33) pin. The RT sets the frequency by adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in determining proper RT resistance, noting that the recommended resistance setting is between 50kΩ and 130kΩ. Settings outside this range may render the switching function inoperable, and proper operation of the controller overall cannot be guaranteed when unsupported resistance values are used. 550 周波数 [ kHz ] 500 450 400 350 300 250 50 60 70 80 90 RT [ kΩ] 100 110 120 130 Fig-21 RT vs. switching frequency (6) Setting the soft start delay The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup. The figure below shows the relation between soft start delay time and capacitance, which can be calculated using equation (12) at right. DELAY TIME[ms] 10 1 0.8V(typ.)×CSS TSS = [sec]・・・(12) ISS(10μA Typ.) 0.1 0.01 0.001 0.01 0.1 SS CAPACITANCE[uF] Fig-22 SS capacitance vs. delay time Recommended capacitance values are between 0.01uF and 0.1uF. Capacitance lower than 0.01uF may generate output overshoots. Please use high accuracy components (such as X5R) when implementing sequential startups involving other power sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on input voltage, output voltage and capacitance, coils and other characteristics. 9/29 (7) Setting over current detection values The current limit value（ILimit）is determined by the resistance of the RCL established between CL and VCCCL. VCCCL VIN Over current detection point IL RCL CL IL Vo ILimit = L Fig-23 90m RCL [A]・・・(13) Fig-24 There are 2 current limit function (ON/OFF control type and OFF latch type) toggled by LOFF pin. ・LOFF=L (0