ML610Q411-NNNTBZ03A7

Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor" and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd." Furthermore, there are no changes to the documents relating to our products other than the company name, the company trademark, logo, etc. Thank you for your understanding. LAPIS Technology Co., Ltd. October 1, 2020 FEDL610Q411-04 Issue Date: July.13, 2015 ML610Q411/Q412 8-bit Microcontroller with a Built-in LCD driver GENERAL DESCRIPTION ML610Q411/Q412 is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), buzzer driver, battery level detect circuit, RC oscillation type A/D converter, 12-bit successive approximation type A/D converter, and LCD driver, are incorporated around LAPIS Semiconductor -original 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask ROM and is most suitable for battery-driven applications. The on-chip debug function that is installed enables program debugging and programming. M L610Q411/Q412 has a dual clock, runs at 32.768kHz crystal oscillation clock or a built-in 500kHz RC oscillation clock, used for a system requires the accurate clock or timer. FEATURES • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system: 16-bit instructions − Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − On-Chip debug function − Minimum instruction execution time 30.5 µs (@32.768 kHz system clock) 2µs (@500kHz system clock) • Internal memory − Internal 16KBbyte Flash ROM (8K×16 bits) (including unusable 1KByte TEST area) − Internal 1KByte Data RAM (1024×8 bits) • Interrupt controller − 2 non-maskable interrupt sources Internal source: 1 (Watch dog timer) External source: 1 (NMI) − 19 maskable interrupt sources Internal sources: 15 (SSIO, SA-A/D converter, I2C, Timer0, Timer1, Timer2, Timer3, 1kHz timer, UART, RC-A/D converter, PWM, TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz) External sources: 4 (P00, P01, P02, P03) • Time base counter − Low-speed time base counter ×1 channel Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) − High-speed time base counter ×1 channel 1/36 FEDL610Q411-04 ML610Q411/ML610Q412 • Watchdog timer − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timers − 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3) − Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3) • 1 kHz timer − 10 Hz/1 Hz interrupt function • Capture − Time base capture × 2 channels (4096 Hz to 32 Hz) • PWM − Resolution 16 bits × 1 channel • Synchronous serial port − Master/slave selectable − LSB first/MSB first selectable − 8-bit length/16-bit length selectable • UART − TXD/RXD × 1 channel − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • I2C bus interface − Master function only − Standard mode (50kbps) • Buzzer driver − 4 output modes, 8 frequencies, 16 duty levels • RC oscillation type A/D converter − 24-bit counter − Time division × 2 channels • Successive approximation type A/D converter − 12-bit A/D converter − Input × 2 channels − Conversion time: 46us/1ch@500kHz • General-purpose ports − Non-maskable interrupt input port × 1 channel − Input-only port × 6 channels (including secondary functions) − Output-only port × 3 channels (including secondary functions) − Input/output port ML610Q411: 22 channels (including secondary functions) ML610Q412: 14 channels (including secondary functions) • LCD driver − The number of segments ML610Q411: 144 dots max. (36 seg × 4 com) ML610Q412: 176 dots max. (44 seg × 4 com) − 1/1 to 1/4 duty − 1/3 bias (built-in bias generation circuit) 2/36 FEDL610Q411-04 ML610Q411/ML610Q412 − − − − Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz) Bias voltage multiplying clock selectable (8 types) Contrast adjustment (32 steps) LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable • Reset − Reset through the RESET_N pin − Power-on reset generation when powered on − Reset when oscillation stop of the low-speed clock is detected − Reset by the watchdog timer (WDT) overflow • Battery Level Detector − Threshold voltages: − Accuracy: One of 16 levels ±2% (Typ.) • Clock − Low-speed clock: (This LSI can not guarantee the operation withoug low-speed crystal oscillation clock) Crystal oscillation (32.768 kHz) − High-speed clock: Built-in RC oscillation (500 kHz) External clock (500kH or less) − High-speed Clock gear: 1/2(250kHz), 1/4(125kHz), 1/8(62.5kHz: default) − Selection of high-speed clock mode by software: Built-in RC oscillation, External clock • Power management − HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). − STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) − High-speed Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8 of the oscillation clock) − Block Control Function: Resets and completely turns circuits of unused peripherals off. • Guaranteed operating range − Operating temperature: −20°C to +70°C (P version: −40°C to +85°C) − Operating voltage: VDD = 1.1V to 3.6V, AVDD = 2.2V to 3.6V 3/36 FEDL610Q411-04 ML610Q411/ML610Q412 • Product name – Supported Function The line-up of the ML610Q411 and the ML610Q412 is below. ROM type Low-speed oscillation stop detect reset Operating temperature Product availability ML610Q411-xxxWA Flash ROM Yes -20°C to +70°C Yes ML610Q411P-xxxWA Flash ROM -40°C to +85°C Yes ML610Q411PA-xxxWA Flash ROM -40°C to +85°C Yes ML610Q412-xxxWA Flash ROM Yes Selectable to disable always Yes -20°C to +70°C Yes ML610Q412P-xxxWA Flash ROM Yes -40°C to +85°C Yes - Chip (Die) - -120-pin plastic TQFP - ROM type Low-speed oscillation stop detect reset Operating temperature Product availability ML610Q411-xxxTB Flash ROM Yes -20°C to +70°C Yes ML610Q411P-xxxTB Flash ROM Yes -40°C to +85°C Yes ML610Q411PA-xxxTB Flash ROM Selectable to disable always -40°C to +85°C Yes ML610Q412-xxxTB Flash ROM Yes -20°C to +70°C Yes ML610Q412P-xxxTB Flash ROM Yes -40°C to +85°C Yes xxx：ROM code number (xxx of the blank product is NNN) Q：Flash ROM version P：Wide range temperature version A: Low-speed clock oscillation stop detection reset is selectable to disable always (See chapter3 and chapter4 in the user’s manual for more detail). WA：Chip (Die) TB：TQFP 4/36 FEDL610Q411-04 ML610Q411/ML610Q412 BLOCK DIAGRAM ML610Q411 Block Diagram Figure 1 show the block diagram of the ML610Q411. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST Instruction Decoder IN0* CS0* RCT0* RS0* RT0* RCM* IN1* CS1* RS1* RT1* AIN0, AIN1 EA PC Instruction Register Program Memory (Flash) 16Kbyte BUS Controller INT 1 RAM 1024byte RESET & TEST Interrupt Controller INT 1 OSC WDT SCK0* SIN0* SOUT0* UART RXD0* TXD0* INT 1 INT 1 2 Power INT 1 INT 1 TBC RC-ADC ×2 INT 4 INT 5 BZ0* NMI P00 to P03 P10 to P11 8bit Timer ×4 GPIO P20 to P22 P30 to P35 P40 to P47 PA0 to PA7 INT 1 12bit-ADC BLD PWM0* INT 1 Buzzer Capture ×2 SDA* SCL* INT 1 PWM 1kHzTC VPP SSIO IC INT 4 AVDD AVSS VREF DSR/CSR Data-bus LSCLK* OUTCLK* VDDL VDDX LR SP XT0 XT1 OSC0* ECSR1～3 ALU VDD VSS RESET_N ELR1～3 Display register 144bit LCD Driver COM0 to COM3 LCD BIAS VL1, VL2, VL3 SEG0 to SEG35 C1, C2 Figure 1 ML610Q411 Block Diagram 5/36 FEDL610Q411-04 ML610Q411/ML610Q412 ML610Q412 Block Diagram Figure 2 show the block diagram of the ML610Q412. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST Instruction Decoder IN0* CS0* RCT0* RS0* RT0* RCM* IN1* CS1* RS1* RT1* VREF EA PC Instruction Register Program Memory (Flash) 16Kbyte BUS Controller INT 1 RAM 1024byte RESET & TEST Interrupt Controller INT 1 OSC WDT SCK0* SIN0* SOUT0* UART RXD0* TXD0* INT 1 INT 1 2 Power INT 1 INT 1 TBC RC-ADC ×2 INT 4 PWM0* INT 1 Melody Capture ×2 SDA* SCL* INT 1 PWM 1kHzTC VPP SSIO IC INT 4 INT 5 MD0* NMI P00 to P03 P10 to P11 8bit Timer ×4 GPIO P20 to P22 P30 to P35 AVDD AVSS AIN0, AIN1 DSR/CSR Data-bus LSCLK* OUTCLK* VDDL VDDX LR SP XT0 XT1 OSC0* ECSR1～3 ALU VDD VSS RESET_N ELR1～3 INT 1 P40 to P47 12bit-ADC BLD Display register 176bit LCD Driver COM0 to COM3 LCD BIAS VL1, VL2, VL3 SEG0 to SEG43 C1, C2 Figure 2 ML610Q412 Block Diagram 6/36 FEDL610Q411-04 ML610Q411/ML610Q412 PIN CONFIGURATION 90pin 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 120pin 1pin VPP VSS P20 P21 P22 P40 P41 RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT1 XT0 AVSS VREF AVDD SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 (NC) (NC) (NC) (NC) (NC) (NC) (NC) 61pin 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91pin SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 VL1 VL2 VL3 C1 C2 ML610Q411 TQFP120 Pin Layout (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) VSS VDD VSS P03 P02 P01 P00 NMI P11 P10 (NC) AIN1 AIN0 (NC) (NC) (NC) (NC) 31pin 30pin (NC): No Connection Note: The assignment of the P30 to P35 are not in order. Figure 3 ML610Q411 TQFP120 Pin Configuration 7/36 FEDL610Q411-04 ML610Q411/ML610Q412 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 120pin 1pin VPP VSS P20 P21 P22 P40 P41 RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT1 XT0 AVSS VREF AVDD SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 (NC) (NC) (NC) (NC) (NC) (NC) (NC) 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 91pin 61pin 71 70 69 68 67 66 65 64 63 62 61 90pin SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 VL1 VL2 VL3 C1 C2 ML610Q412 TQFP120 Pin Layout (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) VSS VDD VSS P03 P02 P01 P00 NMI P11 P10 (NC) AIN1 AIN0 (NC) (NC) (NC) (NC) 31pin 30pin (NC): No Connection Note: The assignment of the P30 to P35 are not in order. Figure 4 ML610Q412 TQFP120 Pin Configuration 8/36 FEDL610Q411-04 ML610Q411/ML610Q412 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 VL1 VL2 VL3 C1 C2 ML610Q411 Chip Pin Layout & Dimension 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 * 47 46 45 44 43 42 41 40 39 38 37 36 35 VSS VDD VSS P03 P02 P01 P00 NMI P11 P10 (NC) AIN1 AIN0 2.636mm XT0 AVSS VREF AVDD VPP VSS P20 P21 P22 P40 P41 RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 * 27 28 29 30 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 2.836mm * Dummy pad Note: These dummy pads are visible and do have any function, they are placed for a mechanical evaluation in LAPIS Semiconductor. Please do NOT implement wire-bonding to the dummy pad. Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 2.836mm x 2.636mm 95 pins 80 µm 70 µm × 70 µm 350 µm VSS level Figure 5 ML610Q411 Chip Layout & Dimension 9/36 FEDL610Q411-04 ML610Q411/ML610Q412 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 VL1 VL2 VL3 C1 C2 ML610Q412 Chip Pin Layout & Dimension 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 * 47 46 45 44 43 42 41 40 39 38 37 36 35 VSS VDD VSS P03 P02 P01 P00 NMI P11 P10 (NC) AIN1 AIN0 2.636mm XT0 AVSS VREF AVDD VPP VSS P20 P21 P22 P40 P41 RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 * 27 28 29 30 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 2.836mm * Dummy pad Note: These dummy pads are visible and do have any function, they are placed for a mechanical evaluation in LAPIS Semiconductor. Please do NOT implement wire-bonding to the dummy pad. Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 2.836mm x 2.636mm 95 pins 80 µm 70 µm × 70 µm 350 µm VSS level Figure 6 ML610Q412 Chip Layout & Dimension 10/36 FEDL610Q411-04 ML610Q411/ML610Q412 ML610Q411 Pad Coordinates Table 1 ML610Q411 Pad Coordinates Chip Center: X=0,Y=0 PAD No. Pad Name X (µm) Y (µm) PAD No. Pad Name X (µm) Y (µm) PAD No. Pad Name X (µm) Y (µm) 1 VPP VSS P20 P21 P22 P40 P41 RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT1 Dummy XT0 AVSS VREF AVDD (NC) (NC) (NC) (NC) AIN0 AIN1 (NC) P10 P11 NMI P00 P01 P02 P03 VSS VDD VSS (NC) (NC) (NC) -1230 -1212 51 - 101 160 52 - - 102 -1312 80 -1070 -1212 53 - - 103 -990 -1212 54 - - 104 -910 -1212 55 - - 105 -830 -1212 56 - - 106 -750 -1212 57 - - 107 -670 -1212 58 - - 108 -590 -1212 59 - - 109 -510 -1212 60 - - 110 -430 -1212 61 1220 1212 111 -350 -1212 62 1140 1212 112 -270 -1212 63 1060 1212 113 -190 -1212 64 980 1212 -- SEG31 SEG32 SEG33 SEG34 SEG35 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Dummy -1312 -1212 -110 -1212 65 -30 -1212 66 (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) C2 C1 VL3 VL2 VL1 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 - -1150 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 50 -1212 67 130 -1212 68 210 -1212 69 290 -1212 70 370 -1212 71 450 -1212 72 530 -1212 73 610 -1212 74 690 -1212 75 770 -1212 76 850 -1212 77 930 -1212 78 1030 -1212 79 1110 -1212 80 1190 -1212 81 - - 82 - - 83 - - 84 - - 85 1312 -522 86 1312 -350 87 - - 88 1312 -210 89 1312 -130 90 1312 -50 91 1312 30 92 1312 110 93 1312 190 94 1312 270 95 1312 350 96 1312 430 97 1312 510 98 - - 99 - - 100 - - 900 1212 820 1212 740 1212 660 1212 580 1212 500 1212 420 1212 340 1212 260 1212 180 1212 100 1212 20 1212 -60 1212 -140 1212 -220 1212 -300 1212 -380 1212 -460 1212 -540 1212 -620 1212 -700 1212 -780 1212 -860 1212 -940 1212 -1020 1212 -1100 1212 -1312 960 -1312 880 -1312 800 -1312 720 -1312 640 -1312 560 -1312 480 -1312 400 -1312 320 -1312 240 -1312 0 -1312 -80 -1312 -160 -1312 -240 -1312 -320 -1312 -400 -1312 -480 -1312 -560 -1312 -640 -1312 -720 -1312 -800 -1312 -908 11/36 FEDL610Q411-04 ML610Q411/ML610Q412 ML610Q412 Pad Coordinates Table 2 ML610Q412 Pad Coordinates Chip Center: X=0,Y=0 PAD No. Pad Name X (µm) Y (µm) PAD No. Pad Name X (µm) Y (µm) PAD No. Pad Name X (µm) Y (µm) 1 VPP VSS P20 P21 P22 P40 P41 RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT1 Dummy XT0 AVSS VREF AVDD (NC) (NC) (NC) (NC) AIN0 AIN1 (NC) P10 P11 NMI P00 P01 P02 P03 VSS VDD VSS (NC) (NC) (NC) -1230 -1212 51 - 101 160 52 - - 102 -1312 80 -1070 -1212 53 - - 103 -990 -1212 54 - - 104 -910 -1212 55 - - 105 -830 -1212 56 - - 106 -750 -1212 57 - - 107 -670 -1212 58 - - 108 -590 -1212 59 - - 109 -510 -1212 60 - - 110 -430 -1212 61 1220 1212 111 -350 -1212 62 1140 1212 112 -270 -1212 63 1060 1212 113 -190 -1212 64 980 1212 - SEG31 SEG32 SEG33 SEG34 SEG35 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 Dummy -1312 -1212 -110 -1212 65 (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) C2 C1 VL3 VL2 VL1 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 - -1150 900 1212 820 1212 740 1212 660 1212 580 1212 500 1212 420 1212 340 1212 260 1212 180 1212 100 1212 20 1212 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 -30 -1212 66 50 -1212 67 130 -1212 68 210 -1212 69 290 -1212 70 370 -1212 71 450 -1212 72 530 -1212 73 610 -1212 74 690 -1212 75 770 -1212 76 850 -1212 77 930 -1212 78 1030 -1212 79 1110 -1212 80 1190 -1212 81 - - 82 - - 83 - - 84 - - 85 1312 -522 86 1312 -350 87 - - 88 1312 -210 89 1312 -130 90 1312 -50 91 1312 30 92 1312 110 93 1312 190 94 1312 270 95 1312 350 96 1312 430 97 1312 510 98 - - 99 - - 100 - - -60 1212 -140 1212 -220 1212 -300 1212 -380 1212 -460 1212 -540 1212 -620 1212 -700 1212 -780 1212 -860 1212 -940 1212 -1020 1212 -1100 1212 -1312 960 -1312 880 -1312 800 -1312 720 -1312 640 -1312 560 -1312 480 -1312 400 -1312 320 -1312 240 -1312 0 -1312 -80 -1312 -160 -1312 -240 -1312 -320 -1312 -400 -1312 -480 -1312 -560 -1312 -640 -1312 -720 -1312 -800 -1312 -908 12/36 FEDL610Q411-04 ML610Q411/ML610Q412 PIN LIST PAD No. Primary function Secondary function Tertiary function Pin name I/O Function Pin name I/O Function Pin name I/O Function VSS ⎯ Negative power supply pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 22, 46 VDD ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 23 VDDL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 25 VDDX ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 VPP ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 28 AVSS ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 30 AVDD ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 65 VL1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 64 VL2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 63 VL3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 62 C1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 61 C2 ⎯ Positive power supply pin Power supply pin for internal logic (internally generated) Power supply pin for low-speed oscillation (internally generated) Power supply pin for Flash ROM Negative power supply pin for successive approximation type ADC Positive power supply pin for successive approximation type ADC Power supply pin for LCD bias (internally generated) Power supply pin for LCD bias (internally generated) Power supply pin for LCD bias (internally generated) Capacitor connection pin for LCD bias generation Capacitor connection pin for LCD bias generation ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 21 TEST I/O Input/output pin for testing ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Reset input pin Low-speed clock oscillation pin Low-speed clock oscillation pin Reference power supply pin for successive approximation type ADC ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2, 24,45,47 8 RESET_N I 27 XT0 I 26 XT1 O 29 VREF ⎯ 13/36 FEDL610Q411-04 ML610Q411/ML610Q412 PAD No. Pin name I/O 35 AIN0 I 36 AIN1 I NMI I 40 41 42 43 44 38 Primary function P00/EXI0/ CAP0 P01/EXI1/ CAP1 P02/EXI2/ RXD0 P03/EXI3 P10 OSC0 Secondary function Tertiary function Function Pin name Successive approximation ⎯ type ADC input Successive approximation ⎯ type ADC input Non-maskable interrupt pin ⎯ I/O Function Pin name I/O Function ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I Input port, External interrupt 0, Capture 0 input ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I Input port, External interrupt 1, Capture 1 input ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I Input port, External interrupt 2, UART0 receive ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I Input port, External interrupt 3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I Input port External clock input ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Low-speed clock output High-speed clock output Melody output RC type ADC0 oscillation input pin RC type ADC0 reference capacitor connection pin RC type ADC0 resistor/capacitor sensor connection pin RC type ADC0 reference resistor connection pin RC type ADC0 resistor sensor connection pin RC type ADC oscillation monitor 2 I C data input/output ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PWM0 O PWM output ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SIN0 I SCK0 I/O 39 P11 I Input port 3 P20/LED0 O Output port LSCLK O 4 P21LED1 O Output port OUTCLK O 5 P22/LED2 O Output port MD0 O 15 P30 I/O Input/output port IN0 I 16 P31 I/O Input/output port CS0 O 17 P34 I/O Input/output port RCT0 O 18 P32 I/O Input/output port RS0 O 19 P33 I/O Input/output port RT0 O 20 P35 I/O Input/output port RCM O 6 P40 I/O Input/output port SDA I/O 7 P41 I/O Input/output port SCL I/O 9 P42 I/O Input/output port RXD0 I UART data input SOUT0 I SSIO data input SSIO synchronous clock SSIO data output 10 P43 I/O Input/output port Input/output port, Timer 0/Timer 2/PWM0 external clock input Input/output port, Timer 1/Timer 3 external clock input TXD0 O UART data output PWM0 O PWM output IN1 I RC type ADC1 oscillation input pin SIN0 I SSIO0 data input CS1 O SCK0 I/O SSIO0 synchronous clock SOUT0 O SSIO0 data output ⎯ ⎯ ⎯ 11 12 P44/T02P0 CK P45/T13P1 CK I/O I/O 13 P46 I/O Input/output port RS1 O 14 P47 I/O Input/output port RT1 O 1 106 PA0(* ) 2 SEG43(* ) 1 107 PA1(* ) 2 SEG42(* ) 1 108 PA2(* ) 2 SEG41(* ) 1 109 PA3(* ) 2 SEG40(* ) 2 I C clock input/output RC type ADC1 reference capacitor connection pin RC type ADC1 reference resistor connection pin RC type ADC1 resistor sensor connection pin I/O Input/output port ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I/O Input/output port ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I/O Input/output port ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I/O Input/output port ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 14/36 FEDL610Q411-04 ML610Q411/ML610Q412 PAD No. Primary function Pin name 1 110 PA4(* ) 2 SEG39(* ) 1 111 PA5(* ) 2 SEG38(* ) 1 112 PA6(* ) 2 SEG37(* ) I/O Function Secondary function Tertiary function Pin name I/O Function Pin name I/O Function I/O Input/output port ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I/O Input/output port ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I/O Input/output port ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I/O Input/output port ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SEG36(* ) O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 69 COM0 O LCD common pin ⎯ ⎯ ⎯ ⎯ ⎯ 68 COM1 O LCD common pin ⎯ ⎯ ⎯ ⎯ ⎯ 67 COM2 O LCD common pin ⎯ ⎯ ⎯ ⎯ ⎯ 66 COM3 O LCD common pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 70 SEG0 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 71 SEG1 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 72 SEG2 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 73 SEG3 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 74 SEG4 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 75 SEG5 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 76 SEG6 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 77 SEG7 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 78 SEG8 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 79 SEG9 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 80 SEG10 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 81 SEG11 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 82 SEG12 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 83 SEG13 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 84 SEG14 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 85 SEG15 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 86 SEG16 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 87 SEG17 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 88 SEG18 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 89 SEG19 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 90 SEG20 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 91 SEG21 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 92 SEG22 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 93 SEG23 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 94 SEG24 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 95 SEG25 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 96 SEG26 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 97 SEG27 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 98 SEG28 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 99 SEG29 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 100 SEG30 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 101 SEG31 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 102 SEG32 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 103 SEG33 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 104 SEG34 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 105 SEG35 O LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 113 PA7(* ) 2 (*1) Pins on ML610Q411. (*2) Pins on ML610Q412. 15/36 FEDL610Q411-04 ML610Q411/ML610Q412 PIN DESCRIPTION Pin name I/O Description Primary/ Secondary/ Tertiary Logic — Negative — — — — Secondary — Secondary — Secondary — Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive System Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected. XT0 I Crystal connection pin for low-speed clock. XT1 O A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL are connected across this pin and VSS as required. OSC0 I High-speed external clock input pin. This pin is used as the secondary function of the P10. LSCLK O Low-speed clock output pin. This pin is used as the secondary function of the P20 pin. OUTCLK O High-speed clock output pin. This pin is used as the secondary function of the P21 pin. General-purpose input port RESET_N I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P10-P11 I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose output port P20-P22 O General-purpose output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose input/output port P30-P35 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P40-P47 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. PA0-PA7 I/O General-purpose input/output port. These pins are for the ML610Q411, but are not provided in the ML610Q412. P00-P03 I 16/36 FEDL610Q411-04 ML610Q411/ML610Q412 Pin name I/O UART TXD0 O RXD0 I Primary/ Secondary/ Tertiary Logic Secondary Positive Primary/Se condary Positive Secondary Positive Secondary Positive Tertiary — Tertiary Positive Tertiary Positive Tertiary Positive Primary — External non-maskable interrupt input pin. An interrupt is generated on both edges. External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00-P03 pins. Primary Positive/ negative Positive/ negative Capture trigger input pins. The value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. These pins are used as the primary functions of the P00 pin(CAP0) and P01 pin(CAP1). Primary Description UART data output pin. This pin is used as the secondary function of the P43 pin. UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. I2C bus interface 2 SDA I/O I C data input/output pin. This pin is used as the secondary function of the P40 pin. This pin has an NMOS open drain output. When using this pin as 2 a function of the I C, externally connect a pull-up resistor. 2 SCL O I C clock output pin. This pin is used as the secondary function of the P41 pin. This pin has an NMOS open drain output. When using this pin as a 2 function of the I C, externally connect a pull-up resistor. Synchronous serial (SSIO) SCK0 SIN0 SOUT0 PWM PWM0 T02P0CK I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P41 or P45 pin. I Synchronous serial data input pin. This pin is used as the tertiary function of the P40 or P44 pin. O Synchronous serial data output pin. This pin is used as the tertiary function of the P42 or P46 pin. O O External interrupt NMI I EXI0-3 I Capture CAP0 I CAP1 I Timer T02P0CK T13P1CK I I PWM0 output pin. This pin is used as the tertiary function of the P43 or P34 pin. PWM0 external clock input pin. This pin is used as the primary function of the P44 pin. External clock input pin used for both Timer 0 and Timer 2. The clocks for these timers are selected by software. This pin is used as the primary function of the P44 pin. External clock input pin used for both Timer 1 and Timer 3. The clocks for these timers are selected by software. This pin is used as the primary function of the P45 pin. Buzzer BZ0 O Buzzer signal output pin. This pin is used as the secondary function of the P22 pin. LED drive LED0-2 O Nch open drain output pins to drive LED. Primary Primary Positive/ negative Positive/ negative Primary — Primary — Secondary Positive/ negative Primary Positive/ negative 17/36 FEDL610Q411-04 ML610Q411/ML610Q412 Pin name I/O Description RC oscillation type A/D converter IN0 I Channel 0 oscillation input pin. This pin is used as the secondary function of the P30 pin. CS0 O Channel 0 reference capacitor connection pin. This pin is used as the secondary function of the P31 pin. RCT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P33 pin. RS0 O This pin is used as the secondary function of the P32 pin which is the reference resistor connection pin of Channel 0. RT0 O Resistor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P34 pin. RC oscillation monitor pin. This pin is used as the secondary function of RCM O the P35 pin. IN1 I Oscillation input pin of Channel 1. This pin is used as the secondary function of the P44 pin. CS1 O Reference capacitor connection pin of Channel 1. This pin is used as the secondary function of the P45 pin. RS1 O Reference resistor connection pin of Channel 1. This pin is used as the secondary function of the P46 pin. RT1 O Resistor sensor connection pin for measurement of Channel 1. This pin is used as the secondary function of the P47 pin. Successive approximation type A/D converter AVSS — Negative power supply pin for successive approximation type A/D converter. AVDD — Positive power supply pin for successive approximation type A/D converter. VREF — Reference power supply pin for successive approximation type A/D converter. AIN0 I Channel 0 analog input for successive approximation type A/D converter. AIN1 I Channel 1 analog input for successive approximation type A/D converter. LCD drive signal COM0-3 O SEG0-35 O Common output pins. Segment output pins. Segment output pin. These pins are for the ML610Q412, but are not provided in the ML610Q411. LCD driver power supply VL1 — Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb, VL2 — and Cc (see measuring circuit 1) are connected between VSS and VL1, VL2, VL3 — and VL3, respectively. C1 — Power supply pins for LCD bias (internally generated). Capacitors C12 is connected between C1 and C2. C2 — SEG36-43 O For testing TEST I/O Input/output pin for testing. A pull-down resistor is internally connected. Power supply VSS — Negative power supply pin. VDD — Positive power supply pin for I/O, internal regulator, battery low detector, and power-on reset. VDDL — Positive power supply pin (internally generated) for internal logic. Capacitors CL0 and CL1 (see measuring circuit 1) are connected between this pin and VSS. VDDX — Positive power supply pin (internally generated) for low-speed oscillation. When using ML610Q411 and ML610Q412, connect capacitor Cx (see measuring circuit 1) between this pin and VSS. VPP — Power supply pin for programming Flash ROM. A pull-down resistor is internally connected. Primary/ Secondary/ Tertiary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Logic — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 18/36 FEDL610Q411-04 ML610Q411/ML610Q412 TERMINATION OF UNUSED PINS Table 3 shows methods of terminating the unused pins. Table 3 Termination of Unused Pins Pin VPP AVDD AVSS VREF AIN0, AIN1 VL1, VL2, VL3 C1, C2 RESET_N TEST NMI P00 to P03 P10 to P11 P20 to P22 P30 to P35 P40 to P47 PA0 to PA7 COM0 to 3 SEG0 to 43 Recommended pin termination Open VSS VSS VSS Open Open Open Open Open Open VDD or VSS VDD Open Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 19/36 FEDL610Q411-04 ML610Q411/ML610Q412 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (VSS = AVSS = 0V) Symbol Condition Rating Unit Power supply voltage 1 Parameter VDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 2 AVDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 3 VPP Ta = 25°C −0.3 to +9.5 V Power supply voltage 4 VDDL Ta = 25°C −0.3 to +3.6 V Power supply voltage 5 VDDX Ta = 25°C −0.3 to +3.6 V Power supply voltage 6 VL1 Ta = 25°C −0.3 to +1.75 V Power supply voltage 7 VL2 Ta = 25°C −0.3 to +3.5 V Power supply voltage 8 VL3 Ta = 25°C −0.3 to +5.25 V Input voltage VIN Ta = 25°C −0.3 to VDD+0.3 V Output voltage VOUT Ta = 25°C −0.3 to VDD+0.3 V Output current 1 IOUT1 Port3–A, Ta = 25°C −12 to +11 mA Output current 2 IOUT2 Port2, Ta = 25°C −12 to +20 mA Power dissipation PD Ta = 25°C 1.25 W Storage temperature TSTG ⎯ −55 to +150 °C RECOMMENDED OPERATING CONDITIONS (VSS = AVSS = 0V) Parameter Operating temperature Operating voltage Operating frequency (CPU) Symbol Condition Range ML610Q411, ML610Q412, ML610Q411P, ML610Q411PA, ML610Q412P −20 to +70 TOP VDD ⎯ 1.1 to 3.6 AVDD ⎯ 2.2 to 3.6 VDD = 1.1 to 3.6V 30k to 36k 46.9k to 78.1k fOP −40 to +85 Unit °C V Hz Capacitor externally connected to VDDL pin CL0 CL1 ⎯ ⎯ 30k to 625k 23k to 625k 1.0±30% 0.1±30% Capacitor externally connected to VDDX pin CX ⎯ 0.1±30% µF Capacitors externally connected to VL1, 2, 3 pins C1, 2, 3 ⎯ 1.0±30% µF C12 ⎯ 1.0±30% µF VDD = 1.3 to 3.6V Capacitors externally connected across C1 and C2 pins µF 20/36 FEDL610Q411-04 ML610Q411/ML610Q412 CLOCK GENERATION CIRCUIT OPERATING CONDITIONS (VSS = 0V) Parameter Low-speed crystal oscillation frequency Recommended equivalent series resistance value of low-speed crystal oscillation Symbol Rating Condition Unit Min. Typ. Max. fXTL ⎯ ⎯ 32.768k ⎯ Hz RL ⎯ ⎯ ⎯ 40k Ω CL=6pF of crystal ⎯ 0 ⎯ oscillation *2 CL=9pF of CDL/CGL crystal ⎯ 6 ⎯ Low-speed crystal oscillation pF external capacitor *1 oscillation CL=12pF of crystal ⎯ 12 ⎯ oscillation ⎯ ⎯ 24 ⎯ CGH *1 : The external CDL and CGL need to be adjusted in consideration of variation of internal loading capacitance CD and CG, and other additional capacitance such as PCB layout. *2 : When using a crystal oscillator CL = 6pF, there is a possibility that can not be adjusted by external CDL and CGL. OPERATING CONDITIONS OF FLASH ROM Parameter Operating temperature Operating voltage Write cycles Data retention Symbol TOP VDD VDDL VPP CEP YDR Condition At write/erase At write/erase*1 At write/erase*1 At write/erase*1 ⎯ ⎯ Range 0 to +40 2.75 to 3.6 2.5 to 2.75 7.7 to 8.3 80 10 (VSS = AVSS = 0V) Unit °C V cycles years *1 : Those voltages must be supplied to VDDL pin and VPP pin when programming and eraseing Flash ROM. VPP pin has an internal pulldown resister. 21/36 FEDL610Q411-04 ML610Q411/ML610Q412 DC CHARACTERISTICS (1/5) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (1/5) Measuring Rating Parameter Symbol Condition Unit circuit Min. Typ. Max. 500kHz RC oscillation frequency VDD = 1.3 to 3.6V fRC Ta = 25°C *3 Typ. −10% Typ. −25% 500 500 Typ. +10% Typ. +25% kHz kHz Low-speed crystal oscillation TXTL ⎯ ⎯ 0.3 2 s start time*2 500kHz RC oscillation start TRC ⎯ ⎯ 50 500 µs 1 time Low-speed oscillation stop TSTOP ⎯ 0.2 3 20 ms *1 detect time Reset pulse width PRST ⎯ 200 ⎯ ⎯ µs Reset noise elimination ⎯ ⎯ ⎯ 0.3 PNRST pulse width Power-on reset activation ⎯ ⎯ ⎯ 10 ms TPOR power rise time 1 * : When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. 2 * : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF. 3 * : Recommended operating temperature (Ta = −40 to +85°C for P version, Ta = −20 to +70°C for non-P version) [Reset pulse width] VIL1 RESET_N VIL1 PRST Reset pulse width (PRST) [Power-on reset activation power rise time] 0.9xVDD VDD 0.1xVDD TPOR Power-on reset activation power rise time (TPOR ) 22/36 FEDL610Q411-04 ML610Q411/ML610Q412 DC CHARACTERISTICS (2/5) Parameter VL1 voltage VL1 temperature deviation *1 VL1 voltage dependency *1 (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (2/5) Measuring Rating Symbol Condition Unit circuit Min. Typ. Max. VL1 VDD = 3.0V, Tj = 25°C CN4–0 = 00H CN4–0 = 01H CN4–0 = 02H CN4–0 = 03H CN4–0 = 04H CN4–0 = 05H CN4–0 = 06H CN4–0 = 07H CN4–0 = 08H CN4–0 = 09H CN4–0 = 0AH CN4–0 = 0BH CN4–0 = 0CH CN4–0 = 0DH CN4–0 = 0EH CN4–0 = 0FH CN4–0 = 10H CN4–0 = 11H CN4–0 = 12H CN4–0 = 13H CN4–0 = 14H CN4–0 = 15H CN4–0 = 16H CN4–0 = 17H CN4–0 = 18H CN4–0 = 19H CN4–0 = 1AH CN4–0 = 1BH CN4–0 = 1CH CN4–0 = 1DH CN4–0 = 1EH CN4–0 = 1FH 0.89 0.91 0.93 0.95 0.97 0.99 1.01 1.03 1.05 1.07 1.09 1.11 1.13 1.15 1.17 1.19 1.21 1.23 1.25 1.27 1.29 1.31 1.33 1.35 1.37 1.39 1.41 1.43 1.45 1.47 1.49 1.51 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 1.42 1.44 1.46 1.48 1.50 1.52 1.54 1.56 0.99 1.01 1.03 1.05 1.07 1.09 1.11 1.13 1.15 1.17 1.19 1.21 1.23 1.25 1.27 1.29 1.31 1.33 1.35 1.37 1.39 1.41 1.43 1.45 1.47 1.49 1.51 1.53 1.55 1.57 1.59 1.61 V 1 ∆VL1 VDD = 3.0V ⎯ −1.5 ⎯ mV/°C ∆VL1 VDD = 1.3 to 3.6V ⎯ 5 20 mV/V VDD = 3.0V, Tj = 25°C 1MΩ load (VL3−VSS) Typ. −10% Typ. −10% VL1×2 Typ. +4% Typ. +4% V VL2 voltage VL2 VL3 voltage VL3 VL1×3 LCD bias voltage TBIAS ⎯ ⎯ ⎯ 600 ms generation time 1 * :VL1 can not exceed VDD level. The maximum VL1 becomes VDD level when the VL1 calculated by the temperature deviation and voltage dependency is going to exceed the VDD level. 23/36 FEDL610Q411-04 ML610Q411/ML610Q412 DC CHARACTERISTICS (3/5) Parameter BLD threshold voltage (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (3/5) Measuring Rating Symbol Condition Unit circuit Min. Typ. Max. VBLD BLD threshold voltage temperature deviation ∆VBLD Supply current 1 IDD1 Supply current 2 Supply current 3 Supply current 4 Supply current 5 Supply current 6 IDD2 IDD3 IDD4 IDD5 IDD6 VDD = 1.35 to 3.6V LD3–0 = 0H LD3–0 = 1H LD3–0 = 2H LD3–0 = 3H LD3–0 = 4H LD3–0 = 5H LD3–0 = 6H LD3–0 = 7H LD3–0 = 8H LD3–0 = 9H LD3–0 = 0AH LD3–0 = 0BH LD3–0 = 0CH LD3–0 = 0DH LD3–0 = 0EH LD3–0 = 0FH 1.35 1.4 1.45 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.7 2.9 Typ. +2% ⎯ 0 ⎯ ⎯ 0.15 0.5 * ⎯ ⎯ 2.5 Ta= 25°C ⎯ 0.5 1.3 VDD = 1.35 to 3.6V CPU: In STOP state. Low-speed/high-speed RC500kHz oscillation: stopped. CPU: In HALT state (LTBC and WDT are Operating. Low speed oscillation 3 4 stop detector is Stopped).* * High-speed 500kHz oscillation: Stopped. LCD and BIAS circuits: Stopped. CPU: In HALT state (LTBC and WDT are Operating. Low speed oscillation stop detector is Stopped).*3 High-speed 500kHz oscillation: Stopped. 2 LCD and BIAS circuits: Operating. * CPU: In 32.768kHz operating state.*1*3 High-speed 500kHz oscillation: Stopped. LCD and BIAS circuits: Operating. *2 CPU: In RC 500kHz operating state. LCD and BIAS circuits: Operating. *2 CPU: In RC 500kHz operating 2 state.* LCD and BIAS circuits: Operating. *2 A/D: In operating state. VDD = AVDD = 3.0V Ta= 25°C 5 Typ. −2% V 1 %/°C µA µA 5 * ⎯ ⎯ 3.5 Ta= 25°C ⎯ 1.28 1.6 1 µA *5 ⎯ ⎯ 11 Ta= 25°C ⎯ 5.5 7 µA 5 * ⎯ ⎯ 12 Ta= 25°C ⎯ 80 90 * ⎯ ⎯ 100 Ta= 25°C ⎯ 0.4 0.5 5 µA 1 mA 5 * ⎯ ⎯ 0.6 *1: When the CPU operating rate is 100% (No HALT state). *2: All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock: 1/128 LSCLK (256Hz) 3 * : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF. 4 * : Significant bits of BLKCON0~BLKCON4 registers are all “1”. 5 * : Recommended operating temperature (Ta = −40 to +85°C for P version, Ta = −20 to +70°C for non-P version) 24/36 FEDL610Q411-04 ML610Q411/ML610Q412 DC CHARACTERISTICS (4/5) Parameter (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (4/5) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IOL1 = +0.5mA, VDD = 1.8 to 3.6V IOL1 = +0.1mA, VDD = 1.3 to 3.6V VDD −0.5 VDD −0.3 VDD −0.3 ⎯ ⎯ ⎯ ⎯ 0.5 0.5 IOL1 = +0.03mA, VDD = 1.1 to 3.6V ⎯ ⎯ 0.3 IOH1 = −0.5mA, VDD = 1.8 to 3.6V VDD −0.5 VDD −0.3 VDD −0.3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.5 ⎯ ⎯ 0.4 IOH1 = −0.5mA, VDD = 1.8 to 3.6V Output voltage 1 nd (P20–P22/2 function is selected) (P30–P36) (P40–P47) *1 (PB0–PB7) Output voltage 2 nd (P20–P22/2 function is Not selected) VOH1 IOH1 = -0.03mA, VDD = 1.1 to 3.6V VOL1 VOH1 Output voltage 4 (COM0–3) *1 (SEG0–35) *2 (SEG0–43) Output leakage (P20–P22) (P30–P35) (P40–P47) *1 (PA0–PA7) Input current 1 (RESET_N) Input current 1 (TEST) VOL3 IOL2 = +5mA, VDD = 1.8 to 3.6V IOL3 = +3mA, VDD = 2.0 to 3.6V (when I2C mode is selected) VOH4 IOH4 = −0.2mA, VL1=1.2V VL3 −0.2 ⎯ ⎯ VOMH4 IOMH4 = +0.2mA, VL1=1.2V ⎯ ⎯ VL2 +0.2 VOM4S IOM4S = −0.2mA, VL1=1.2V VL2 −0.2 ⎯ ⎯ VOML4 IOML4 = +0.2mA, VL1=1.2V ⎯ ⎯ VL1 +0.2 VOML4S IOML4S = −0.2mA, VL1=1.2V VL1 −0.2 ⎯ ⎯ VOL4 IOL4 = +0.2mA, VL1=1.2V ⎯ ⎯ 0.2 IOOH VOH = VDD (in high-impedance state) ⎯ ⎯ 1 IOOL VOL = VSS (in high-impedance state) −1 ⎯ ⎯ IIH1 VIH1 = VDD VDD = 1.3 to 3.6V VIL1 = VSS VDD = 1.1 to 3.6V VDD = 1.3 to 3.6V VIH1 = VDD VDD = 1.1 to 3.6V VIL1 = Vss VIH2 = VDD VDD = 1.3 to 3.6V (when pulled-down) VDD = 1.1 to 3.6V VIL2 = VSS VDD = 1.3 to 3.6V (when pulled-up) VDD = 1.1 to 3.6V 0 −600 −600 10 2 -1 0.2 0.01 −200 −200 ⎯ −300 −300 300 300 ⎯ 30 30 −30 −30 1 -10 -2 600 600 ⎯ 200 200 -0.2 -0.01 IIH2Z VIH2 = VDD (in high-impedance state) ⎯ ⎯ 1 IIL2Z VIL2 = VSS (in high-impedance state) −1 ⎯ ⎯ IIL1 IIH1 IIL1 Input current 2 (NMI) (P00-P03) (P10-P11) (P30-P35) (P40-P47) (PA0-PA7) *1 IOH1 = -0.1mA, VDD = 1.3 to 3.6V IOH1 = -0.03mA, VDD = 1.1 to 3.6V VOL2 Output voltage 3 (P40–P41) IOH1 = -0.1mA, VDD = 1.3 to 3.6V IIH2 IIL2 V 2 µA 3 µA 4 *1: ML610Q411 *2: ML610Q412 25/36 FEDL610Q411-04 ML610Q411/ML610Q412 DC CHARACTERISTICS (5/5)) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (5/5) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. Parameter Input voltage 1 (RESET_N) (TEST) (NMI) (P00–P03) (P10–P11) (P31–P35) (P40–P43) (P45–P47) *1 (PA0–PA7) Hysteresis width (RESET_N) (TEST_N) (NMI) (P00–P03) (P10–P11) (P31–P35) (P40–P43) (P45–P47) *1 (PA0–PA7) Input voltage 2 (P30, P44) Input pin capacitance (NMI) (P00–P03) (P10–P11) (P30–P35) (P40–P47) *1 (PA0–PA7) *1: ML610Q411 VDD = 1.3 to 3.6V 0.7 ×VDD ⎯ VDD VDD = 1.1 to 3.6V 0.7 ×VDD ⎯ VDD VDD = 1.3 to 3.6V 0 ⎯ 0.3 ×VDD VDD = 1.1 to 3.6V 0 ⎯ 0.2 ×VDD VDD = 2.0 to 3.6V 0.05 ×VDD 0.18 ×VDD 0.4 ×VDD VDD = 1.1 to 3.6V 0.02 ×VDD 0.18 ×VDD 0.4 ×VDD VIH2 ⎯ 0.7 ×VDD ⎯ VDD VIL2 ⎯ 0 ⎯ 0.3 ×VDD CIN f = 10kHz Vrms = 50mV Ta = 25°C ⎯ ⎯ 5 VIH1 VIL1 V 5 pF ⎯ ∆VT HYSTERESIS WIDTH ∆VT Input signal VDD VSS Internal signal VDDL VSS 26/36 FEDL610Q411-04 ML610Q411/ML610Q412 MEASURING CIRCUITS MEASURING CIRCUIT 1 XT0 32.768kHz crystal XT1 C2 P10/OSC0 C12 C1 VDD AVDD VREFVDDL VDDX VL1 VL2 VL3 VSS AVSS 1µF CV: CL0: 1µF 0.1µF CL1: 0.1µF CX: Ca,Cb,Cc,Cd: 1µF 1µF C12,C34: 32.768kHz crystal: C-001R (Epson Toyocom) A CL1 CL0 CX Ca Cb Cc CV MEASURING CIRCUIT 2 (*2) VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 V AVDDVREF VSSAVSS (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. 27/36 FEDL610Q411-04 ML610Q411/ML610Q412 MEASURING CIRCUIT 3 (*2) VIL Input pins RS1 Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 A AVDDVREF VSSAVSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. MEASURING CIRCUIT 4 Input pins Output pins (*3) A VDD VDDL VDDX VL1 VL2 VL3 AVDD VREF VSSAVSS *3: Measured at the specified output pins. VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 Waveform monitoring MEASURING CIRCUIT 5 AVDDVREF VSSAVSS *1: Input logic circuit to determine the specified measuring conditions. 28/36 FEDL610Q411-04 ML610Q411/ML610Q412 AC CHARACTERISTICS (External Interrupt) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Interrupt: Enabled (MIE = 1), External interrupt disable period TNUL 76.8 CPU: NOP operation ⎯ 106.8 µs System clock: 32.768kHz P00–P03 (Rising-edge interrupt) tNUL P00–P03 (Falling-edge interrupt) tNUL NMI, P00–P03 (Both-edge interrupt) tNUL AC CHARACTERISTICS (Serial Port) (VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Transmit baud rate ⎯ tTBRT ⎯ BRT*1 ⎯ BRT*1 BRT*1 BRT*1 −3% +3% *1: Baud rate period (including the error of the clock frequency selected) set with the serial port baud rate register (SIOBRTL,H) and the serial port mode register 0 (SIOMOD0). Receive baud rate ⎯ tRBRT s s tTBRT TXD0* tRBRT RXD0* *: Indicates the secondary function of the port. 29/36 FEDL610Q411-04 ML610Q411/ML610Q412 AC CHARACTERISTICS (Synchronous Serial Port) (VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. When high-speed oscillation is SCLK input cycle 10 ⎯ ⎯ µs tSCYC (slave mode) not active SCLK output cycle tSCYC ⎯ ⎯ SCLK*1 ⎯ s (master mode) When high-speed oscillation is SCLK input pulse width 4 ⎯ ⎯ µs tSW (slave mode) not active SCLK*1 SCLK*1 SCLK*1 SCLK output pulse width s ⎯ tSW (master mode) ×0.4 ×0.5 ×0.6 SOUT output delay time tSD ⎯ ⎯ ⎯ 500 ns (slave mode) SOUT output delay time tSD ⎯ ⎯ ⎯ 500 ns (master mode) SIN input setup time ⎯ 80 ⎯ ⎯ ns tSS (slave mode) SIN input setup time ⎯ 500 ⎯ ⎯ ns tSS (master mode) SIN input tSH ⎯ 300 ⎯ ⎯ ns hold time *1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1) tSCYC tSW tSW SCLK0* tSD tSD SOUT0* tSS tSH SIN0* *: Indicates the secondary function of the port. 30/36 FEDL610Q411-04 ML610Q411/ML610Q412 AC CHARACTERISTICS (I2C Bus Interface: Standard Mode) (VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency fSCL ⎯ ⎯ 50 ⎯ kHz SCL hold time tHD:STA ⎯ 4.0 ⎯ ⎯ µs (start/restart condition) SCL ”L” level time tLOW ⎯ 4.7 ⎯ ⎯ µs SCL ”H” level time tHIGH ⎯ 4.0 ⎯ ⎯ µs SCL setup time ⎯ 4.7 ⎯ ⎯ µs tSU:STA (restart condition) SDA hold time tHD:DAT ⎯ 0 ⎯ ⎯ µs SDA setup time tSU:DAT ⎯ 0.25 ⎯ ⎯ µs SDA setup time tSU:STO ⎯ 4.0 ⎯ ⎯ µs (stop condition) Bus-free time tBUF ⎯ 4.7 ⎯ ⎯ µs Start condition Restart condition Stop condition P40/SDA P41/SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF 31/36 FEDL610Q411-04 ML610Q411/ML610Q412 AC CHARACTERISTICS (RC Oscillation A/D Converter) (VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. RS0, RS1, Resistors for oscillation RT0, CS0, CT0, CS1 ≥ 740pF 1 ⎯ ⎯ kΩ RT0-1,RT1 fOSC1 Resistor for oscillation = 1kΩ 209.4 330.6 435.1 kHz Oscillation frequency fOSC2 Resistor for oscillation = 10kΩ 41.29 55.27 64.16 kHz VDD = 1.5V Resistor for oscillation = 100kΩ 4.71 5.97 7.06 kHz fOSC3 Kf1 RT0, RT0-1, RT1 = 1kHz 5.567 5.982 6.225 ⎯ RS to RT oscillation frequency ratio *1 Kf2 RT0, RT0-1, RT1 = 10kHz 0.99 1 1.01 ⎯ VDD = 1.5V Kf3 RT0, RT0-1, RT1 = 100kHz 0.104 0.108 0.118 ⎯ fOSC1 Resistor for oscillation = 1kΩ 407.3 486.7 594.6 kHz Oscillation frequency fOSC2 Resistor for oscillation = 10kΩ 49.76 59.28 72.76 kHz VDD = 3.0V fOSC3 Resistor for oscillation = 100kΩ 5.04 5.993 7.04 kHz Kf1 RT0, RT0-1, RT1 = 1kHz 8.006 8.210 8.416 ⎯ RS to RT oscillation frequency *1 ratio Kf2 RT0, RT0-1, RT1 = 10kHz 0.99 1 1.01 ⎯ VDD = 3.0V Kf3 RT0, RT0-1, RT1 = 100kHz 0.100 0.108 0.115 ⎯ *1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. fOSCX(RT0-1−CS0 oscillation) fOSCX(RS0−CS0 oscillation) , IN0 CS0 RCT0 (*1) VIL *1: Input logic circuit to determine the specified measuring conditions. VDDL VDDX RT1 RT0, RT0-1, RT1: 1kΩ /10kΩ/100kΩ RS0, RS1: 10kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF IN1 CS1 RS1 RT1 RCM VDD CV RT0 RS0 RS0 RT0 Input pins VIH , fOSCX(RT1−CS1 oscillation) fOSCX(RS1−CS1 oscillation) CVR1 RT0-1 CT0 CS0 CVR0 RS1 fOSCX(RT0−CS0 oscillation) fOSCX(RS0−CS0 oscillation) (x = 1, 2, 3) CS1 Kfx = Frequency measurement (fOSCX) AVDD VREFVSS AVSS CL1 CL0 CX Note: - Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. - When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal. - Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have. 32/36 FEDL610Q411-04 ML610Q411/ML610Q412 Electrical Characteristics of Successive Approximation Type A/D Converter (VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Resolution n ⎯ ⎯ ⎯ 12 bit 2.7V ≤ VREF ≤ 3.6V −4 ⎯ +4 Integral non-linearity error IDL 2.2V ≤ VREF ≤ 2.7V −6 ⎯ +6 2.7V ≤ VREF ≤ 3.6V −3 ⎯ +3 Differential non-linearity error LSB DNL 2.2V ≤ VREF ≤ 2.7V −5 ⎯ +5 Zero-scale error VOFF ⎯ −6 ⎯ +6 Full-scale error FSE ⎯ −6 ⎯ +6 Reference voltage VREF ⎯ 2.2 ⎯ AVDD V Conversion time ⎯ tCONV ⎯ 23*1 ⎯ φ/CH φ: Period of high-speed clock (HSCLK) 1 * : 2φ / CH is required as an interval time for each conversion in the case of consecutive A/D conversion. AVDD Reference voltage VREF VDD VDDL 10µF 1µF A 0.1µF − 1µF RI≤5kΩ + Analog input 0.1µF VDDX AIN0, AIN1 0.1µF VSS AVSS 33/36 FEDL610Q411-04 ML610Q411/ML610Q412 PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 34/36 FEDL610Q411-04 ML610Q411/ML610Q412 REVISION HISTORY Document No. Date FEDL610Q411-01 Jul.17,2010 FEDL610Q411-02 Mar.23,2011 FEDL610Q411-03 FEDL610Q411-04 Apr.15,2015 July.13,2015 Page Previous Current Edition Edition – 3, 4, 21 – 3, 4, 21 34 34 All 1~3 5 7 9 11 13 15 16 18~20 21 23 24 25 27 All 1~3 5 7 9 11 13 15 16 18~20 22 24 25 26 27 4 4 – 21 21 22 36 36 14 14 Description Formally edition 1 Add the explanation of ML610Q411PC. Replace the package dimension (Only the format is changed. Package size and material are not changed.) Change header and footer. Delete ML610Q415 and ML610Q411PC Change from "Shipment" to "Product name － Supported Function" Add CLOCK GENERATION CIRCUIT OPERATING CONDITIONS Change "RESET" to "Reset pulse width (PRST) " and "Power-on reset activation power rise time (TPOR) ". Change description in Note. Corrected a typo. -PAD No,”37” is corrected to “36”. -PAD No,”36” is corrected to “35”. 35/36 FEDL610Q411-04 ML610Q411/ML610Q412 Notes 1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing circuits for mass production. 4) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) The Products specified in this document are not designed to be radiation tolerant. 7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the recommended usage conditions and specifications contained herein. 10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Copyright 2010 – 2015 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/ 36/36