MR45V064BMAZAATL

Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor" and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd." Furthermore, there are no changes to the documents relating to our products other than the company name, the company trademark, logo, etc. Thank you for your understanding. LAPIS Technology Co., Ltd. October 1, 2020 FEDR45V064B-01 Issue Date: Jan 08, 2016 MR45V064B 64k(8,192-Word × 8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI GENERAL DESCRIPTION The MR45V064B is a nonvolatile 8,192-word x 8-bit ferroelectric random access memory (FeRAM) developed in the ferroelectric process and silicon-gate CMOS technology. The MR45V064B is accessed using Serial Peripheral Interface.Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. The MR45V064B can be used in various applications, because the device is guaranteed for the write/read tolerance of 1012 cycles per bit and the rewrite count can be extended significantly. FEATURES • • • • • • • 8,192-word × 8-bit configuration (Serial Peripheral Interface : SPI) A single 1.8V to 3.6V （3.3 V typ） power supply Operating frequency: 40MHz Read/write tolerance 1012 cycles/bit Data retention 10 years Guaranteed operating temperature range −40 to 85°C (Extended temperature version) Package options: 8-pin plastic SOP (P-SOP8-200-1.27-T2K) 1/20 FEDR45V064B-01 MR45V064B PIN CONFIGURATION 8-pin plastic SOP 1 SO 2 WP# 3 VSS 4 MR45V064B CS# 8 VCC 7 HOLD# 6 SCK 5 SI Note: Signal names that end with # indicate that the signals are negative-true logic. PIN DESCRIPTIONS Pin Name CS# Description Chip Select (input, negative logic) Latches an address by low input, activates the FeRAM, and enables a read or write operation. Write Protect( input , negative logic ) WP# Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should be fixed low or high in write-operations. HOLD( input , negative logic ) HOLD# Hold pin is used when the serial-communication suspended without disable the chip select. When HOLD# is low ,the serial-output is in High-Z status and serial-input/serial-clock are “Don’t Care” . CS# should be low in hold operation. Serial Clock SCK SI SO VCC, VSS Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on the rising edge and output occur on the falling edge. Serial input SI pins are serial input pins for Operation-code , addresses ,and data-inputs . Serial output SO pins are serial output pins. Power supply Apply the specified voltage to VCC. Connect VSS to ground. 2/20 FEDR45V064B-01 MR45V064B SPIMODE SPI mode0（CPOL=0, CPHA=0） CS# SCK SI MSB LSB SPI mode3（CPOL=1, CPHA=1） CS# SCK SI MSB LSB STATUS REGISTER b7 b0 SRWD 0 0 0 BP1 BP0 WEL WIP Status Register Write Disable Block Protect Bits Write Enable Latch Write In Progress (Always 0) Name Function WIP WEL BP0,BP1 Fixed to 0. Write Enable Latch. This indicates internal WEL condition. Block Protect: These bits can be changed protect area. This is the software protect. SRWD Status Register Write Disable （ SRWD ） : SRWD controls the effect of the hardware WP# pin. This device will be in hardware-protect by combination of SRWD and WP#. Fixed to 0. 0 3/20 FEDR45V064B-01 MR45V064B OPERATION-CODE Operation codes are listed in the table below.If the device receives invalid operation code,the device will be diselected. Instruction Description Instruction format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010 FSTRD Fast Read from Memory Array 0000 1011 RDID Read device ID 1001 1111 4/20 FEDR45V064B-01 MR45V064B COMMANDS WREN (Write Enable) It is necessary to set Write Enable Latch（WEL）bit before write-operation (WRITE and WRSR). WREN command sets WEL bit. CS# WP# Fixed “H” 0 1 2 3 4 5 6 7 SCK SI SO High-Z WRDI (Write Disable) WRDI command resets WEL bit. CS# WP# Fixed “H” 0 1 2 3 4 5 6 7 SCK SI SO High-Z 5/20 FEDR45V064B-01 MR45V064B RDSR (READ Status Register) The RDSR command allows to read data of status register. CS# WP# Fixed “H” 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 SRWD 0 0 0 SCK SI SO High-Z 7 BP1 BP0 WEL WIP SRWD WRSR (WRITE Status Register） WRSR command allows to write data to status register(SRWD,BP0,BP1). It is necessary to set Write Enable Latch（WEL）bit by WREN command before executing WRSR. CS# 0 1 2 3 4 5 6 7 8 9 10 11 7 6 5 4 SRWD X X X 12 13 14 15 3 2 1 0 X X SCK SI SO BP1 BP0 High-Z Note: WP#=Fix ”H” 6/20 FEDR45V064B-01 MR45V064B READ (Read from Memory Array) READ command can be valid when CS# goes “L”,then the op-code and 16bit-adresses are inputted to serial input”SI”. The inputted adresses are loaded to internal register,then the data from corresponded address is output at serial-output “SO”.If CS# will keep “L”,the internal adress will be incresed automatically after 8 clocks and will output the data from new-address.When it reaches the most significant adress,the adress counter rolls over tostarting adress,and reading cycle can be continued infinitely. CS# 0 1 2 3 4 5 6 7 8 9 10 15 14 13 11 12 21 22 23 12 11 2 1 0 A2 A1 A0 SCK SI X X A12 A11 X 16bit Address An SO High-Z CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 m Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q0 SCK SI SO Data Out (An) Data Out (An+1) Note : WP# = fixed ”H” FSTRD (Fast Read from Memory Array) FSTRD command can be valid when CS# goes “L”, then the op-code and 16bit-adresses are inputted to serial input ”SI”. After 8bits for dummy byte, the data from corresponded address is output at serial-output “SO”. CS# 0 1 2 3 4 5 6 7 8 9 10 15 14 13 X X X 11 12 12 11 21 22 23 SCK SI A12 A11 2 1 0 A2 A1 A0 16bit Address An SO High-Z CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 m Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q0 SCK SI SO Dummy Byte Data Out (An) Note : WP# = fixed ”H” 7/20 FEDR45V064B-01 MR45V064B WRITE (Write to Memory Array） Write command can be valid when CS# goes “L”,then the op-code and 16bit-adresses are inputted to serial input”SI”. Writing is terminated when CS# goes high after data-input. If CS# will keep “L”,the internal adress will be incresed automatically.When it reaches the most significant adress,the adress counter rolls over to starting adress 0000h,and writing cycle(overwriting) can be continued infinitely. WRITE (1Byte) CS# 0 1 2 3 4 5 6 7 8 9 10 15 14 13 X X X 11 12 12 11 21 22 23 SCK SI A12 A11 2 1 0 A2 A1 A0 16bit Address An CS# 24 25 26 27 28 29 30 31 D7 D6 D5 D4 D3 D2 D1 D0 4 5 6 SCK SI Data Byte 1 Note : WP# = Fixed ”H” , SO=High-Z WRITE (Page) CS# 0 1 2 3 7 8 9 10 11 12 21 22 23 15 14 13 12 11 2 1 0 X X X A2 A1 A0 SCK SI A12 A11 16bit Address An CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 SCK SI Data Byte 1 Data Byte 2 CS# 40 41 42 43 44 45 46 47 D7 D6 D5 D4 D3 D2 D1 D0 SCK SI Data Byte 3 D7 D6 D5 D4 D0 Data Byte N Note : WP# = Fixed ”H” , SO=High-Z 8/20 FEDR45V064B-01 MR45V064B WRITE PROTECTION Writing protection block is shown as follows: Protect Block size Block Protect BIT BP1 BP0 0 0 1 1 0 1 0 1 Protected Block None Upper 1/4 block Upper 1/2 block All Protected Address Area None 1800h – 1FFFh 1000h – 1FFFh 0000h – 1FFFh Writing Protect WP# 1 SRWD mode 0 0 0 1 1 0 1 Writing protection status in status register Protection status in memory Unprotected Protected blocks blocks Software protection (SPM) Status register is unprotected when WEL-bit is set by WREN command. BP0 and BP1 are unprotected. Protected Unprotected Hardware protection (HPM) Status register is protected. BP0 and BP1 are protected. Protected Unprotected 9/20 FEDR45V064B-01 MR45V064B HOLD Hold status is used for suspending serial comunication without disable the chip. SO becomes “High-Z” and SI is “Don’t care” during the hold status. It is necessary to keep CS#=L in hold status. Hold status Hold status SCK HOLD# RDID ( Read device ID) RDID command can be valid when CS# goes “L”,then the op-code are inputted to serial input”SI”. Then 3bytes of device ID is output at serial-output “SO”. Manufacture id ( LAPIS ) device type ( MR45V064B ) 1st Byte 2nd Byte 3rd Byte AEh 83h 05h CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 1 1 1 0 SCK SI 1st Byte SO 1 0 1 0 CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 1 0 1 SCK SI 2nd Byte SO 1 0 0 0 3rd Byte 0 0 1 1 0 0 0 0 0 Note : WP# = Fixed ”H” 10/20 FEDR45V064B-01 MR45V064B ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS The application of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may damage the device. Therefore, do not allow actual characteristics to exceed any one parameter ratings PIN VOLTAGES Parameter Pin Voltage (Input Signal) Pin Voltage (Input/Output Voltage) Power Supply Voltage Rating Symbol Unit Min. Max. VIN –0.5 VCC + 0.5 V VINQ, VOUTQ –0.5 VCC + 0.5 V VCC –0.5 4.0 V TEMPERATURE RANGE Parameter Storage Temperature (Extended Temperature Version) Operating Temperature (Extended Temperature Version) Symbol Rating Unit Min. Max. Tstg –55 125 °C Topr –40 85 °C Note OTHERS Parameter Power Dissipation Symbol Rating Note PD 1,000mW Ta=25°C 11/20 FEDR45V064B-01 MR45V064B RECOMMENDED OPERATING CONDITIONS POWER SUPPLY VOLTAGE [V] Symbol Min. Typ. Max. Power Supply Voltage VCC 1.8 3.3 3.6 Ground Voltage VSS 0 0 0 Parameter Note DC INPUT VOLTAGE [V] Symbol Min. Max. Input High Voltage VIH VCC x 0.7 VCC＋0.3 Input Low Voltage VIL –0.3 VCC x 0.3 Parameter Note OVERSHOOT/UNDERSHOOT TOLERANCE Symbol Pulse Width Peak “H” input VIH OVERSHOOT ≤ 20ns VCC+1.0V “L” input VIL UNDERSHOOT ≤ 20ns – 1.0V Parameter 12/20 FEDR45V064B-01 MR45V064B DC CHARACTERISTICS DC INPUT/OUTPUT CHARACTERISTICS Parameter Output High Voltage Symbol Condition VOH IOH =－2mA Min. Max. Unit Note VCC×0.85 ― V VCC≧2.0V VCC×0.80 ― V VCC